blob: 89b7eb82fc2ba14888516bbd81663c3ab22cc3e3 [file] [log] [blame]
Minghuan Lian62d0ff832014-11-05 16:45:11 +08001/*
2 * PCIe host controller driver for Freescale Layerscape SoCs
3 *
4 * Copyright (C) 2014 Freescale Semiconductor.
5 *
6 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
Minghuan Lian62d0ff832014-11-05 16:45:11 +080014#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/of_pci.h>
17#include <linux/of_platform.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/pci.h>
21#include <linux/platform_device.h>
22#include <linux/resource.h>
23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
25
26#include "pcie-designware.h"
27
28/* PEX1/2 Misc Ports Status Register */
29#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
30#define LTSSM_STATE_SHIFT 20
31#define LTSSM_STATE_MASK 0x3f
32#define LTSSM_PCIE_L0 0x11 /* L0 state */
33
34/* Symbol Timer Register and Filter Mask Register 1 */
35#define PCIE_STRFMR1 0x71c
36
Minghuan Liand6463342015-10-16 15:19:17 +080037struct ls_pcie_drvdata {
38 struct pcie_host_ops *ops;
39};
40
Minghuan Lian62d0ff832014-11-05 16:45:11 +080041struct ls_pcie {
42 struct list_head node;
43 struct device *dev;
44 struct pci_bus *bus;
45 void __iomem *dbi;
46 struct regmap *scfg;
47 struct pcie_port pp;
Minghuan Liand6463342015-10-16 15:19:17 +080048 const struct ls_pcie_drvdata *drvdata;
Minghuan Lian62d0ff832014-11-05 16:45:11 +080049 int index;
50 int msi_irq;
51};
52
53#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
54
Minghuan Lian7af4ce32015-10-16 15:19:16 +080055static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
56{
57 u32 header_type;
58
59 header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
60 header_type &= 0x7f;
61
62 return header_type == PCI_HEADER_TYPE_BRIDGE;
63}
64
Minghuan Liand6463342015-10-16 15:19:17 +080065static int ls1021_pcie_link_up(struct pcie_port *pp)
Minghuan Lian62d0ff832014-11-05 16:45:11 +080066{
67 u32 state;
68 struct ls_pcie *pcie = to_ls_pcie(pp);
69
Minghuan Liand6463342015-10-16 15:19:17 +080070 if (!pcie->scfg)
71 return 0;
72
Minghuan Lian62d0ff832014-11-05 16:45:11 +080073 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
74 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
75
76 if (state < LTSSM_PCIE_L0)
77 return 0;
78
79 return 1;
80}
81
Minghuan Liand6463342015-10-16 15:19:17 +080082static void ls1021_pcie_host_init(struct pcie_port *pp)
Bjorn Helgaas1d3f9ba2015-06-02 16:24:25 -050083{
84 struct ls_pcie *pcie = to_ls_pcie(pp);
Minghuan Liand6463342015-10-16 15:19:17 +080085 u32 val, index[2];
86
87 pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
88 "fsl,pcie-scfg");
89 if (IS_ERR(pcie->scfg)) {
90 dev_err(pp->dev, "No syscfg phandle specified\n");
91 pcie->scfg = NULL;
92 return;
93 }
94
95 if (of_property_read_u32_array(pp->dev->of_node,
96 "fsl,pcie-scfg", index, 2)) {
97 pcie->scfg = NULL;
98 return;
99 }
100 pcie->index = index[1];
Bjorn Helgaas1d3f9ba2015-06-02 16:24:25 -0500101
102 dw_pcie_setup_rc(pp);
Bjorn Helgaas1d3f9ba2015-06-02 16:24:25 -0500103
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800104 /*
105 * LS1021A Workaround for internal TKT228622
106 * to fix the INTx hang issue
107 */
108 val = ioread32(pcie->dbi + PCIE_STRFMR1);
109 val &= 0xffff;
110 iowrite32(val, pcie->dbi + PCIE_STRFMR1);
111}
112
Minghuan Liand6463342015-10-16 15:19:17 +0800113static struct pcie_host_ops ls1021_pcie_host_ops = {
114 .link_up = ls1021_pcie_link_up,
115 .host_init = ls1021_pcie_host_init,
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800116};
117
Minghuan Liand6463342015-10-16 15:19:17 +0800118static struct ls_pcie_drvdata ls1021_drvdata = {
119 .ops = &ls1021_pcie_host_ops,
120};
121
122static const struct of_device_id ls_pcie_of_match[] = {
123 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
124 { },
125};
126MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
127
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800128static int ls_add_pcie_port(struct ls_pcie *pcie)
129{
130 struct pcie_port *pp;
131 int ret;
132
133 pp = &pcie->pp;
134 pp->dev = pcie->dev;
135 pp->dbi_base = pcie->dbi;
136 pp->root_bus_nr = -1;
Minghuan Liand6463342015-10-16 15:19:17 +0800137 pp->ops = pcie->drvdata->ops;
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800138
139 ret = dw_pcie_host_init(pp);
140 if (ret) {
141 dev_err(pp->dev, "failed to initialize host\n");
142 return ret;
143 }
144
145 return 0;
146}
147
148static int __init ls_pcie_probe(struct platform_device *pdev)
149{
Minghuan Liand6463342015-10-16 15:19:17 +0800150 const struct of_device_id *match;
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800151 struct ls_pcie *pcie;
152 struct resource *dbi_base;
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800153 int ret;
154
Minghuan Liand6463342015-10-16 15:19:17 +0800155 match = of_match_device(ls_pcie_of_match, &pdev->dev);
156 if (!match)
157 return -ENODEV;
158
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800159 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
160 if (!pcie)
161 return -ENOMEM;
162
163 pcie->dev = &pdev->dev;
164
165 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800166 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
Bjorn Helgaase3dc17a2015-04-09 14:36:52 -0500167 if (IS_ERR(pcie->dbi)) {
168 dev_err(&pdev->dev, "missing *regs* space\n");
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800169 return PTR_ERR(pcie->dbi);
Bjorn Helgaase3dc17a2015-04-09 14:36:52 -0500170 }
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800171
Minghuan Liand6463342015-10-16 15:19:17 +0800172 pcie->drvdata = match->data;
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800173
Minghuan Lian7af4ce32015-10-16 15:19:16 +0800174 if (!ls_pcie_is_bridge(pcie))
175 return -ENODEV;
176
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800177 ret = ls_add_pcie_port(pcie);
178 if (ret < 0)
179 return ret;
180
181 platform_set_drvdata(pdev, pcie);
182
183 return 0;
184}
185
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800186static struct platform_driver ls_pcie_driver = {
187 .driver = {
188 .name = "layerscape-pcie",
Minghuan Lian62d0ff832014-11-05 16:45:11 +0800189 .of_match_table = ls_pcie_of_match,
190 },
191};
192
193module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
194
195MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
196MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
197MODULE_LICENSE("GPL v2");