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Sascha Hauer295c08b2009-08-19 01:43:50 +02001/*
2 * Regulator Driver for Freescale MC13783 PMIC
3 *
Yong Shen167e3d82010-12-14 14:00:54 +08004 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
Sascha Hauer295c08b2009-08-19 01:43:50 +02005 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Alberto Panizzo1bd588f2009-12-14 18:26:38 +01006 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
Sascha Hauer295c08b2009-08-19 01:43:50 +02007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +010013#include <linux/mfd/mc13783.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020014#include <linux/regulator/machine.h>
15#include <linux/regulator/driver.h>
16#include <linux/platform_device.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020017#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020019#include <linux/init.h>
20#include <linux/err.h>
Paul Gortmaker65602c32011-07-17 16:28:23 -040021#include <linux/module.h>
Yong Shen167e3d82010-12-14 14:00:54 +080022#include "mc13xxx.h"
Sascha Hauer295c08b2009-08-19 01:43:50 +020023
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +020024#define MC13783_REG_SWITCHERS0 24
25/* Enable does not exist for SW1A */
26#define MC13783_REG_SWITCHERS0_SW1AEN 0
27#define MC13783_REG_SWITCHERS0_SW1AVSEL 0
28#define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0)
29
30#define MC13783_REG_SWITCHERS1 25
31/* Enable does not exist for SW1B */
32#define MC13783_REG_SWITCHERS1_SW1BEN 0
33#define MC13783_REG_SWITCHERS1_SW1BVSEL 0
34#define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0)
35
36#define MC13783_REG_SWITCHERS2 26
37/* Enable does not exist for SW2A */
38#define MC13783_REG_SWITCHERS2_SW2AEN 0
39#define MC13783_REG_SWITCHERS2_SW2AVSEL 0
40#define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0)
41
42#define MC13783_REG_SWITCHERS3 27
43/* Enable does not exist for SW2B */
44#define MC13783_REG_SWITCHERS3_SW2BEN 0
45#define MC13783_REG_SWITCHERS3_SW2BVSEL 0
46#define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0)
47
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +010048#define MC13783_REG_SWITCHERS5 29
49#define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +010050#define MC13783_REG_SWITCHERS5_SW3VSEL 18
51#define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
52
53#define MC13783_REG_REGULATORSETTING0 30
54#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
55#define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
56#define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
57#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
58#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
59#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
60#define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
61#define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
62#define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
63
64#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
65#define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
66#define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
67#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
68#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
69#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
70#define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
71#define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
72#define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
73
74#define MC13783_REG_REGULATORSETTING1 31
75#define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
76#define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
77#define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
78#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
79#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
80
81#define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
82#define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
83#define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
84#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
85#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +010086
87#define MC13783_REG_REGULATORMODE0 32
88#define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
89#define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
90#define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
91#define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
92#define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
93#define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
94#define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
95#define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
96
97#define MC13783_REG_REGULATORMODE1 33
98#define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
99#define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
100#define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
101#define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
102#define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
103#define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
104#define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
105#define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
106#define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
107
108#define MC13783_REG_POWERMISC 34
109#define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
110#define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
111#define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
112#define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100113#define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
114#define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
115
116#define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
117
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100118
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100119/* Voltage Values */
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +0200120static const int mc13783_sw1x_val[] = {
121 900000, 925000, 950000, 975000,
122 1000000, 1025000, 1050000, 1075000,
123 1100000, 1125000, 1150000, 1175000,
124 1200000, 1225000, 1250000, 1275000,
125 1300000, 1325000, 1350000, 1375000,
126 1400000, 1425000, 1450000, 1475000,
127 1500000, 1525000, 1550000, 1575000,
128 1600000, 1625000, 1650000, 1675000,
129 1700000, 1700000, 1700000, 1700000,
130 1800000, 1800000, 1800000, 1800000,
131 1850000, 1850000, 1850000, 1850000,
132 2000000, 2000000, 2000000, 2000000,
133 2100000, 2100000, 2100000, 2100000,
134 2200000, 2200000, 2200000, 2200000,
135 2200000, 2200000, 2200000, 2200000,
136 2200000, 2200000, 2200000, 2200000,
137};
138
139static const int mc13783_sw2x_val[] = {
140 900000, 925000, 950000, 975000,
141 1000000, 1025000, 1050000, 1075000,
142 1100000, 1125000, 1150000, 1175000,
143 1200000, 1225000, 1250000, 1275000,
144 1300000, 1325000, 1350000, 1375000,
145 1400000, 1425000, 1450000, 1475000,
146 1500000, 1525000, 1550000, 1575000,
147 1600000, 1625000, 1650000, 1675000,
148 1700000, 1700000, 1700000, 1700000,
149 1800000, 1800000, 1800000, 1800000,
150 1900000, 1900000, 1900000, 1900000,
151 2000000, 2000000, 2000000, 2000000,
152 2100000, 2100000, 2100000, 2100000,
153 2200000, 2200000, 2200000, 2200000,
154 2200000, 2200000, 2200000, 2200000,
155 2200000, 2200000, 2200000, 2200000,
156};
157
Axel Lin34e74f32012-06-08 15:41:48 +0800158static const unsigned int mc13783_sw3_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100159 5000000, 5000000, 5000000, 5500000,
160};
161
Axel Lin34e74f32012-06-08 15:41:48 +0800162static const unsigned int mc13783_vaudio_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100163 2775000,
164};
165
Axel Lin34e74f32012-06-08 15:41:48 +0800166static const unsigned int mc13783_viohi_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100167 2775000,
168};
169
Axel Lin34e74f32012-06-08 15:41:48 +0800170static const unsigned int mc13783_violo_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100171 1200000, 1300000, 1500000, 1800000,
172};
173
Axel Lin34e74f32012-06-08 15:41:48 +0800174static const unsigned int mc13783_vdig_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100175 1200000, 1300000, 1500000, 1800000,
176};
177
Axel Lin34e74f32012-06-08 15:41:48 +0800178static const unsigned int mc13783_vgen_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100179 1200000, 1300000, 1500000, 1800000,
180 1100000, 2000000, 2775000, 2400000,
181};
182
Axel Lin34e74f32012-06-08 15:41:48 +0800183static const unsigned int mc13783_vrfdig_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100184 1200000, 1500000, 1800000, 1875000,
185};
186
Axel Lin34e74f32012-06-08 15:41:48 +0800187static const unsigned int mc13783_vrfref_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100188 2475000, 2600000, 2700000, 2775000,
189};
190
Axel Lin34e74f32012-06-08 15:41:48 +0800191static const unsigned int mc13783_vrfcp_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100192 2700000, 2775000,
193};
194
Axel Lin34e74f32012-06-08 15:41:48 +0800195static const unsigned int mc13783_vsim_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100196 1800000, 2900000, 3000000,
197};
198
Axel Lin34e74f32012-06-08 15:41:48 +0800199static const unsigned int mc13783_vesim_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100200 1800000, 2900000,
201};
202
Axel Lin34e74f32012-06-08 15:41:48 +0800203static const unsigned int mc13783_vcam_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100204 1500000, 1800000, 2500000, 2550000,
205 2600000, 2750000, 2800000, 3000000,
206};
207
Axel Lin34e74f32012-06-08 15:41:48 +0800208static const unsigned int mc13783_vrfbg_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100209 1250000,
210};
211
Axel Lin34e74f32012-06-08 15:41:48 +0800212static const unsigned int mc13783_vvib_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100213 1300000, 1800000, 2000000, 3000000,
214};
215
Axel Lin34e74f32012-06-08 15:41:48 +0800216static const unsigned int mc13783_vmmc_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100217 1600000, 1800000, 2000000, 2600000,
218 2700000, 2800000, 2900000, 3000000,
219};
220
Axel Lin34e74f32012-06-08 15:41:48 +0800221static const unsigned int mc13783_vrf_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100222 1500000, 1875000, 2700000, 2775000,
Sascha Hauer295c08b2009-08-19 01:43:50 +0200223};
224
Axel Lin34e74f32012-06-08 15:41:48 +0800225static const unsigned int mc13783_gpo_val[] = {
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100226 3100000,
227};
228
Axel Lin34e74f32012-06-08 15:41:48 +0800229static const unsigned int mc13783_pwgtdrv_val[] = {
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100230 5500000,
231};
232
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100233static struct regulator_ops mc13783_gpo_regulator_ops;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200234
Yong Shen167e3d82010-12-14 14:00:54 +0800235#define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages) \
236 MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \
237 mc13xxx_regulator_ops)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100238
Yong Shen167e3d82010-12-14 14:00:54 +0800239#define MC13783_FIXED_DEFINE(prefix, name, reg, voltages) \
240 MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \
241 mc13xxx_fixed_regulator_ops)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100242
Yong Shen167e3d82010-12-14 14:00:54 +0800243#define MC13783_GPO_DEFINE(prefix, name, reg, voltages) \
244 MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \
245 mc13783_gpo_regulator_ops)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100246
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100247#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \
Yong Shen57c78e32010-12-14 14:00:53 +0800248 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100249#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \
Yong Shen57c78e32010-12-14 14:00:53 +0800250 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100251
Yong Shen167e3d82010-12-14 14:00:54 +0800252static struct mc13xxx_regulator mc13783_regulators[] = {
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +0200253 MC13783_DEFINE_SW(SW1A, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
254 MC13783_DEFINE_SW(SW1B, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
255 MC13783_DEFINE_SW(SW2A, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
256 MC13783_DEFINE_SW(SW2B, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100257 MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100258
Yong Shen57c78e32010-12-14 14:00:53 +0800259 MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
260 MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900261 MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100262 mc13783_violo_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900263 MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100264 mc13783_vdig_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900265 MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100266 mc13783_vgen_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900267 MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100268 mc13783_vrfdig_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900269 MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100270 mc13783_vrfref_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900271 MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100272 mc13783_vrfcp_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900273 MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100274 mc13783_vsim_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900275 MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100276 mc13783_vesim_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900277 MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100278 mc13783_vcam_val),
Yong Shen57c78e32010-12-14 14:00:53 +0800279 MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900280 MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100281 mc13783_vvib_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900282 MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100283 mc13783_vrf_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900284 MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100285 mc13783_vrf_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900286 MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100287 mc13783_vmmc_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900288 MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100289 mc13783_vmmc_val),
Yong Shen57c78e32010-12-14 14:00:53 +0800290 MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
291 MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
292 MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
293 MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
294 MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
295 MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),
Sascha Hauer295c08b2009-08-19 01:43:50 +0200296};
297
Yong Shen167e3d82010-12-14 14:00:54 +0800298static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
299 u32 val)
Sascha Hauer295c08b2009-08-19 01:43:50 +0200300{
Yong Shen167e3d82010-12-14 14:00:54 +0800301 struct mc13xxx *mc13783 = priv->mc13xxx;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100302 int ret;
303 u32 valread;
304
305 BUG_ON(val & ~mask);
306
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800307 mc13xxx_lock(priv->mc13xxx);
Yong Shen167e3d82010-12-14 14:00:54 +0800308 ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100309 if (ret)
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800310 goto out;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100311
312 /* Update the stored state for Power Gates. */
313 priv->powermisc_pwgt_state =
314 (priv->powermisc_pwgt_state & ~mask) | val;
315 priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
316
317 /* Construct the new register value */
318 valread = (valread & ~mask) | val;
319 /* Overwrite the PWGTxEN with the stored version */
320 valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
321 priv->powermisc_pwgt_state;
322
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800323 ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
324out:
325 mc13xxx_unlock(priv->mc13xxx);
326 return ret;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100327}
328
329static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
330{
Yong Shen167e3d82010-12-14 14:00:54 +0800331 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
332 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100333 int id = rdev_get_id(rdev);
Yong Shen167e3d82010-12-14 14:00:54 +0800334 u32 en_val = mc13xxx_regulators[id].enable_bit;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100335
336 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
337
338 /* Power Gate enable value is 0 */
Yong Shen57c78e32010-12-14 14:00:53 +0800339 if (id == MC13783_REG_PWGT1SPI ||
340 id == MC13783_REG_PWGT2SPI)
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100341 en_val = 0;
342
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800343 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100344 en_val);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100345}
346
347static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
348{
Yong Shen167e3d82010-12-14 14:00:54 +0800349 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
350 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100351 int id = rdev_get_id(rdev);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100352 u32 dis_val = 0;
353
354 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
355
356 /* Power Gate disable value is 1 */
Yong Shen57c78e32010-12-14 14:00:53 +0800357 if (id == MC13783_REG_PWGT1SPI ||
358 id == MC13783_REG_PWGT2SPI)
Yong Shen167e3d82010-12-14 14:00:54 +0800359 dis_val = mc13xxx_regulators[id].enable_bit;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100360
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800361 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100362 dis_val);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100363}
364
365static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
366{
Yong Shen167e3d82010-12-14 14:00:54 +0800367 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
368 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100369 int ret, id = rdev_get_id(rdev);
370 unsigned int val;
371
Yong Shen167e3d82010-12-14 14:00:54 +0800372 mc13xxx_lock(priv->mc13xxx);
373 ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
374 mc13xxx_unlock(priv->mc13xxx);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100375
376 if (ret)
377 return ret;
378
379 /* Power Gates state is stored in powermisc_pwgt_state
380 * where the meaning of bits is negated */
381 val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
382 (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
383
Yong Shen167e3d82010-12-14 14:00:54 +0800384 return (val & mc13xxx_regulators[id].enable_bit) != 0;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100385}
386
387static struct regulator_ops mc13783_gpo_regulator_ops = {
388 .enable = mc13783_gpo_regulator_enable,
389 .disable = mc13783_gpo_regulator_disable,
390 .is_enabled = mc13783_gpo_regulator_is_enabled,
Axel Lin34e74f32012-06-08 15:41:48 +0800391 .list_voltage = regulator_list_voltage_table,
Yong Shen167e3d82010-12-14 14:00:54 +0800392 .set_voltage = mc13xxx_fixed_regulator_set_voltage,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100393};
394
Bill Pembertona5023572012-11-19 13:22:22 -0500395static int mc13783_regulator_probe(struct platform_device *pdev)
Sascha Hauer295c08b2009-08-19 01:43:50 +0200396{
Yong Shen167e3d82010-12-14 14:00:54 +0800397 struct mc13xxx_regulator_priv *priv;
398 struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
Samuel Ortiz8f1585a2011-09-19 11:33:17 +0200399 struct mc13xxx_regulator_platform_data *pdata =
Samuel Ortizc8a03c92011-04-08 01:55:01 +0200400 dev_get_platdata(&pdev->dev);
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400401 struct mc13xxx_regulator_init_data *mc13xxx_data;
Axel Lina9d58012012-04-10 13:51:06 +0800402 struct regulator_config config = { };
Sachin Kamat8e568632013-09-04 12:00:59 +0530403 int i, num_regulators;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200404
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400405 num_regulators = mc13xxx_get_num_regulators_dt(pdev);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200406
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400407 if (num_regulators <= 0 && pdata)
408 num_regulators = pdata->num_regulators;
409 if (num_regulators <= 0)
Sascha Hauer0757b602012-02-29 09:01:40 +0100410 return -EINVAL;
411
Fabio Estevamcbe10a32011-12-29 13:56:02 -0200412 priv = devm_kzalloc(&pdev->dev, sizeof(*priv) +
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400413 num_regulators * sizeof(priv->regulators[0]),
Sascha Hauer295c08b2009-08-19 01:43:50 +0200414 GFP_KERNEL);
415 if (!priv)
416 return -ENOMEM;
417
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400418 priv->num_regulators = num_regulators;
Yong Shen167e3d82010-12-14 14:00:54 +0800419 priv->mc13xxx_regulators = mc13783_regulators;
420 priv->mc13xxx = mc13783;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400421 platform_set_drvdata(pdev, priv);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200422
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400423 mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
424 ARRAY_SIZE(mc13783_regulators));
425
426 for (i = 0; i < priv->num_regulators; i++) {
427 struct regulator_init_data *init_data;
Axel Lina9d58012012-04-10 13:51:06 +0800428 struct regulator_desc *desc;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400429 struct device_node *node = NULL;
430 int id;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200431
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400432 if (mc13xxx_data) {
433 id = mc13xxx_data[i].id;
434 init_data = mc13xxx_data[i].init_data;
435 node = mc13xxx_data[i].node;
436 } else {
437 id = pdata->regulators[i].id;
438 init_data = pdata->regulators[i].init_data;
439 }
440 desc = &mc13783_regulators[id].desc;
Axel Lina9d58012012-04-10 13:51:06 +0800441
442 config.dev = &pdev->dev;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400443 config.init_data = init_data;
Axel Lina9d58012012-04-10 13:51:06 +0800444 config.driver_data = priv;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400445 config.of_node = node;
Axel Lina9d58012012-04-10 13:51:06 +0800446
Sachin Kamat8e568632013-09-04 12:00:59 +0530447 priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
448 &config);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200449 if (IS_ERR(priv->regulators[i])) {
450 dev_err(&pdev->dev, "failed to register regulator %s\n",
451 mc13783_regulators[i].desc.name);
Sachin Kamat8e568632013-09-04 12:00:59 +0530452 return PTR_ERR(priv->regulators[i]);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200453 }
454 }
455
Sascha Hauer295c08b2009-08-19 01:43:50 +0200456 return 0;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200457}
458
459static struct platform_driver mc13783_regulator_driver = {
460 .driver = {
461 .name = "mc13783-regulator",
Sascha Hauer295c08b2009-08-19 01:43:50 +0200462 },
Alberto Panizzo735eb932009-12-14 18:53:35 +0100463 .probe = mc13783_regulator_probe,
Sascha Hauer295c08b2009-08-19 01:43:50 +0200464};
465
466static int __init mc13783_regulator_init(void)
467{
Alberto Panizzo735eb932009-12-14 18:53:35 +0100468 return platform_driver_register(&mc13783_regulator_driver);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200469}
470subsys_initcall(mc13783_regulator_init);
471
472static void __exit mc13783_regulator_exit(void)
473{
474 platform_driver_unregister(&mc13783_regulator_driver);
475}
476module_exit(mc13783_regulator_exit);
477
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100478MODULE_LICENSE("GPL v2");
Axel Lin1dcc4342010-05-06 11:33:36 +0800479MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Sascha Hauer295c08b2009-08-19 01:43:50 +0200480MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
481MODULE_ALIAS("platform:mc13783-regulator");