blob: d72a71bff218553106f69d489cf7caf34ed59b9a [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <drm/drmP.h>
34#include "radeon_drm.h"
35#include "radeon.h"
36
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037
38int radeon_ttm_init(struct radeon_device *rdev);
39void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010040static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
42/*
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
45 */
46
Jerome Glisse4c788672009-11-20 14:29:23 +010047static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020048{
Jerome Glisse4c788672009-11-20 14:29:23 +010049 struct radeon_bo *bo;
50
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
56 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057}
58
Jerome Glissed03d8582009-12-14 21:02:09 +010059bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
60{
61 if (bo->destroy == &radeon_ttm_bo_destroy)
62 return true;
63 return false;
64}
65
Jerome Glisse312ea8d2009-12-07 15:52:58 +010066void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
67{
68 u32 c = 0;
69
70 rbo->placement.fpfn = 0;
71 rbo->placement.lpfn = 0;
72 rbo->placement.placement = rbo->placements;
73 rbo->placement.busy_placement = rbo->placements;
74 if (domain & RADEON_GEM_DOMAIN_VRAM)
75 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
76 TTM_PL_FLAG_VRAM;
77 if (domain & RADEON_GEM_DOMAIN_GTT)
78 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
79 if (domain & RADEON_GEM_DOMAIN_CPU)
80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse9fb03e62009-12-11 15:13:22 +010081 if (!c)
82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010083 rbo->placement.num_placement = c;
84 rbo->placement.num_busy_placement = c;
85}
86
Jerome Glisse4c788672009-11-20 14:29:23 +010087int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
88 unsigned long size, bool kernel, u32 domain,
89 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090{
Jerome Glisse4c788672009-11-20 14:29:23 +010091 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020092 enum ttm_bo_type type;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020093 int r;
94
95 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
96 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
97 }
98 if (kernel) {
99 type = ttm_bo_type_kernel;
100 } else {
101 type = ttm_bo_type_device;
102 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100103 *bo_ptr = NULL;
104 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
105 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200106 return -ENOMEM;
Jerome Glisse4c788672009-11-20 14:29:23 +0100107 bo->rdev = rdev;
108 bo->gobj = gobj;
109 bo->surface_reg = -1;
110 INIT_LIST_HEAD(&bo->list);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200111
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100112 radeon_ttm_placement_from_domain(bo, domain);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100113 /* Kernel allocation are uninterruptible */
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100114 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
115 &bo->placement, 0, 0, !kernel, NULL, size,
116 &radeon_ttm_bo_destroy);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200117 if (unlikely(r != 0)) {
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100118 if (r != -ERESTARTSYS)
119 dev_err(rdev->dev,
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100120 "object_init failed for (%lu, 0x%08X)\n",
121 size, domain);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 return r;
123 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100124 *bo_ptr = bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200125 if (gobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100126 mutex_lock(&bo->rdev->gem.mutex);
127 list_add_tail(&bo->list, &rdev->gem.objects);
128 mutex_unlock(&bo->rdev->gem.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200129 }
130 return 0;
131}
132
Jerome Glisse4c788672009-11-20 14:29:23 +0100133int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200134{
Jerome Glisse4c788672009-11-20 14:29:23 +0100135 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200136 int r;
137
Jerome Glisse4c788672009-11-20 14:29:23 +0100138 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200139 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100140 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200141 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 return 0;
143 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100144 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145 if (r) {
146 return r;
147 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100148 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200149 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100150 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200151 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100152 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153 return 0;
154}
155
Jerome Glisse4c788672009-11-20 14:29:23 +0100156void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157{
Jerome Glisse4c788672009-11-20 14:29:23 +0100158 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100160 bo->kptr = NULL;
161 radeon_bo_check_tiling(bo, 0, 0);
162 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163}
164
Jerome Glisse4c788672009-11-20 14:29:23 +0100165void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200166{
Jerome Glisse4c788672009-11-20 14:29:23 +0100167 struct ttm_buffer_object *tbo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200168
Jerome Glisse4c788672009-11-20 14:29:23 +0100169 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100171 tbo = &((*bo)->tbo);
172 ttm_bo_unref(&tbo);
173 if (tbo == NULL)
174 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200175}
176
Jerome Glisse4c788672009-11-20 14:29:23 +0100177int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200178{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100179 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100181 radeon_ttm_placement_from_domain(bo, domain);
Jerome Glisse4c788672009-11-20 14:29:23 +0100182 if (bo->pin_count) {
183 bo->pin_count++;
184 if (gpu_addr)
185 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200186 return 0;
187 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100188 radeon_ttm_placement_from_domain(bo, domain);
189 for (i = 0; i < bo->placement.num_placement; i++)
190 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100191 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100192 if (likely(r == 0)) {
193 bo->pin_count = 1;
194 if (gpu_addr != NULL)
195 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100197 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100198 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 return r;
200}
201
Jerome Glisse4c788672009-11-20 14:29:23 +0100202int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100204 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205
Jerome Glisse4c788672009-11-20 14:29:23 +0100206 if (!bo->pin_count) {
207 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
208 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100210 bo->pin_count--;
211 if (bo->pin_count)
212 return 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100213 for (i = 0; i < bo->placement.num_placement; i++)
214 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100215 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100216 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100217 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100218 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219}
220
Jerome Glisse4c788672009-11-20 14:29:23 +0100221int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200222{
Dave Airlied796d842010-01-25 13:08:08 +1000223 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
224 if (0 && (rdev->flags & RADEON_IS_IGP)) {
Alex Deucher06b64762010-01-05 11:27:29 -0500225 if (rdev->mc.igp_sideport_enabled == false)
226 /* Useless to evict on IGP chips */
227 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228 }
229 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
230}
231
Jerome Glisse4c788672009-11-20 14:29:23 +0100232void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200233{
Jerome Glisse4c788672009-11-20 14:29:23 +0100234 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235 struct drm_gem_object *gobj;
236
237 if (list_empty(&rdev->gem.objects)) {
238 return;
239 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100240 dev_err(rdev->dev, "Userspace still has active objects !\n");
241 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200242 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100243 gobj = bo->gobj;
244 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
245 gobj, bo, (unsigned long)gobj->size,
246 *((unsigned long *)&gobj->refcount));
247 mutex_lock(&bo->rdev->gem.mutex);
248 list_del_init(&bo->list);
249 mutex_unlock(&bo->rdev->gem.mutex);
250 radeon_bo_unref(&bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200251 gobj->driver_private = NULL;
252 drm_gem_object_unreference(gobj);
253 mutex_unlock(&rdev->ddev->struct_mutex);
254 }
255}
256
Jerome Glisse4c788672009-11-20 14:29:23 +0100257int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200258{
Jerome Glissea4d68272009-09-11 13:00:43 +0200259 /* Add an MTRR for the VRAM */
260 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
261 MTRR_TYPE_WRCOMB, 1);
262 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
263 rdev->mc.mc_vram_size >> 20,
264 (unsigned long long)rdev->mc.aper_size >> 20);
265 DRM_INFO("RAM width %dbits %cDR\n",
266 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200267 return radeon_ttm_init(rdev);
268}
269
Jerome Glisse4c788672009-11-20 14:29:23 +0100270void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200271{
272 radeon_ttm_fini(rdev);
273}
274
Jerome Glisse4c788672009-11-20 14:29:23 +0100275void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
276 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200277{
278 if (lobj->wdomain) {
279 list_add(&lobj->list, head);
280 } else {
281 list_add_tail(&lobj->list, head);
282 }
283}
284
Jerome Glisse4c788672009-11-20 14:29:23 +0100285int radeon_bo_list_reserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286{
Jerome Glisse4c788672009-11-20 14:29:23 +0100287 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200288 int r;
289
Dave Airlie9d8401f2009-10-08 09:28:19 +1000290 list_for_each_entry(lobj, head, list){
Jerome Glisse4c788672009-11-20 14:29:23 +0100291 r = radeon_bo_reserve(lobj->bo, false);
292 if (unlikely(r != 0))
293 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200294 }
295 return 0;
296}
297
Jerome Glisse4c788672009-11-20 14:29:23 +0100298void radeon_bo_list_unreserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200299{
Jerome Glisse4c788672009-11-20 14:29:23 +0100300 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200301
Dave Airlie9d8401f2009-10-08 09:28:19 +1000302 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100303 /* only unreserve object we successfully reserved */
304 if (radeon_bo_is_reserved(lobj->bo))
305 radeon_bo_unreserve(lobj->bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306 }
307}
308
Jerome Glisse4c788672009-11-20 14:29:23 +0100309int radeon_bo_list_validate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200310{
Jerome Glisse4c788672009-11-20 14:29:23 +0100311 struct radeon_bo_list *lobj;
312 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200313 struct radeon_fence *old_fence = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200314 int r;
315
Jerome Glisse4c788672009-11-20 14:29:23 +0100316 r = radeon_bo_list_reserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318 return r;
319 }
Dave Airlie9d8401f2009-10-08 09:28:19 +1000320 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100321 bo = lobj->bo;
322 if (!bo->pin_count) {
Michel Dänzer664f8652009-07-28 12:30:57 +0200323 if (lobj->wdomain) {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100324 radeon_ttm_placement_from_domain(bo,
325 lobj->wdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200326 } else {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100327 radeon_ttm_placement_from_domain(bo,
328 lobj->rdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200329 }
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100330 r = ttm_bo_validate(&bo->tbo, &bo->placement,
Jerome Glisse4c788672009-11-20 14:29:23 +0100331 true, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100332 if (unlikely(r))
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200333 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200334 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100335 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
336 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200337 if (fence) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100338 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
339 bo->tbo.sync_obj = radeon_fence_ref(fence);
340 bo->tbo.sync_obj_arg = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200341 }
342 if (old_fence) {
343 radeon_fence_unref(&old_fence);
344 }
345 }
346 return 0;
347}
348
Jerome Glisse4c788672009-11-20 14:29:23 +0100349void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200350{
Jerome Glisse4c788672009-11-20 14:29:23 +0100351 struct radeon_bo_list *lobj;
352 struct radeon_fence *old_fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200353
Jerome Glisse4c788672009-11-20 14:29:23 +0100354 if (fence)
355 list_for_each_entry(lobj, head, list) {
356 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
357 if (old_fence == fence) {
358 lobj->bo->tbo.sync_obj = NULL;
359 radeon_fence_unref(&old_fence);
360 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200361 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100362 radeon_bo_list_unreserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200363}
364
Jerome Glisse4c788672009-11-20 14:29:23 +0100365int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200366 struct vm_area_struct *vma)
367{
Jerome Glisse4c788672009-11-20 14:29:23 +0100368 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200369}
370
Dave Airlie550e2d92009-12-09 14:15:38 +1000371int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200372{
Jerome Glisse4c788672009-11-20 14:29:23 +0100373 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000374 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100375 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000376 int steal;
377 int i;
378
Jerome Glisse4c788672009-11-20 14:29:23 +0100379 BUG_ON(!atomic_read(&bo->tbo.reserved));
380
381 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000382 return 0;
383
Jerome Glisse4c788672009-11-20 14:29:23 +0100384 if (bo->surface_reg >= 0) {
385 reg = &rdev->surface_regs[bo->surface_reg];
386 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000387 goto out;
388 }
389
390 steal = -1;
391 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
392
393 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100394 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000395 break;
396
Jerome Glisse4c788672009-11-20 14:29:23 +0100397 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000398 if (old_object->pin_count == 0)
399 steal = i;
400 }
401
402 /* if we are all out */
403 if (i == RADEON_GEM_MAX_SURFACES) {
404 if (steal == -1)
405 return -ENOMEM;
406 /* find someone with a surface reg and nuke their BO */
407 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100408 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000409 /* blow away the mapping */
410 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100411 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000412 old_object->surface_reg = -1;
413 i = steal;
414 }
415
Jerome Glisse4c788672009-11-20 14:29:23 +0100416 bo->surface_reg = i;
417 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000418
419out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100420 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
421 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
422 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000423 return 0;
424}
425
Jerome Glisse4c788672009-11-20 14:29:23 +0100426static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000427{
Jerome Glisse4c788672009-11-20 14:29:23 +0100428 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000429 struct radeon_surface_reg *reg;
430
Jerome Glisse4c788672009-11-20 14:29:23 +0100431 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000432 return;
433
Jerome Glisse4c788672009-11-20 14:29:23 +0100434 reg = &rdev->surface_regs[bo->surface_reg];
435 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000436
Jerome Glisse4c788672009-11-20 14:29:23 +0100437 reg->bo = NULL;
438 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000439}
440
Jerome Glisse4c788672009-11-20 14:29:23 +0100441int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
442 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000443{
Jerome Glisse4c788672009-11-20 14:29:23 +0100444 int r;
445
446 r = radeon_bo_reserve(bo, false);
447 if (unlikely(r != 0))
448 return r;
449 bo->tiling_flags = tiling_flags;
450 bo->pitch = pitch;
451 radeon_bo_unreserve(bo);
452 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000453}
454
Jerome Glisse4c788672009-11-20 14:29:23 +0100455void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
456 uint32_t *tiling_flags,
457 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000458{
Jerome Glisse4c788672009-11-20 14:29:23 +0100459 BUG_ON(!atomic_read(&bo->tbo.reserved));
Dave Airliee024e112009-06-24 09:48:08 +1000460 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100461 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000462 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100463 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000464}
465
Jerome Glisse4c788672009-11-20 14:29:23 +0100466int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
467 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000468{
Jerome Glisse4c788672009-11-20 14:29:23 +0100469 BUG_ON(!atomic_read(&bo->tbo.reserved));
470
471 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000472 return 0;
473
474 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100475 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000476 return 0;
477 }
478
Jerome Glisse4c788672009-11-20 14:29:23 +0100479 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000480 if (!has_moved)
481 return 0;
482
Jerome Glisse4c788672009-11-20 14:29:23 +0100483 if (bo->surface_reg >= 0)
484 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000485 return 0;
486 }
487
Jerome Glisse4c788672009-11-20 14:29:23 +0100488 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000489 return 0;
490
Jerome Glisse4c788672009-11-20 14:29:23 +0100491 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000492}
493
494void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glissed03d8582009-12-14 21:02:09 +0100495 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000496{
Jerome Glissed03d8582009-12-14 21:02:09 +0100497 struct radeon_bo *rbo;
498 if (!radeon_ttm_bo_is_radeon_bo(bo))
499 return;
500 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100501 radeon_bo_check_tiling(rbo, 0, 1);
Dave Airliee024e112009-06-24 09:48:08 +1000502}
503
504void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
505{
Jerome Glissed03d8582009-12-14 21:02:09 +0100506 struct radeon_bo *rbo;
507 if (!radeon_ttm_bo_is_radeon_bo(bo))
508 return;
509 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100510 radeon_bo_check_tiling(rbo, 0, 0);
Dave Airliee024e112009-06-24 09:48:08 +1000511}