Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <linux/list.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include "radeon_drm.h" |
| 35 | #include "radeon.h" |
| 36 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | |
| 38 | int radeon_ttm_init(struct radeon_device *rdev); |
| 39 | void radeon_ttm_fini(struct radeon_device *rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 40 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
| 44 | * function are calling it. |
| 45 | */ |
| 46 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 47 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 49 | struct radeon_bo *bo; |
| 50 | |
| 51 | bo = container_of(tbo, struct radeon_bo, tbo); |
| 52 | mutex_lock(&bo->rdev->gem.mutex); |
| 53 | list_del_init(&bo->list); |
| 54 | mutex_unlock(&bo->rdev->gem.mutex); |
| 55 | radeon_bo_clear_surface_reg(bo); |
| 56 | kfree(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | } |
| 58 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 59 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
| 60 | { |
| 61 | if (bo->destroy == &radeon_ttm_bo_destroy) |
| 62 | return true; |
| 63 | return false; |
| 64 | } |
| 65 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 66 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
| 67 | { |
| 68 | u32 c = 0; |
| 69 | |
| 70 | rbo->placement.fpfn = 0; |
| 71 | rbo->placement.lpfn = 0; |
| 72 | rbo->placement.placement = rbo->placements; |
| 73 | rbo->placement.busy_placement = rbo->placements; |
| 74 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
| 75 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
| 76 | TTM_PL_FLAG_VRAM; |
| 77 | if (domain & RADEON_GEM_DOMAIN_GTT) |
| 78 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 79 | if (domain & RADEON_GEM_DOMAIN_CPU) |
| 80 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 9fb03e6 | 2009-12-11 15:13:22 +0100 | [diff] [blame] | 81 | if (!c) |
| 82 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 83 | rbo->placement.num_placement = c; |
| 84 | rbo->placement.num_busy_placement = c; |
| 85 | } |
| 86 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 87 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
| 88 | unsigned long size, bool kernel, u32 domain, |
| 89 | struct radeon_bo **bo_ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 91 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | enum ttm_bo_type type; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 93 | int r; |
| 94 | |
| 95 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 96 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 97 | } |
| 98 | if (kernel) { |
| 99 | type = ttm_bo_type_kernel; |
| 100 | } else { |
| 101 | type = ttm_bo_type_device; |
| 102 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 103 | *bo_ptr = NULL; |
| 104 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
| 105 | if (bo == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 106 | return -ENOMEM; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 107 | bo->rdev = rdev; |
| 108 | bo->gobj = gobj; |
| 109 | bo->surface_reg = -1; |
| 110 | INIT_LIST_HEAD(&bo->list); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 111 | |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 112 | radeon_ttm_placement_from_domain(bo, domain); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 113 | /* Kernel allocation are uninterruptible */ |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 114 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
| 115 | &bo->placement, 0, 0, !kernel, NULL, size, |
| 116 | &radeon_ttm_bo_destroy); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 117 | if (unlikely(r != 0)) { |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 118 | if (r != -ERESTARTSYS) |
| 119 | dev_err(rdev->dev, |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 120 | "object_init failed for (%lu, 0x%08X)\n", |
| 121 | size, domain); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | return r; |
| 123 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 124 | *bo_ptr = bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | if (gobj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 126 | mutex_lock(&bo->rdev->gem.mutex); |
| 127 | list_add_tail(&bo->list, &rdev->gem.objects); |
| 128 | mutex_unlock(&bo->rdev->gem.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 129 | } |
| 130 | return 0; |
| 131 | } |
| 132 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 133 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 134 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 135 | bool is_iomem; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 136 | int r; |
| 137 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 138 | if (bo->kptr) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 139 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 140 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 142 | return 0; |
| 143 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 144 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 145 | if (r) { |
| 146 | return r; |
| 147 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 148 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 149 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 150 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 152 | radeon_bo_check_tiling(bo, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 153 | return 0; |
| 154 | } |
| 155 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 156 | void radeon_bo_kunmap(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 158 | if (bo->kptr == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 160 | bo->kptr = NULL; |
| 161 | radeon_bo_check_tiling(bo, 0, 0); |
| 162 | ttm_bo_kunmap(&bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | } |
| 164 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 165 | void radeon_bo_unref(struct radeon_bo **bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 167 | struct ttm_buffer_object *tbo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 168 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 169 | if ((*bo) == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 171 | tbo = &((*bo)->tbo); |
| 172 | ttm_bo_unref(&tbo); |
| 173 | if (tbo == NULL) |
| 174 | *bo = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | } |
| 176 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 177 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 178 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 179 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 181 | radeon_ttm_placement_from_domain(bo, domain); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 182 | if (bo->pin_count) { |
| 183 | bo->pin_count++; |
| 184 | if (gpu_addr) |
| 185 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 186 | return 0; |
| 187 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 188 | radeon_ttm_placement_from_domain(bo, domain); |
| 189 | for (i = 0; i < bo->placement.num_placement; i++) |
| 190 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 191 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 192 | if (likely(r == 0)) { |
| 193 | bo->pin_count = 1; |
| 194 | if (gpu_addr != NULL) |
| 195 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | } |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 197 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 198 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | return r; |
| 200 | } |
| 201 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 202 | int radeon_bo_unpin(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 204 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 206 | if (!bo->pin_count) { |
| 207 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
| 208 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 210 | bo->pin_count--; |
| 211 | if (bo->pin_count) |
| 212 | return 0; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 213 | for (i = 0; i < bo->placement.num_placement; i++) |
| 214 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 215 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 216 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 217 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 218 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | } |
| 220 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 221 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | { |
Dave Airlie | d796d84 | 2010-01-25 13:08:08 +1000 | [diff] [blame^] | 223 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
| 224 | if (0 && (rdev->flags & RADEON_IS_IGP)) { |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 225 | if (rdev->mc.igp_sideport_enabled == false) |
| 226 | /* Useless to evict on IGP chips */ |
| 227 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | } |
| 229 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 230 | } |
| 231 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 232 | void radeon_bo_force_delete(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 233 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 234 | struct radeon_bo *bo, *n; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | struct drm_gem_object *gobj; |
| 236 | |
| 237 | if (list_empty(&rdev->gem.objects)) { |
| 238 | return; |
| 239 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 240 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
| 241 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | mutex_lock(&rdev->ddev->struct_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 243 | gobj = bo->gobj; |
| 244 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
| 245 | gobj, bo, (unsigned long)gobj->size, |
| 246 | *((unsigned long *)&gobj->refcount)); |
| 247 | mutex_lock(&bo->rdev->gem.mutex); |
| 248 | list_del_init(&bo->list); |
| 249 | mutex_unlock(&bo->rdev->gem.mutex); |
| 250 | radeon_bo_unref(&bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | gobj->driver_private = NULL; |
| 252 | drm_gem_object_unreference(gobj); |
| 253 | mutex_unlock(&rdev->ddev->struct_mutex); |
| 254 | } |
| 255 | } |
| 256 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 257 | int radeon_bo_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | { |
Jerome Glisse | a4d6827 | 2009-09-11 13:00:43 +0200 | [diff] [blame] | 259 | /* Add an MTRR for the VRAM */ |
| 260 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| 261 | MTRR_TYPE_WRCOMB, 1); |
| 262 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
| 263 | rdev->mc.mc_vram_size >> 20, |
| 264 | (unsigned long long)rdev->mc.aper_size >> 20); |
| 265 | DRM_INFO("RAM width %dbits %cDR\n", |
| 266 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | return radeon_ttm_init(rdev); |
| 268 | } |
| 269 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 270 | void radeon_bo_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | { |
| 272 | radeon_ttm_fini(rdev); |
| 273 | } |
| 274 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 275 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
| 276 | struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 277 | { |
| 278 | if (lobj->wdomain) { |
| 279 | list_add(&lobj->list, head); |
| 280 | } else { |
| 281 | list_add_tail(&lobj->list, head); |
| 282 | } |
| 283 | } |
| 284 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 285 | int radeon_bo_list_reserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 287 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | int r; |
| 289 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 290 | list_for_each_entry(lobj, head, list){ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 291 | r = radeon_bo_reserve(lobj->bo, false); |
| 292 | if (unlikely(r != 0)) |
| 293 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 294 | } |
| 295 | return 0; |
| 296 | } |
| 297 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 298 | void radeon_bo_list_unreserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 299 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 300 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 301 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 302 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 303 | /* only unreserve object we successfully reserved */ |
| 304 | if (radeon_bo_is_reserved(lobj->bo)) |
| 305 | radeon_bo_unreserve(lobj->bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 306 | } |
| 307 | } |
| 308 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 309 | int radeon_bo_list_validate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 311 | struct radeon_bo_list *lobj; |
| 312 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | struct radeon_fence *old_fence = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 314 | int r; |
| 315 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 316 | r = radeon_bo_list_reserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | if (unlikely(r != 0)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | return r; |
| 319 | } |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 320 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 321 | bo = lobj->bo; |
| 322 | if (!bo->pin_count) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 323 | if (lobj->wdomain) { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 324 | radeon_ttm_placement_from_domain(bo, |
| 325 | lobj->wdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 326 | } else { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 327 | radeon_ttm_placement_from_domain(bo, |
| 328 | lobj->rdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 329 | } |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 330 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 331 | true, false); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 332 | if (unlikely(r)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 333 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 334 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 335 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
| 336 | lobj->tiling_flags = bo->tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | if (fence) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 338 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; |
| 339 | bo->tbo.sync_obj = radeon_fence_ref(fence); |
| 340 | bo->tbo.sync_obj_arg = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 341 | } |
| 342 | if (old_fence) { |
| 343 | radeon_fence_unref(&old_fence); |
| 344 | } |
| 345 | } |
| 346 | return 0; |
| 347 | } |
| 348 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 349 | void radeon_bo_list_unvalidate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 350 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 351 | struct radeon_bo_list *lobj; |
| 352 | struct radeon_fence *old_fence; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 353 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 354 | if (fence) |
| 355 | list_for_each_entry(lobj, head, list) { |
| 356 | old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); |
| 357 | if (old_fence == fence) { |
| 358 | lobj->bo->tbo.sync_obj = NULL; |
| 359 | radeon_fence_unref(&old_fence); |
| 360 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 362 | radeon_bo_list_unreserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | } |
| 364 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 365 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 366 | struct vm_area_struct *vma) |
| 367 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 368 | return ttm_fbdev_mmap(vma, &bo->tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | } |
| 370 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 371 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 372 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 373 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 374 | struct radeon_surface_reg *reg; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 375 | struct radeon_bo *old_object; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 376 | int steal; |
| 377 | int i; |
| 378 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 379 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 380 | |
| 381 | if (!bo->tiling_flags) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 382 | return 0; |
| 383 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 384 | if (bo->surface_reg >= 0) { |
| 385 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 386 | i = bo->surface_reg; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 387 | goto out; |
| 388 | } |
| 389 | |
| 390 | steal = -1; |
| 391 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 392 | |
| 393 | reg = &rdev->surface_regs[i]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 394 | if (!reg->bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 395 | break; |
| 396 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 397 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 398 | if (old_object->pin_count == 0) |
| 399 | steal = i; |
| 400 | } |
| 401 | |
| 402 | /* if we are all out */ |
| 403 | if (i == RADEON_GEM_MAX_SURFACES) { |
| 404 | if (steal == -1) |
| 405 | return -ENOMEM; |
| 406 | /* find someone with a surface reg and nuke their BO */ |
| 407 | reg = &rdev->surface_regs[steal]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 408 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 409 | /* blow away the mapping */ |
| 410 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 411 | ttm_bo_unmap_virtual(&old_object->tbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 412 | old_object->surface_reg = -1; |
| 413 | i = steal; |
| 414 | } |
| 415 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 416 | bo->surface_reg = i; |
| 417 | reg->bo = bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 418 | |
| 419 | out: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 420 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
| 421 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, |
| 422 | bo->tbo.num_pages << PAGE_SHIFT); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 423 | return 0; |
| 424 | } |
| 425 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 426 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 427 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 428 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 429 | struct radeon_surface_reg *reg; |
| 430 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 431 | if (bo->surface_reg == -1) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 432 | return; |
| 433 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 434 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 435 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 436 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 437 | reg->bo = NULL; |
| 438 | bo->surface_reg = -1; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 439 | } |
| 440 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 441 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 442 | uint32_t tiling_flags, uint32_t pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 443 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 444 | int r; |
| 445 | |
| 446 | r = radeon_bo_reserve(bo, false); |
| 447 | if (unlikely(r != 0)) |
| 448 | return r; |
| 449 | bo->tiling_flags = tiling_flags; |
| 450 | bo->pitch = pitch; |
| 451 | radeon_bo_unreserve(bo); |
| 452 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 453 | } |
| 454 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 455 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 456 | uint32_t *tiling_flags, |
| 457 | uint32_t *pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 458 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 459 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 460 | if (tiling_flags) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 461 | *tiling_flags = bo->tiling_flags; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 462 | if (pitch) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 463 | *pitch = bo->pitch; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 464 | } |
| 465 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 466 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 467 | bool force_drop) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 468 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 469 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 470 | |
| 471 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 472 | return 0; |
| 473 | |
| 474 | if (force_drop) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 475 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 476 | return 0; |
| 477 | } |
| 478 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 479 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 480 | if (!has_moved) |
| 481 | return 0; |
| 482 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 483 | if (bo->surface_reg >= 0) |
| 484 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 485 | return 0; |
| 486 | } |
| 487 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 488 | if ((bo->surface_reg >= 0) && !has_moved) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 489 | return 0; |
| 490 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 491 | return radeon_bo_get_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 492 | } |
| 493 | |
| 494 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 495 | struct ttm_mem_reg *mem) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 496 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 497 | struct radeon_bo *rbo; |
| 498 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
| 499 | return; |
| 500 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 501 | radeon_bo_check_tiling(rbo, 0, 1); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
| 505 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 506 | struct radeon_bo *rbo; |
| 507 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
| 508 | return; |
| 509 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 510 | radeon_bo_check_tiling(rbo, 0, 0); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 511 | } |