Thierry Reding | 099a664 | 2015-09-09 15:29:22 +0200 | [diff] [blame] | 1 | if ARCH_TEGRA |
| 2 | |
| 3 | # 32-bit ARM SoCs |
| 4 | if ARM |
| 5 | |
| 6 | config ARCH_TEGRA_2x_SOC |
| 7 | bool "Enable support for Tegra20 family" |
| 8 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| 9 | select ARM_ERRATA_720789 |
| 10 | select ARM_ERRATA_754327 if SMP |
| 11 | select ARM_ERRATA_764369 if SMP |
| 12 | select PINCTRL_TEGRA20 |
| 13 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 14 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 15 | select TEGRA_TIMER |
| 16 | help |
| 17 | Support for NVIDIA Tegra AP20 and T20 processors, based on the |
| 18 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| 19 | |
| 20 | config ARCH_TEGRA_3x_SOC |
| 21 | bool "Enable support for Tegra30 family" |
| 22 | select ARM_ERRATA_754322 |
| 23 | select ARM_ERRATA_764369 if SMP |
| 24 | select PINCTRL_TEGRA30 |
| 25 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 26 | select TEGRA_TIMER |
| 27 | help |
| 28 | Support for NVIDIA Tegra T30 processor family, based on the |
| 29 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| 30 | |
| 31 | config ARCH_TEGRA_114_SOC |
| 32 | bool "Enable support for Tegra114 family" |
| 33 | select ARM_ERRATA_798181 if SMP |
Thierry Reding | 099a664 | 2015-09-09 15:29:22 +0200 | [diff] [blame] | 34 | select HAVE_ARM_ARCH_TIMER |
| 35 | select PINCTRL_TEGRA114 |
| 36 | select TEGRA_TIMER |
| 37 | help |
| 38 | Support for NVIDIA Tegra T114 processor family, based on the |
| 39 | ARM CortexA15MP CPU |
| 40 | |
| 41 | config ARCH_TEGRA_124_SOC |
| 42 | bool "Enable support for Tegra124 family" |
Thierry Reding | 099a664 | 2015-09-09 15:29:22 +0200 | [diff] [blame] | 43 | select HAVE_ARM_ARCH_TIMER |
| 44 | select PINCTRL_TEGRA124 |
| 45 | select TEGRA_TIMER |
| 46 | help |
| 47 | Support for NVIDIA Tegra T124 processor family, based on the |
| 48 | ARM CortexA15MP CPU |
| 49 | |
| 50 | endif |
| 51 | |
| 52 | # 64-bit ARM SoCs |
| 53 | if ARM64 |
| 54 | |
| 55 | config ARCH_TEGRA_132_SOC |
| 56 | bool "NVIDIA Tegra132 SoC" |
| 57 | select PINCTRL_TEGRA124 |
Thierry Reding | 099a664 | 2015-09-09 15:29:22 +0200 | [diff] [blame] | 58 | help |
| 59 | Enable support for NVIDIA Tegra132 SoC, based on the Denver |
| 60 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, |
| 61 | but contains an NVIDIA Denver CPU complex in place of |
| 62 | Tegra124's "4+1" Cortex-A15 CPU complex. |
| 63 | |
Thierry Reding | 9544595 | 2015-11-16 07:15:55 +0100 | [diff] [blame] | 64 | config ARCH_TEGRA_210_SOC |
| 65 | bool "NVIDIA Tegra210 SoC" |
| 66 | select PINCTRL_TEGRA210 |
Thierry Reding | 9544595 | 2015-11-16 07:15:55 +0100 | [diff] [blame] | 67 | help |
| 68 | Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, |
| 69 | the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 |
| 70 | cores in a switched configuration. It features a GPU of the Maxwell |
| 71 | architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 |
| 72 | and providing 256 CUDA cores. It supports hardware-accelerated en- |
| 73 | and decoding of various video standards including H.265, H.264 and |
| 74 | VP8 at 4K resolution and up to 60 fps. |
| 75 | |
| 76 | Besides the multimedia features it also comes with a variety of I/O |
| 77 | controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to |
| 78 | name only a few. |
| 79 | |
Thierry Reding | 099a664 | 2015-09-09 15:29:22 +0200 | [diff] [blame] | 80 | endif |
| 81 | endif |