Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / d8a944582da1a4d29a1487ff7f435643505a12a0 / . / arch / arm / mach-omap2 / opp2420_data.c
blob: 126a9396b3a8e9c8b39609c71e136c15a2aa2756 [file] [log] [blame]
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700[diff] [blame^]1/*
2 * opp2420_data.c - old-style "OPP" table for OMAP2420
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
12 * these combinations is via the 'ratio's' which the clocks operate with
13 * respect to each other. These ratio sets are for a given voltage/DPLL
14 * setting. All configurations can be described by a DPLL setting and a ratio
15 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
16 *
17 * 2430 differs from 2420 in that there are no more phase synchronizers used.
18 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
19 * 2430 (iva2.1, NOdsp, mdm)
20 *
21 * XXX Missing voltage data.
22 *
23 * THe format described in this file is deprecated. Once a reasonable
24 * OPP API exists, the data in this file should be converted to use it.
25 *
26 * This is technically part of the OMAP2xxx clock code.
27 */
28
29#include "opp2xxx.h"
30#include "sdrc.h"
31#include "clock.h"
32
33/*-------------------------------------------------------------------------
34 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
35 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
36 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
37 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
38 *
39 * Filling in table based on H4 boards and 2430-SDPs variants available.
40 * There are quite a few more rates combinations which could be defined.
41 *
42 * When multiple values are defined the start up will try and choose the
43 * fastest one. If a 'fast' value is defined, then automatically, the /2
44 * one should be included as it can be used. Generally having more that
45 * one fast set does not make sense, as static timings need to be changed
46 * to change the set. The exception is the bypass setting which is
47 * availble for low power bypass.
48 *
49 * Note: This table needs to be sorted, fastest to slowest.
50 *-------------------------------------------------------------------------*/
51const struct prcm_config omap2420_rate_table[] = {
52 /* PRCM I - FAST */
53 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
54 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
55 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
56 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
57 RATE_IN_242X},
58
59 /* PRCM II - FAST */
60 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
61 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
62 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
63 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
64 RATE_IN_242X},
65
66 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
67 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
68 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
69 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
70 RATE_IN_242X},
71
72 /* PRCM III - FAST */
73 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
74 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
75 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
76 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
77 RATE_IN_242X},
78
79 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
80 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
81 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
82 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
83 RATE_IN_242X},
84
85 /* PRCM II - SLOW */
86 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
87 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
88 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
89 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
90 RATE_IN_242X},
91
92 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
93 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
94 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
95 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
96 RATE_IN_242X},
97
98 /* PRCM III - SLOW */
99 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
100 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
101 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
102 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
103 RATE_IN_242X},
104
105 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
106 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
107 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
108 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
109 RATE_IN_242X},
110
111 /* PRCM-VII (boot-bypass) */
112 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
113 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
114 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
115 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
116 RATE_IN_242X},
117
118 /* PRCM-VII (boot-bypass) */
119 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
120 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
121 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
122 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
123 RATE_IN_242X},
124
125 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126};