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gerrit-public.fairphone.software / kernel / msm-4.19 / d8ce823fb34e6b50b1d9cb804c1067546eab9cee / . / arch / arm / boot / dts / imx6sl.dtsi
blob: 177d9e791a0155dd7db082b735baad8a27f6cd9b [file] [log] [blame]
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h>
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38 };
39
40 intc: interrupt-controller@00a01000 {
41 compatible = "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 interrupt-controller;
46 reg = <0x00a01000 0x1000>,
47 <0x00a00100 0x100>;
48 };
49
50 clocks {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ckil {
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 };
58
59 osc {
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63 };
64
65 soc {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "simple-bus";
69 interrupt-parent = <&intc>;
70 ranges;
71
72 L2: l2-cache@00a02000 {
73 compatible = "arm,pl310-cache";
74 reg = <0x00a02000 0x1000>;
75 interrupts = <0 92 0x04>;
76 cache-unified;
77 cache-level = <2>;
78 arm,tag-latency = <4 2 3>;
79 arm,data-latency = <4 2 3>;
80 };
81
82 pmu {
83 compatible = "arm,cortex-a9-pmu";
84 interrupts = <0 94 0x04>;
85 };
86
87 aips1: aips-bus@02000000 {
88 compatible = "fsl,aips-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x02000000 0x100000>;
92 ranges;
93
94 spba: spba-bus@02000000 {
95 compatible = "fsl,spba-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x02000000 0x40000>;
99 ranges;
100
101 spdif: spdif@02004000 {
102 reg = <0x02004000 0x4000>;
103 interrupts = <0 52 0x04>;
104 };
105
106 ecspi1: ecspi@02008000 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
110 reg = <0x02008000 0x4000>;
111 interrupts = <0 31 0x04>;
112 clocks = <&clks IMX6SL_CLK_ECSPI1>,
113 <&clks IMX6SL_CLK_ECSPI1>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 ecspi2: ecspi@0200c000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
122 reg = <0x0200c000 0x4000>;
123 interrupts = <0 32 0x04>;
124 clocks = <&clks IMX6SL_CLK_ECSPI2>,
125 <&clks IMX6SL_CLK_ECSPI2>;
126 clock-names = "ipg", "per";
127 status = "disabled";
128 };
129
130 ecspi3: ecspi@02010000 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
134 reg = <0x02010000 0x4000>;
135 interrupts = <0 33 0x04>;
136 clocks = <&clks IMX6SL_CLK_ECSPI3>,
137 <&clks IMX6SL_CLK_ECSPI3>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
141
142 ecspi4: ecspi@02014000 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
146 reg = <0x02014000 0x4000>;
147 interrupts = <0 34 0x04>;
148 clocks = <&clks IMX6SL_CLK_ECSPI4>,
149 <&clks IMX6SL_CLK_ECSPI4>;
150 clock-names = "ipg", "per";
151 status = "disabled";
152 };
153
154 uart5: serial@02018000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]155 compatible = "fsl,imx6sl-uart",
156 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]157 reg = <0x02018000 0x4000>;
158 interrupts = <0 30 0x04>;
159 clocks = <&clks IMX6SL_CLK_UART>,
160 <&clks IMX6SL_CLK_UART_SERIAL>;
161 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]162 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
163 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]164 status = "disabled";
165 };
166
167 uart1: serial@02020000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]168 compatible = "fsl,imx6sl-uart",
169 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>;
172 clocks = <&clks IMX6SL_CLK_UART>,
173 <&clks IMX6SL_CLK_UART_SERIAL>;
174 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]175 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
176 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]177 status = "disabled";
178 };
179
180 uart2: serial@02024000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]181 compatible = "fsl,imx6sl-uart",
182 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]183 reg = <0x02024000 0x4000>;
184 interrupts = <0 27 0x04>;
185 clocks = <&clks IMX6SL_CLK_UART>,
186 <&clks IMX6SL_CLK_UART_SERIAL>;
187 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]188 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
189 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]190 status = "disabled";
191 };
192
193 ssi1: ssi@02028000 {
194 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
195 reg = <0x02028000 0x4000>;
196 interrupts = <0 46 0x04>;
197 clocks = <&clks IMX6SL_CLK_SSI1>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]198 dmas = <&sdma 37 1 0>,
199 <&sdma 38 1 0>;
200 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]201 fsl,fifo-depth = <15>;
202 status = "disabled";
203 };
204
205 ssi2: ssi@0202c000 {
206 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
207 reg = <0x0202c000 0x4000>;
208 interrupts = <0 47 0x04>;
209 clocks = <&clks IMX6SL_CLK_SSI2>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]210 dmas = <&sdma 41 1 0>,
211 <&sdma 42 1 0>;
212 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]213 fsl,fifo-depth = <15>;
214 status = "disabled";
215 };
216
217 ssi3: ssi@02030000 {
218 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
219 reg = <0x02030000 0x4000>;
220 interrupts = <0 48 0x04>;
221 clocks = <&clks IMX6SL_CLK_SSI3>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]222 dmas = <&sdma 45 1 0>,
223 <&sdma 46 1 0>;
224 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]225 fsl,fifo-depth = <15>;
226 status = "disabled";
227 };
228
229 uart3: serial@02034000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]230 compatible = "fsl,imx6sl-uart",
231 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]232 reg = <0x02034000 0x4000>;
233 interrupts = <0 28 0x04>;
234 clocks = <&clks IMX6SL_CLK_UART>,
235 <&clks IMX6SL_CLK_UART_SERIAL>;
236 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]237 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
238 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]239 status = "disabled";
240 };
241
242 uart4: serial@02038000 {
Huang Shijie6eb85f92013-07-08 17:14:19 +0800[diff] [blame]243 compatible = "fsl,imx6sl-uart",
244 "fsl,imx6q-uart", "fsl,imx21-uart";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]245 reg = <0x02038000 0x4000>;
246 interrupts = <0 29 0x04>;
247 clocks = <&clks IMX6SL_CLK_UART>,
248 <&clks IMX6SL_CLK_UART_SERIAL>;
249 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]250 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
251 dma-names = "rx", "tx";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]252 status = "disabled";
253 };
254 };
255
256 pwm1: pwm@02080000 {
257 #pwm-cells = <2>;
258 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
259 reg = <0x02080000 0x4000>;
260 interrupts = <0 83 0x04>;
261 clocks = <&clks IMX6SL_CLK_PWM1>,
262 <&clks IMX6SL_CLK_PWM1>;
263 clock-names = "ipg", "per";
264 };
265
266 pwm2: pwm@02084000 {
267 #pwm-cells = <2>;
268 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
269 reg = <0x02084000 0x4000>;
270 interrupts = <0 84 0x04>;
271 clocks = <&clks IMX6SL_CLK_PWM2>,
272 <&clks IMX6SL_CLK_PWM2>;
273 clock-names = "ipg", "per";
274 };
275
276 pwm3: pwm@02088000 {
277 #pwm-cells = <2>;
278 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
279 reg = <0x02088000 0x4000>;
280 interrupts = <0 85 0x04>;
281 clocks = <&clks IMX6SL_CLK_PWM3>,
282 <&clks IMX6SL_CLK_PWM3>;
283 clock-names = "ipg", "per";
284 };
285
286 pwm4: pwm@0208c000 {
287 #pwm-cells = <2>;
288 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
289 reg = <0x0208c000 0x4000>;
290 interrupts = <0 86 0x04>;
291 clocks = <&clks IMX6SL_CLK_PWM4>,
292 <&clks IMX6SL_CLK_PWM4>;
293 clock-names = "ipg", "per";
294 };
295
296 gpt: gpt@02098000 {
297 compatible = "fsl,imx6sl-gpt";
298 reg = <0x02098000 0x4000>;
299 interrupts = <0 55 0x04>;
300 clocks = <&clks IMX6SL_CLK_GPT>,
301 <&clks IMX6SL_CLK_GPT_SERIAL>;
302 clock-names = "ipg", "per";
303 };
304
305 gpio1: gpio@0209c000 {
306 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
307 reg = <0x0209c000 0x4000>;
308 interrupts = <0 66 0x04 0 67 0x04>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314
315 gpio2: gpio@020a0000 {
316 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
317 reg = <0x020a0000 0x4000>;
318 interrupts = <0 68 0x04 0 69 0x04>;
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 };
324
325 gpio3: gpio@020a4000 {
326 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
327 reg = <0x020a4000 0x4000>;
328 interrupts = <0 70 0x04 0 71 0x04>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334
335 gpio4: gpio@020a8000 {
336 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
337 reg = <0x020a8000 0x4000>;
338 interrupts = <0 72 0x04 0 73 0x04>;
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
344
345 gpio5: gpio@020ac000 {
346 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
347 reg = <0x020ac000 0x4000>;
348 interrupts = <0 74 0x04 0 75 0x04>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 kpp: kpp@020b8000 {
356 reg = <0x020b8000 0x4000>;
357 interrupts = <0 82 0x04>;
358 };
359
360 wdog1: wdog@020bc000 {
361 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
362 reg = <0x020bc000 0x4000>;
363 interrupts = <0 80 0x04>;
364 clocks = <&clks IMX6SL_CLK_DUMMY>;
365 };
366
367 wdog2: wdog@020c0000 {
368 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
369 reg = <0x020c0000 0x4000>;
370 interrupts = <0 81 0x04>;
371 clocks = <&clks IMX6SL_CLK_DUMMY>;
372 status = "disabled";
373 };
374
375 clks: ccm@020c4000 {
376 compatible = "fsl,imx6sl-ccm";
377 reg = <0x020c4000 0x4000>;
378 interrupts = <0 87 0x04 0 88 0x04>;
379 #clock-cells = <1>;
380 };
381
382 anatop: anatop@020c8000 {
Shawn Guod8ce8232013-08-13 16:54:05 +0800[diff] [blame^]383 compatible = "fsl,imx6sl-anatop",
384 "fsl,imx6q-anatop",
385 "syscon", "simple-bus";
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]386 reg = <0x020c8000 0x1000>;
387 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
388
389 regulator-1p1@110 {
390 compatible = "fsl,anatop-regulator";
391 regulator-name = "vdd1p1";
392 regulator-min-microvolt = <800000>;
393 regulator-max-microvolt = <1375000>;
394 regulator-always-on;
395 anatop-reg-offset = <0x110>;
396 anatop-vol-bit-shift = <8>;
397 anatop-vol-bit-width = <5>;
398 anatop-min-bit-val = <4>;
399 anatop-min-voltage = <800000>;
400 anatop-max-voltage = <1375000>;
401 };
402
403 regulator-3p0@120 {
404 compatible = "fsl,anatop-regulator";
405 regulator-name = "vdd3p0";
406 regulator-min-microvolt = <2800000>;
407 regulator-max-microvolt = <3150000>;
408 regulator-always-on;
409 anatop-reg-offset = <0x120>;
410 anatop-vol-bit-shift = <8>;
411 anatop-vol-bit-width = <5>;
412 anatop-min-bit-val = <0>;
413 anatop-min-voltage = <2625000>;
414 anatop-max-voltage = <3400000>;
415 };
416
417 regulator-2p5@130 {
418 compatible = "fsl,anatop-regulator";
419 regulator-name = "vdd2p5";
420 regulator-min-microvolt = <2100000>;
421 regulator-max-microvolt = <2850000>;
422 regulator-always-on;
423 anatop-reg-offset = <0x130>;
424 anatop-vol-bit-shift = <8>;
425 anatop-vol-bit-width = <5>;
426 anatop-min-bit-val = <0>;
427 anatop-min-voltage = <2100000>;
428 anatop-max-voltage = <2850000>;
429 };
430
431 reg_arm: regulator-vddcore@140 {
432 compatible = "fsl,anatop-regulator";
433 regulator-name = "cpu";
434 regulator-min-microvolt = <725000>;
435 regulator-max-microvolt = <1450000>;
436 regulator-always-on;
437 anatop-reg-offset = <0x140>;
438 anatop-vol-bit-shift = <0>;
439 anatop-vol-bit-width = <5>;
440 anatop-delay-reg-offset = <0x170>;
441 anatop-delay-bit-shift = <24>;
442 anatop-delay-bit-width = <2>;
443 anatop-min-bit-val = <1>;
444 anatop-min-voltage = <725000>;
445 anatop-max-voltage = <1450000>;
446 };
447
448 reg_pu: regulator-vddpu@140 {
449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vddpu";
451 regulator-min-microvolt = <725000>;
452 regulator-max-microvolt = <1450000>;
453 regulator-always-on;
454 anatop-reg-offset = <0x140>;
455 anatop-vol-bit-shift = <9>;
456 anatop-vol-bit-width = <5>;
457 anatop-delay-reg-offset = <0x170>;
458 anatop-delay-bit-shift = <26>;
459 anatop-delay-bit-width = <2>;
460 anatop-min-bit-val = <1>;
461 anatop-min-voltage = <725000>;
462 anatop-max-voltage = <1450000>;
463 };
464
465 reg_soc: regulator-vddsoc@140 {
466 compatible = "fsl,anatop-regulator";
467 regulator-name = "vddsoc";
468 regulator-min-microvolt = <725000>;
469 regulator-max-microvolt = <1450000>;
470 regulator-always-on;
471 anatop-reg-offset = <0x140>;
472 anatop-vol-bit-shift = <18>;
473 anatop-vol-bit-width = <5>;
474 anatop-delay-reg-offset = <0x170>;
475 anatop-delay-bit-shift = <28>;
476 anatop-delay-bit-width = <2>;
477 anatop-min-bit-val = <1>;
478 anatop-min-voltage = <725000>;
479 anatop-max-voltage = <1450000>;
480 };
481 };
482
483 usbphy1: usbphy@020c9000 {
484 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
485 reg = <0x020c9000 0x1000>;
486 interrupts = <0 44 0x04>;
487 clocks = <&clks IMX6SL_CLK_USBPHY1>;
488 };
489
490 usbphy2: usbphy@020ca000 {
491 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
492 reg = <0x020ca000 0x1000>;
493 interrupts = <0 45 0x04>;
494 clocks = <&clks IMX6SL_CLK_USBPHY2>;
495 };
496
497 snvs@020cc000 {
498 compatible = "fsl,sec-v4.0-mon", "simple-bus";
499 #address-cells = <1>;
500 #size-cells = <1>;
501 ranges = <0 0x020cc000 0x4000>;
502
503 snvs-rtc-lp@34 {
504 compatible = "fsl,sec-v4.0-mon-rtc-lp";
505 reg = <0x34 0x58>;
506 interrupts = <0 19 0x04 0 20 0x04>;
507 };
508 };
509
510 epit1: epit@020d0000 {
511 reg = <0x020d0000 0x4000>;
512 interrupts = <0 56 0x04>;
513 };
514
515 epit2: epit@020d4000 {
516 reg = <0x020d4000 0x4000>;
517 interrupts = <0 57 0x04>;
518 };
519
520 src: src@020d8000 {
521 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
522 reg = <0x020d8000 0x4000>;
523 interrupts = <0 91 0x04 0 96 0x04>;
524 #reset-cells = <1>;
525 };
526
527 gpc: gpc@020dc000 {
528 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
529 reg = <0x020dc000 0x4000>;
530 interrupts = <0 89 0x04>;
531 };
532
533 iomuxc: iomuxc@020e0000 {
534 compatible = "fsl,imx6sl-iomuxc";
535 reg = <0x020e0000 0x4000>;
536
537 fec {
538 pinctrl_fec_1: fecgrp-1 {
539 fsl,pins = <
540 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
541 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
542 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
543 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
544 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
545 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
546 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
547 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
548 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
549 >;
550 };
551 };
552
553 uart1 {
554 pinctrl_uart1_1: uart1grp-1 {
555 fsl,pins = <
556 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
557 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
558 >;
559 };
560 };
561
562 usdhc1 {
563 pinctrl_usdhc1_1: usdhc1grp-1 {
564 fsl,pins = <
565 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
566 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
567 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
568 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
569 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
570 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
571 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
572 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
573 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
574 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
575 >;
576 };
577 };
578
579 usdhc2 {
580 pinctrl_usdhc2_1: usdhc2grp-1 {
581 fsl,pins = <
582 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
583 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
584 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
585 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
586 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
587 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
588 >;
589 };
590 };
591
592 usdhc3 {
593 pinctrl_usdhc3_1: usdhc3grp-1 {
594 fsl,pins = <
595 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
596 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
597 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
598 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
599 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
600 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
601 >;
602 };
603 };
604 };
605
606 csi: csi@020e4000 {
607 reg = <0x020e4000 0x4000>;
608 interrupts = <0 7 0x04>;
609 };
610
611 spdc: spdc@020e8000 {
612 reg = <0x020e8000 0x4000>;
613 interrupts = <0 6 0x04>;
614 };
615
616 sdma: sdma@020ec000 {
617 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
618 reg = <0x020ec000 0x4000>;
619 interrupts = <0 2 0x04>;
620 clocks = <&clks IMX6SL_CLK_SDMA>,
621 <&clks IMX6SL_CLK_SDMA>;
622 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]623 #dma-cells = <3>;
Shawn Guoe29fe212013-05-03 11:26:30 +0800[diff] [blame]624 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
625 };
626
627 pxp: pxp@020f0000 {
628 reg = <0x020f0000 0x4000>;
629 interrupts = <0 98 0x04>;
630 };
631
632 epdc: epdc@020f4000 {
633 reg = <0x020f4000 0x4000>;
634 interrupts = <0 97 0x04>;
635 };
636
637 lcdif: lcdif@020f8000 {
638 reg = <0x020f8000 0x4000>;
639 interrupts = <0 39 0x04>;
640 };
641
642 dcp: dcp@020fc000 {
643 reg = <0x020fc000 0x4000>;
644 interrupts = <0 99 0x04>;
645 };
646 };
647
648 aips2: aips-bus@02100000 {
649 compatible = "fsl,aips-bus", "simple-bus";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 reg = <0x02100000 0x100000>;
653 ranges;
654
655 usbotg1: usb@02184000 {
656 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
657 reg = <0x02184000 0x200>;
658 interrupts = <0 43 0x04>;
659 clocks = <&clks IMX6SL_CLK_USBOH3>;
660 fsl,usbphy = <&usbphy1>;
661 fsl,usbmisc = <&usbmisc 0>;
662 status = "disabled";
663 };
664
665 usbotg2: usb@02184200 {
666 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
667 reg = <0x02184200 0x200>;
668 interrupts = <0 40 0x04>;
669 clocks = <&clks IMX6SL_CLK_USBOH3>;
670 fsl,usbphy = <&usbphy2>;
671 fsl,usbmisc = <&usbmisc 1>;
672 status = "disabled";
673 };
674
675 usbh: usb@02184400 {
676 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
677 reg = <0x02184400 0x200>;
678 interrupts = <0 42 0x04>;
679 clocks = <&clks IMX6SL_CLK_USBOH3>;
680 fsl,usbmisc = <&usbmisc 2>;
681 status = "disabled";
682 };
683
684 usbmisc: usbmisc@02184800 {
685 #index-cells = <1>;
686 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
687 reg = <0x02184800 0x200>;
688 clocks = <&clks IMX6SL_CLK_USBOH3>;
689 };
690
691 fec: ethernet@02188000 {
692 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
693 reg = <0x02188000 0x4000>;
694 interrupts = <0 114 0x04>;
695 clocks = <&clks IMX6SL_CLK_ENET_REF>,
696 <&clks IMX6SL_CLK_ENET_REF>;
697 clock-names = "ipg", "ahb";
698 status = "disabled";
699 };
700
701 usdhc1: usdhc@02190000 {
702 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
703 reg = <0x02190000 0x4000>;
704 interrupts = <0 22 0x04>;
705 clocks = <&clks IMX6SL_CLK_USDHC1>,
706 <&clks IMX6SL_CLK_USDHC1>,
707 <&clks IMX6SL_CLK_USDHC1>;
708 clock-names = "ipg", "ahb", "per";
709 bus-width = <4>;
710 status = "disabled";
711 };
712
713 usdhc2: usdhc@02194000 {
714 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
715 reg = <0x02194000 0x4000>;
716 interrupts = <0 23 0x04>;
717 clocks = <&clks IMX6SL_CLK_USDHC2>,
718 <&clks IMX6SL_CLK_USDHC2>,
719 <&clks IMX6SL_CLK_USDHC2>;
720 clock-names = "ipg", "ahb", "per";
721 bus-width = <4>;
722 status = "disabled";
723 };
724
725 usdhc3: usdhc@02198000 {
726 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
727 reg = <0x02198000 0x4000>;
728 interrupts = <0 24 0x04>;
729 clocks = <&clks IMX6SL_CLK_USDHC3>,
730 <&clks IMX6SL_CLK_USDHC3>,
731 <&clks IMX6SL_CLK_USDHC3>;
732 clock-names = "ipg", "ahb", "per";
733 bus-width = <4>;
734 status = "disabled";
735 };
736
737 usdhc4: usdhc@0219c000 {
738 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
739 reg = <0x0219c000 0x4000>;
740 interrupts = <0 25 0x04>;
741 clocks = <&clks IMX6SL_CLK_USDHC4>,
742 <&clks IMX6SL_CLK_USDHC4>,
743 <&clks IMX6SL_CLK_USDHC4>;
744 clock-names = "ipg", "ahb", "per";
745 bus-width = <4>;
746 status = "disabled";
747 };
748
749 i2c1: i2c@021a0000 {
750 #address-cells = <1>;
751 #size-cells = <0>;
752 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
753 reg = <0x021a0000 0x4000>;
754 interrupts = <0 36 0x04>;
755 clocks = <&clks IMX6SL_CLK_I2C1>;
756 status = "disabled";
757 };
758
759 i2c2: i2c@021a4000 {
760 #address-cells = <1>;
761 #size-cells = <0>;
762 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
763 reg = <0x021a4000 0x4000>;
764 interrupts = <0 37 0x04>;
765 clocks = <&clks IMX6SL_CLK_I2C2>;
766 status = "disabled";
767 };
768
769 i2c3: i2c@021a8000 {
770 #address-cells = <1>;
771 #size-cells = <0>;
772 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
773 reg = <0x021a8000 0x4000>;
774 interrupts = <0 38 0x04>;
775 clocks = <&clks IMX6SL_CLK_I2C3>;
776 status = "disabled";
777 };
778
779 mmdc: mmdc@021b0000 {
780 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
781 reg = <0x021b0000 0x4000>;
782 };
783
784 rngb: rngb@021b4000 {
785 reg = <0x021b4000 0x4000>;
786 interrupts = <0 5 0x04>;
787 };
788
789 weim: weim@021b8000 {
790 reg = <0x021b8000 0x4000>;
791 interrupts = <0 14 0x04>;
792 };
793
794 ocotp: ocotp@021bc000 {
795 compatible = "fsl,imx6sl-ocotp";
796 reg = <0x021bc000 0x4000>;
797 };
798
799 audmux: audmux@021d8000 {
800 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
801 reg = <0x021d8000 0x4000>;
802 status = "disabled";
803 };
804 };
805 };
806};