blob: 68d24b80053bd8cd7da4477373db2c2b31e346dc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004,2005 by Thiemo Seufer
9 */
10
11#include <stdarg.h>
12
13#include <linux/config.h>
14#include <linux/mm.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/string.h>
18#include <linux/init.h>
19
20#include <asm/pgtable.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
23#include <asm/inst.h>
24#include <asm/elf.h>
25#include <asm/smp.h>
26#include <asm/war.h>
27
28/* #define DEBUG_TLB */
29
30static __init int __attribute__((unused)) r45k_bvahwbug(void)
31{
32 /* XXX: We should probe for the presence of this bug, but we don't. */
33 return 0;
34}
35
36static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
37{
38 /* XXX: We should probe for the presence of this bug, but we don't. */
39 return 0;
40}
41
42static __init int __attribute__((unused)) bcm1250_m3_war(void)
43{
44 return BCM1250_M3_WAR;
45}
46
47static __init int __attribute__((unused)) r10000_llsc_war(void)
48{
49 return R10000_LLSC_WAR;
50}
51
52/*
53 * A little micro-assembler, intended for TLB refill handler
54 * synthesizing. It is intentionally kept simple, does only support
55 * a subset of instructions, and does not try to hide pipeline effects
56 * like branch delay slots.
57 */
58
59enum fields
60{
61 RS = 0x001,
62 RT = 0x002,
63 RD = 0x004,
64 RE = 0x008,
65 SIMM = 0x010,
66 UIMM = 0x020,
67 BIMM = 0x040,
68 JIMM = 0x080,
69 FUNC = 0x100,
70};
71
72#define OP_MASK 0x2f
73#define OP_SH 26
74#define RS_MASK 0x1f
75#define RS_SH 21
76#define RT_MASK 0x1f
77#define RT_SH 16
78#define RD_MASK 0x1f
79#define RD_SH 11
80#define RE_MASK 0x1f
81#define RE_SH 6
82#define IMM_MASK 0xffff
83#define IMM_SH 0
84#define JIMM_MASK 0x3ffffff
85#define JIMM_SH 0
86#define FUNC_MASK 0x2f
87#define FUNC_SH 0
88
89enum opcode {
90 insn_invalid,
91 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
92 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
93 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +000094 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
96 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
97 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
98 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
99 insn_tlbwr, insn_xor, insn_xori
100};
101
102struct insn {
103 enum opcode opcode;
104 u32 match;
105 enum fields fields;
106};
107
108/* This macro sets the non-variable bits of an instruction. */
109#define M(a, b, c, d, e, f) \
110 ((a) << OP_SH \
111 | (b) << RS_SH \
112 | (c) << RT_SH \
113 | (d) << RD_SH \
114 | (e) << RE_SH \
115 | (f) << FUNC_SH)
116
117static __initdata struct insn insn_table[] = {
118 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
119 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
120 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
121 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
122 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
123 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
124 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
125 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
126 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
127 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
128 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
129 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
130 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
131 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD },
132 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD },
133 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
134 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
135 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
136 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
138 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
139 { insn_j, M(j_op,0,0,0,0,0), JIMM },
140 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
141 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
142 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
143 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
144 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
145 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
146 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
147 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD },
148 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD },
149 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
150 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
151 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
152 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
153 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
154 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
155 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
156 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
157 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
158 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
159 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
160 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
161 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
162 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
163 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
164 { insn_invalid, 0, 0 }
165};
166
167#undef M
168
169static __init u32 build_rs(u32 arg)
170{
171 if (arg & ~RS_MASK)
172 printk(KERN_WARNING "TLB synthesizer field overflow\n");
173
174 return (arg & RS_MASK) << RS_SH;
175}
176
177static __init u32 build_rt(u32 arg)
178{
179 if (arg & ~RT_MASK)
180 printk(KERN_WARNING "TLB synthesizer field overflow\n");
181
182 return (arg & RT_MASK) << RT_SH;
183}
184
185static __init u32 build_rd(u32 arg)
186{
187 if (arg & ~RD_MASK)
188 printk(KERN_WARNING "TLB synthesizer field overflow\n");
189
190 return (arg & RD_MASK) << RD_SH;
191}
192
193static __init u32 build_re(u32 arg)
194{
195 if (arg & ~RE_MASK)
196 printk(KERN_WARNING "TLB synthesizer field overflow\n");
197
198 return (arg & RE_MASK) << RE_SH;
199}
200
201static __init u32 build_simm(s32 arg)
202{
203 if (arg > 0x7fff || arg < -0x8000)
204 printk(KERN_WARNING "TLB synthesizer field overflow\n");
205
206 return arg & 0xffff;
207}
208
209static __init u32 build_uimm(u32 arg)
210{
211 if (arg & ~IMM_MASK)
212 printk(KERN_WARNING "TLB synthesizer field overflow\n");
213
214 return arg & IMM_MASK;
215}
216
217static __init u32 build_bimm(s32 arg)
218{
219 if (arg > 0x1ffff || arg < -0x20000)
220 printk(KERN_WARNING "TLB synthesizer field overflow\n");
221
222 if (arg & 0x3)
223 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
224
225 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
226}
227
228static __init u32 build_jimm(u32 arg)
229{
230 if (arg & ~((JIMM_MASK) << 2))
231 printk(KERN_WARNING "TLB synthesizer field overflow\n");
232
233 return (arg >> 2) & JIMM_MASK;
234}
235
236static __init u32 build_func(u32 arg)
237{
238 if (arg & ~FUNC_MASK)
239 printk(KERN_WARNING "TLB synthesizer field overflow\n");
240
241 return arg & FUNC_MASK;
242}
243
244/*
245 * The order of opcode arguments is implicitly left to right,
246 * starting with RS and ending with FUNC or IMM.
247 */
248static void __init build_insn(u32 **buf, enum opcode opc, ...)
249{
250 struct insn *ip = NULL;
251 unsigned int i;
252 va_list ap;
253 u32 op;
254
255 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
256 if (insn_table[i].opcode == opc) {
257 ip = &insn_table[i];
258 break;
259 }
260
261 if (!ip)
262 panic("Unsupported TLB synthesizer instruction %d", opc);
263
264 op = ip->match;
265 va_start(ap, opc);
266 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
267 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
268 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
269 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
270 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
271 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
272 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
273 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
274 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
275 va_end(ap);
276
277 **buf = op;
278 (*buf)++;
279}
280
281#define I_u1u2u3(op) \
282 static inline void i##op(u32 **buf, unsigned int a, \
283 unsigned int b, unsigned int c) \
284 { \
285 build_insn(buf, insn##op, a, b, c); \
286 }
287
288#define I_u2u1u3(op) \
289 static inline void i##op(u32 **buf, unsigned int a, \
290 unsigned int b, unsigned int c) \
291 { \
292 build_insn(buf, insn##op, b, a, c); \
293 }
294
295#define I_u3u1u2(op) \
296 static inline void i##op(u32 **buf, unsigned int a, \
297 unsigned int b, unsigned int c) \
298 { \
299 build_insn(buf, insn##op, b, c, a); \
300 }
301
302#define I_u1u2s3(op) \
303 static inline void i##op(u32 **buf, unsigned int a, \
304 unsigned int b, signed int c) \
305 { \
306 build_insn(buf, insn##op, a, b, c); \
307 }
308
309#define I_u2s3u1(op) \
310 static inline void i##op(u32 **buf, unsigned int a, \
311 signed int b, unsigned int c) \
312 { \
313 build_insn(buf, insn##op, c, a, b); \
314 }
315
316#define I_u2u1s3(op) \
317 static inline void i##op(u32 **buf, unsigned int a, \
318 unsigned int b, signed int c) \
319 { \
320 build_insn(buf, insn##op, b, a, c); \
321 }
322
323#define I_u1u2(op) \
324 static inline void i##op(u32 **buf, unsigned int a, \
325 unsigned int b) \
326 { \
327 build_insn(buf, insn##op, a, b); \
328 }
329
330#define I_u1s2(op) \
331 static inline void i##op(u32 **buf, unsigned int a, \
332 signed int b) \
333 { \
334 build_insn(buf, insn##op, a, b); \
335 }
336
337#define I_u1(op) \
338 static inline void i##op(u32 **buf, unsigned int a) \
339 { \
340 build_insn(buf, insn##op, a); \
341 }
342
343#define I_0(op) \
344 static inline void i##op(u32 **buf) \
345 { \
346 build_insn(buf, insn##op); \
347 }
348
349I_u2u1s3(_addiu);
350I_u3u1u2(_addu);
351I_u2u1u3(_andi);
352I_u3u1u2(_and);
353I_u1u2s3(_beq);
354I_u1u2s3(_beql);
355I_u1s2(_bgez);
356I_u1s2(_bgezl);
357I_u1s2(_bltz);
358I_u1s2(_bltzl);
359I_u1u2s3(_bne);
360I_u1u2(_dmfc0);
361I_u1u2(_dmtc0);
362I_u2u1s3(_daddiu);
363I_u3u1u2(_daddu);
364I_u2u1u3(_dsll);
365I_u2u1u3(_dsll32);
366I_u2u1u3(_dsra);
367I_u2u1u3(_dsrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368I_u3u1u2(_dsubu);
369I_0(_eret);
370I_u1(_j);
371I_u1(_jal);
372I_u1(_jr);
373I_u2s3u1(_ld);
374I_u2s3u1(_ll);
375I_u2s3u1(_lld);
376I_u1s2(_lui);
377I_u2s3u1(_lw);
378I_u1u2(_mfc0);
379I_u1u2(_mtc0);
380I_u2u1u3(_ori);
381I_0(_rfe);
382I_u2s3u1(_sc);
383I_u2s3u1(_scd);
384I_u2s3u1(_sd);
385I_u2u1u3(_sll);
386I_u2u1u3(_sra);
387I_u2u1u3(_srl);
388I_u3u1u2(_subu);
389I_u2s3u1(_sw);
390I_0(_tlbp);
391I_0(_tlbwi);
392I_0(_tlbwr);
393I_u3u1u2(_xor)
394I_u2u1u3(_xori);
395
396/*
397 * handling labels
398 */
399
400enum label_id {
401 label_invalid,
402 label_second_part,
403 label_leave,
404 label_vmalloc,
405 label_vmalloc_done,
406 label_tlbw_hazard,
407 label_split,
408 label_nopage_tlbl,
409 label_nopage_tlbs,
410 label_nopage_tlbm,
411 label_smp_pgtable_change,
412 label_r3000_write_probe_fail,
413 label_r3000_write_probe_ok
414};
415
416struct label {
417 u32 *addr;
418 enum label_id lab;
419};
420
421static __init void build_label(struct label **lab, u32 *addr,
422 enum label_id l)
423{
424 (*lab)->addr = addr;
425 (*lab)->lab = l;
426 (*lab)++;
427}
428
429#define L_LA(lb) \
430 static inline void l##lb(struct label **lab, u32 *addr) \
431 { \
432 build_label(lab, addr, label##lb); \
433 }
434
435L_LA(_second_part)
436L_LA(_leave)
437L_LA(_vmalloc)
438L_LA(_vmalloc_done)
439L_LA(_tlbw_hazard)
440L_LA(_split)
441L_LA(_nopage_tlbl)
442L_LA(_nopage_tlbs)
443L_LA(_nopage_tlbm)
444L_LA(_smp_pgtable_change)
445L_LA(_r3000_write_probe_fail)
446L_LA(_r3000_write_probe_ok)
447
448/* convenience macros for instructions */
Ralf Baechle875d43e2005-09-03 15:56:16 -0700449#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
451# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
452# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
453# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
454# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
455# define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd)
456# define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd)
457# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
458# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
459# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
460# define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
461# define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
462#else
463# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
464# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
465# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
466# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
467# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
468# define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd)
469# define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd)
470# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
471# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
472# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
473# define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
474# define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
475#endif
476
477#define i_b(buf, off) i_beq(buf, 0, 0, off)
478#define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
479#define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
480#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
481#define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
482#define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
483#define i_nop(buf) i_sll(buf, 0, 0, 0)
484#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
485#define i_ehb(buf) i_sll(buf, 0, 0, 3)
486
Ralf Baechle875d43e2005-09-03 15:56:16 -0700487#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488static __init int __attribute__((unused)) in_compat_space_p(long addr)
489{
490 /* Is this address in 32bit compat space? */
491 return (((addr) & 0xffffffff00000000) == 0xffffffff00000000);
492}
493
494static __init int __attribute__((unused)) rel_highest(long val)
495{
496 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
497}
498
499static __init int __attribute__((unused)) rel_higher(long val)
500{
501 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
502}
503#endif
504
505static __init int rel_hi(long val)
506{
507 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
508}
509
510static __init int rel_lo(long val)
511{
512 return ((val & 0xffff) ^ 0x8000) - 0x8000;
513}
514
515static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
516{
Yoichi Yuasa766160c2005-09-03 15:56:22 -0700517#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 if (!in_compat_space_p(addr)) {
519 i_lui(buf, rs, rel_highest(addr));
520 if (rel_higher(addr))
521 i_daddiu(buf, rs, rs, rel_higher(addr));
522 if (rel_hi(addr)) {
523 i_dsll(buf, rs, rs, 16);
524 i_daddiu(buf, rs, rs, rel_hi(addr));
525 i_dsll(buf, rs, rs, 16);
526 } else
527 i_dsll32(buf, rs, rs, 0);
528 } else
529#endif
530 i_lui(buf, rs, rel_hi(addr));
531}
532
533static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
534 long addr)
535{
536 i_LA_mostly(buf, rs, addr);
537 if (rel_lo(addr))
538 i_ADDIU(buf, rs, rs, rel_lo(addr));
539}
540
541/*
542 * handle relocations
543 */
544
545struct reloc {
546 u32 *addr;
547 unsigned int type;
548 enum label_id lab;
549};
550
551static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
552 enum label_id l)
553{
554 (*rel)->addr = addr;
555 (*rel)->type = R_MIPS_PC16;
556 (*rel)->lab = l;
557 (*rel)++;
558}
559
560static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
561{
562 long laddr = (long)lab->addr;
563 long raddr = (long)rel->addr;
564
565 switch (rel->type) {
566 case R_MIPS_PC16:
567 *rel->addr |= build_bimm(laddr - (raddr + 4));
568 break;
569
570 default:
571 panic("Unsupported TLB synthesizer relocation %d",
572 rel->type);
573 }
574}
575
576static __init void resolve_relocs(struct reloc *rel, struct label *lab)
577{
578 struct label *l;
579
580 for (; rel->lab != label_invalid; rel++)
581 for (l = lab; l->lab != label_invalid; l++)
582 if (rel->lab == l->lab)
583 __resolve_relocs(rel, l);
584}
585
586static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
587 long off)
588{
589 for (; rel->lab != label_invalid; rel++)
590 if (rel->addr >= first && rel->addr < end)
591 rel->addr += off;
592}
593
594static __init void move_labels(struct label *lab, u32 *first, u32 *end,
595 long off)
596{
597 for (; lab->lab != label_invalid; lab++)
598 if (lab->addr >= first && lab->addr < end)
599 lab->addr += off;
600}
601
602static __init void copy_handler(struct reloc *rel, struct label *lab,
603 u32 *first, u32 *end, u32 *target)
604{
605 long off = (long)(target - first);
606
607 memcpy(target, first, (end - first) * sizeof(u32));
608
609 move_relocs(rel, first, end, off);
610 move_labels(lab, first, end, off);
611}
612
613static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
614 u32 *addr)
615{
616 for (; rel->lab != label_invalid; rel++) {
617 if (rel->addr == addr
618 && (rel->type == R_MIPS_PC16
619 || rel->type == R_MIPS_26))
620 return 1;
621 }
622
623 return 0;
624}
625
626/* convenience functions for labeled branches */
627static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r,
628 unsigned int reg, enum label_id l)
629{
630 r_mips_pc16(r, *p, l);
631 i_bltz(p, reg, 0);
632}
633
634static void __attribute__((unused)) il_b(u32 **p, struct reloc **r,
635 enum label_id l)
636{
637 r_mips_pc16(r, *p, l);
638 i_b(p, 0);
639}
640
641static void il_beqz(u32 **p, struct reloc **r, unsigned int reg,
642 enum label_id l)
643{
644 r_mips_pc16(r, *p, l);
645 i_beqz(p, reg, 0);
646}
647
648static void __attribute__((unused))
649il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
650{
651 r_mips_pc16(r, *p, l);
652 i_beqzl(p, reg, 0);
653}
654
655static void il_bnez(u32 **p, struct reloc **r, unsigned int reg,
656 enum label_id l)
657{
658 r_mips_pc16(r, *p, l);
659 i_bnez(p, reg, 0);
660}
661
662static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
663 enum label_id l)
664{
665 r_mips_pc16(r, *p, l);
666 i_bgezl(p, reg, 0);
667}
668
669/* The only general purpose registers allowed in TLB handlers. */
670#define K0 26
671#define K1 27
672
673/* Some CP0 registers */
674#define C0_INDEX 0
675#define C0_ENTRYLO0 2
676#define C0_ENTRYLO1 3
677#define C0_CONTEXT 4
678#define C0_BADVADDR 8
679#define C0_ENTRYHI 10
680#define C0_EPC 14
681#define C0_XCONTEXT 20
682
Ralf Baechle875d43e2005-09-03 15:56:16 -0700683#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
685#else
686# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
687#endif
688
689/* The worst case length of the handler is around 18 instructions for
690 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
691 * Maximum space available is 32 instructions for R3000 and 64
692 * instructions for R4000.
693 *
694 * We deliberately chose a buffer size of 128, so we won't scribble
695 * over anything important on overflow before we panic.
696 */
697static __initdata u32 tlb_handler[128];
698
699/* simply assume worst case size for labels and relocs */
700static __initdata struct label labels[128];
701static __initdata struct reloc relocs[128];
702
703/*
704 * The R3000 TLB handler is simple.
705 */
706static void __init build_r3000_tlb_refill_handler(void)
707{
708 long pgdc = (long)pgd_current;
709 u32 *p;
710
711 memset(tlb_handler, 0, sizeof(tlb_handler));
712 p = tlb_handler;
713
714 i_mfc0(&p, K0, C0_BADVADDR);
715 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
716 i_lw(&p, K1, rel_lo(pgdc), K1);
717 i_srl(&p, K0, K0, 22); /* load delay */
718 i_sll(&p, K0, K0, 2);
719 i_addu(&p, K1, K1, K0);
720 i_mfc0(&p, K0, C0_CONTEXT);
721 i_lw(&p, K1, 0, K1); /* cp0 delay */
722 i_andi(&p, K0, K0, 0xffc); /* load delay */
723 i_addu(&p, K1, K1, K0);
724 i_lw(&p, K0, 0, K1);
725 i_nop(&p); /* load delay */
726 i_mtc0(&p, K0, C0_ENTRYLO0);
727 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
728 i_tlbwr(&p); /* cp0 delay */
729 i_jr(&p, K1);
730 i_rfe(&p); /* branch delay */
731
732 if (p > tlb_handler + 32)
733 panic("TLB refill handler space exceeded");
734
735 printk("Synthesized TLB handler (%u instructions).\n",
736 (unsigned int)(p - tlb_handler));
737#ifdef DEBUG_TLB
738 {
739 int i;
740
741 for (i = 0; i < (p - tlb_handler); i++)
742 printk("%08x\n", tlb_handler[i]);
743 }
744#endif
745
746 memcpy((void *)CAC_BASE, tlb_handler, 0x80);
747 flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
748}
749
750/*
751 * The R4000 TLB handler is much more complicated. We have two
752 * consecutive handler areas with 32 instructions space each.
753 * Since they aren't used at the same time, we can overflow in the
754 * other one.To keep things simple, we first assume linear space,
755 * then we relocate it to the final handler layout as needed.
756 */
757static __initdata u32 final_handler[64];
758
759/*
760 * Hazards
761 *
762 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
763 * 2. A timing hazard exists for the TLBP instruction.
764 *
765 * stalling_instruction
766 * TLBP
767 *
768 * The JTLB is being read for the TLBP throughout the stall generated by the
769 * previous instruction. This is not really correct as the stalling instruction
770 * can modify the address used to access the JTLB. The failure symptom is that
771 * the TLBP instruction will use an address created for the stalling instruction
772 * and not the address held in C0_ENHI and thus report the wrong results.
773 *
774 * The software work-around is to not allow the instruction preceding the TLBP
775 * to stall - make it an NOP or some other instruction guaranteed not to stall.
776 *
777 * Errata 2 will not be fixed. This errata is also on the R5000.
778 *
779 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
780 */
781static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
782{
783 switch (current_cpu_data.cputype) {
784 case CPU_R5000:
785 case CPU_R5000A:
786 case CPU_NEVADA:
787 i_nop(p);
788 i_tlbp(p);
789 break;
790
791 default:
792 i_tlbp(p);
793 break;
794 }
795}
796
797/*
798 * Write random or indexed TLB entry, and care about the hazards from
799 * the preceeding mtc0 and for the following eret.
800 */
801enum tlb_write_entry { tlb_random, tlb_indexed };
802
803static __init void build_tlb_write_entry(u32 **p, struct label **l,
804 struct reloc **r,
805 enum tlb_write_entry wmode)
806{
807 void(*tlbw)(u32 **) = NULL;
808
809 switch (wmode) {
810 case tlb_random: tlbw = i_tlbwr; break;
811 case tlb_indexed: tlbw = i_tlbwi; break;
812 }
813
814 switch (current_cpu_data.cputype) {
815 case CPU_R4000PC:
816 case CPU_R4000SC:
817 case CPU_R4000MC:
818 case CPU_R4400PC:
819 case CPU_R4400SC:
820 case CPU_R4400MC:
821 /*
822 * This branch uses up a mtc0 hazard nop slot and saves
823 * two nops after the tlbw instruction.
824 */
825 il_bgezl(p, r, 0, label_tlbw_hazard);
826 tlbw(p);
827 l_tlbw_hazard(l, *p);
828 i_nop(p);
829 break;
830
Ralf Baechle6cbe0632005-03-20 22:57:38 +0000831 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 case CPU_R4600:
833 case CPU_R4700:
834 case CPU_R5000:
835 case CPU_R5000A:
836 case CPU_5KC:
837 case CPU_TX49XX:
838 case CPU_AU1000:
839 case CPU_AU1100:
840 case CPU_AU1500:
841 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000842 case CPU_AU1200:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 i_nop(p);
844 tlbw(p);
845 break;
846
847 case CPU_R10000:
848 case CPU_R12000:
849 case CPU_4KC:
850 case CPU_SB1:
851 case CPU_4KSC:
852 case CPU_20KC:
853 case CPU_25KF:
854 tlbw(p);
855 break;
856
857 case CPU_NEVADA:
858 i_nop(p); /* QED specifies 2 nops hazard */
859 /*
860 * This branch uses up a mtc0 hazard nop slot and saves
861 * a nop after the tlbw instruction.
862 */
863 il_bgezl(p, r, 0, label_tlbw_hazard);
864 tlbw(p);
865 l_tlbw_hazard(l, *p);
866 break;
867
868 case CPU_RM7000:
869 i_nop(p);
870 i_nop(p);
871 i_nop(p);
872 i_nop(p);
873 tlbw(p);
874 break;
875
876 case CPU_4KEC:
877 case CPU_24K:
878 i_ehb(p);
879 tlbw(p);
880 break;
881
882 case CPU_RM9000:
883 /*
884 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
885 * use of the JTLB for instructions should not occur for 4
886 * cpu cycles and use for data translations should not occur
887 * for 3 cpu cycles.
888 */
889 i_ssnop(p);
890 i_ssnop(p);
891 i_ssnop(p);
892 i_ssnop(p);
893 tlbw(p);
894 i_ssnop(p);
895 i_ssnop(p);
896 i_ssnop(p);
897 i_ssnop(p);
898 break;
899
900 case CPU_VR4111:
901 case CPU_VR4121:
902 case CPU_VR4122:
903 case CPU_VR4181:
904 case CPU_VR4181A:
905 i_nop(p);
906 i_nop(p);
907 tlbw(p);
908 i_nop(p);
909 i_nop(p);
910 break;
911
912 case CPU_VR4131:
913 case CPU_VR4133:
914 i_nop(p);
915 i_nop(p);
916 tlbw(p);
917 break;
918
919 default:
920 panic("No TLB refill handler yet (CPU type: %d)",
921 current_cpu_data.cputype);
922 break;
923 }
924}
925
Ralf Baechle875d43e2005-09-03 15:56:16 -0700926#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927/*
928 * TMP and PTR are scratch.
929 * TMP will be clobbered, PTR will hold the pmd entry.
930 */
931static __init void
932build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
933 unsigned int tmp, unsigned int ptr)
934{
935 long pgdc = (long)pgd_current;
936
937 /*
938 * The vmalloc handling is not in the hotpath.
939 */
940 i_dmfc0(p, tmp, C0_BADVADDR);
941 il_bltz(p, r, tmp, label_vmalloc);
942 /* No i_nop needed here, since the next insn doesn't touch TMP. */
943
944#ifdef CONFIG_SMP
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000945# ifdef CONFIG_BUILD_ELF64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000947 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 * stored in CONTEXT.
949 */
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000950 i_dmfc0(p, ptr, C0_CONTEXT);
951 i_dsrl(p, ptr, ptr, 23);
952 i_LA_mostly(p, tmp, pgdc);
953 i_daddu(p, ptr, ptr, tmp);
954 i_dmfc0(p, tmp, C0_BADVADDR);
955 i_ld(p, ptr, rel_lo(pgdc), ptr);
956# else
957 /*
958 * 64 bit SMP running in compat space has the lower part of
959 * &pgd_current[smp_processor_id()] stored in CONTEXT.
960 */
961 if (!in_compat_space_p(pgdc))
962 panic("Invalid page directory address!");
963
964 i_dmfc0(p, ptr, C0_CONTEXT);
965 i_dsra(p, ptr, ptr, 23);
966 i_ld(p, ptr, 0, ptr);
967# endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968#else
969 i_LA_mostly(p, ptr, pgdc);
970 i_ld(p, ptr, rel_lo(pgdc), ptr);
971#endif
972
973 l_vmalloc_done(l, *p);
974 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */
975 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
976 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
977 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
978 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
979 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
980 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
981 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
982}
983
984/*
985 * BVADDR is the faulting address, PTR is scratch.
986 * PTR will hold the pgd for vmalloc.
987 */
988static __init void
989build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
990 unsigned int bvaddr, unsigned int ptr)
991{
992 long swpd = (long)swapper_pg_dir;
993
994 l_vmalloc(l, *p);
995 i_LA(p, ptr, VMALLOC_START);
996 i_dsubu(p, bvaddr, bvaddr, ptr);
997
998 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
999 il_b(p, r, label_vmalloc_done);
1000 i_lui(p, ptr, rel_hi(swpd));
1001 } else {
1002 i_LA_mostly(p, ptr, swpd);
1003 il_b(p, r, label_vmalloc_done);
1004 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1005 }
1006}
1007
Ralf Baechle875d43e2005-09-03 15:56:16 -07001008#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009
1010/*
1011 * TMP and PTR are scratch.
1012 * TMP will be clobbered, PTR will hold the pgd entry.
1013 */
1014static __init void __attribute__((unused))
1015build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1016{
1017 long pgdc = (long)pgd_current;
1018
1019 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1020#ifdef CONFIG_SMP
1021 i_mfc0(p, ptr, C0_CONTEXT);
1022 i_LA_mostly(p, tmp, pgdc);
1023 i_srl(p, ptr, ptr, 23);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 i_addu(p, ptr, tmp, ptr);
1025#else
1026 i_LA_mostly(p, ptr, pgdc);
1027#endif
1028 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1029 i_lw(p, ptr, rel_lo(pgdc), ptr);
1030 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1031 i_sll(p, tmp, tmp, PGD_T_LOG2);
1032 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1033}
1034
Ralf Baechle875d43e2005-09-03 15:56:16 -07001035#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036
1037static __init void build_adjust_context(u32 **p, unsigned int ctx)
1038{
1039 unsigned int shift = 4 - (PTE_T_LOG2 + 1);
1040 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1041
1042 switch (current_cpu_data.cputype) {
1043 case CPU_VR41XX:
1044 case CPU_VR4111:
1045 case CPU_VR4121:
1046 case CPU_VR4122:
1047 case CPU_VR4131:
1048 case CPU_VR4181:
1049 case CPU_VR4181A:
1050 case CPU_VR4133:
1051 shift += 2;
1052 break;
1053
1054 default:
1055 break;
1056 }
1057
1058 if (shift)
1059 i_SRL(p, ctx, ctx, shift);
1060 i_andi(p, ctx, ctx, mask);
1061}
1062
1063static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1064{
1065 /*
1066 * Bug workaround for the Nevada. It seems as if under certain
1067 * circumstances the move from cp0_context might produce a
1068 * bogus result when the mfc0 instruction and its consumer are
1069 * in a different cacheline or a load instruction, probably any
1070 * memory reference, is between them.
1071 */
1072 switch (current_cpu_data.cputype) {
1073 case CPU_NEVADA:
1074 i_LW(p, ptr, 0, ptr);
1075 GET_CONTEXT(p, tmp); /* get context reg */
1076 break;
1077
1078 default:
1079 GET_CONTEXT(p, tmp); /* get context reg */
1080 i_LW(p, ptr, 0, ptr);
1081 break;
1082 }
1083
1084 build_adjust_context(p, tmp);
1085 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1086}
1087
1088static __init void build_update_entries(u32 **p, unsigned int tmp,
1089 unsigned int ptep)
1090{
1091 /*
1092 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1093 * Kernel is a special case. Only a few CPUs use it.
1094 */
1095#ifdef CONFIG_64BIT_PHYS_ADDR
1096 if (cpu_has_64bits) {
1097 i_ld(p, tmp, 0, ptep); /* get even pte */
1098 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1099 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1100 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1101 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1102 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1103 } else {
1104 int pte_off_even = sizeof(pte_t) / 2;
1105 int pte_off_odd = pte_off_even + sizeof(pte_t);
1106
1107 /* The pte entries are pre-shifted */
1108 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1109 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1110 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1111 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1112 }
1113#else
1114 i_LW(p, tmp, 0, ptep); /* get even pte */
1115 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1116 if (r45k_bvahwbug())
1117 build_tlb_probe_entry(p);
1118 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1119 if (r4k_250MHZhwbug())
1120 i_mtc0(p, 0, C0_ENTRYLO0);
1121 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1122 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1123 if (r45k_bvahwbug())
1124 i_mfc0(p, tmp, C0_INDEX);
1125 if (r4k_250MHZhwbug())
1126 i_mtc0(p, 0, C0_ENTRYLO1);
1127 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1128#endif
1129}
1130
1131static void __init build_r4000_tlb_refill_handler(void)
1132{
1133 u32 *p = tlb_handler;
1134 struct label *l = labels;
1135 struct reloc *r = relocs;
1136 u32 *f;
1137 unsigned int final_len;
1138
1139 memset(tlb_handler, 0, sizeof(tlb_handler));
1140 memset(labels, 0, sizeof(labels));
1141 memset(relocs, 0, sizeof(relocs));
1142 memset(final_handler, 0, sizeof(final_handler));
1143
1144 /*
1145 * create the plain linear handler
1146 */
1147 if (bcm1250_m3_war()) {
1148 i_MFC0(&p, K0, C0_BADVADDR);
1149 i_MFC0(&p, K1, C0_ENTRYHI);
1150 i_xor(&p, K0, K0, K1);
1151 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1152 il_bnez(&p, &r, K0, label_leave);
1153 /* No need for i_nop */
1154 }
1155
Ralf Baechle875d43e2005-09-03 15:56:16 -07001156#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1158#else
1159 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1160#endif
1161
1162 build_get_ptep(&p, K0, K1);
1163 build_update_entries(&p, K0, K1);
1164 build_tlb_write_entry(&p, &l, &r, tlb_random);
1165 l_leave(&l, p);
1166 i_eret(&p); /* return from trap */
1167
Ralf Baechle875d43e2005-09-03 15:56:16 -07001168#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1170#endif
1171
1172 /*
1173 * Overflow check: For the 64bit handler, we need at least one
1174 * free instruction slot for the wrap-around branch. In worst
1175 * case, if the intended insertion point is a delay slot, we
1176 * need three, with the the second nop'ed and the third being
1177 * unused.
1178 */
Ralf Baechle875d43e2005-09-03 15:56:16 -07001179#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180 if ((p - tlb_handler) > 64)
1181 panic("TLB refill handler space exceeded");
1182#else
1183 if (((p - tlb_handler) > 63)
1184 || (((p - tlb_handler) > 61)
1185 && insn_has_bdelay(relocs, tlb_handler + 29)))
1186 panic("TLB refill handler space exceeded");
1187#endif
1188
1189 /*
1190 * Now fold the handler in the TLB refill handler space.
1191 */
Ralf Baechle875d43e2005-09-03 15:56:16 -07001192#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 f = final_handler;
1194 /* Simplest case, just copy the handler. */
1195 copy_handler(relocs, labels, tlb_handler, p, f);
1196 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -07001197#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 f = final_handler + 32;
1199 if ((p - tlb_handler) <= 32) {
1200 /* Just copy the handler. */
1201 copy_handler(relocs, labels, tlb_handler, p, f);
1202 final_len = p - tlb_handler;
1203 } else {
1204 u32 *split = tlb_handler + 30;
1205
1206 /*
1207 * Find the split point.
1208 */
1209 if (insn_has_bdelay(relocs, split - 1))
1210 split--;
1211
1212 /* Copy first part of the handler. */
1213 copy_handler(relocs, labels, tlb_handler, split, f);
1214 f += split - tlb_handler;
1215
1216 /* Insert branch. */
1217 l_split(&l, final_handler);
1218 il_b(&f, &r, label_split);
1219 if (insn_has_bdelay(relocs, split))
1220 i_nop(&f);
1221 else {
1222 copy_handler(relocs, labels, split, split + 1, f);
1223 move_labels(labels, f, f + 1, -1);
1224 f++;
1225 split++;
1226 }
1227
1228 /* Copy the rest of the handler. */
1229 copy_handler(relocs, labels, split, p, final_handler);
1230 final_len = (f - (final_handler + 32)) + (p - split);
1231 }
Ralf Baechle875d43e2005-09-03 15:56:16 -07001232#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233
1234 resolve_relocs(relocs, labels);
1235 printk("Synthesized TLB refill handler (%u instructions).\n",
1236 final_len);
1237
1238#ifdef DEBUG_TLB
1239 {
1240 int i;
1241
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001242 for (i = 0; i < final_len; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243 printk("%08x\n", final_handler[i]);
1244 }
1245#endif
1246
1247 memcpy((void *)CAC_BASE, final_handler, 0x100);
1248 flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
1249}
1250
1251/*
1252 * TLB load/store/modify handlers.
1253 *
1254 * Only the fastpath gets synthesized at runtime, the slowpath for
1255 * do_page_fault remains normal asm.
1256 */
1257extern void tlb_do_page_fault_0(void);
1258extern void tlb_do_page_fault_1(void);
1259
1260#define __tlb_handler_align \
1261 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1262
1263/*
1264 * 128 instructions for the fastpath handler is generous and should
1265 * never be exceeded.
1266 */
1267#define FASTPATH_SIZE 128
1268
1269u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1270u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1271u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1272
1273static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001274iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275{
1276#ifdef CONFIG_SMP
1277# ifdef CONFIG_64BIT_PHYS_ADDR
1278 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001279 i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 else
1281# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001282 i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283#else
1284# ifdef CONFIG_64BIT_PHYS_ADDR
1285 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001286 i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 else
1288# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001289 i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290#endif
1291}
1292
1293static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001294iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1295 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001297#ifdef CONFIG_64BIT_PHYS_ADDR
1298 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1299#endif
1300
1301 i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302#ifdef CONFIG_SMP
1303# ifdef CONFIG_64BIT_PHYS_ADDR
1304 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001305 i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 else
1307# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001308 i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309
1310 if (r10000_llsc_war())
1311 il_beqzl(p, r, pte, label_smp_pgtable_change);
1312 else
1313 il_beqz(p, r, pte, label_smp_pgtable_change);
1314
1315# ifdef CONFIG_64BIT_PHYS_ADDR
1316 if (!cpu_has_64bits) {
1317 /* no i_nop needed */
1318 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001319 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1321 il_beqz(p, r, pte, label_smp_pgtable_change);
1322 /* no i_nop needed */
1323 i_lw(p, pte, 0, ptr);
1324 } else
1325 i_nop(p);
1326# else
1327 i_nop(p);
1328# endif
1329#else
1330# ifdef CONFIG_64BIT_PHYS_ADDR
1331 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001332 i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001333 else
1334# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001335 i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336
1337# ifdef CONFIG_64BIT_PHYS_ADDR
1338 if (!cpu_has_64bits) {
1339 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001340 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1342 i_lw(p, pte, 0, ptr);
1343 }
1344# endif
1345#endif
1346}
1347
1348/*
1349 * Check if PTE is present, if not then jump to LABEL. PTR points to
1350 * the page table where this PTE is located, PTE will be re-loaded
1351 * with it's original value.
1352 */
1353static void __init
1354build_pte_present(u32 **p, struct label **l, struct reloc **r,
1355 unsigned int pte, unsigned int ptr, enum label_id lid)
1356{
1357 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1358 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1359 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001360 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361}
1362
1363/* Make PTE valid, store result in PTR. */
1364static void __init
1365build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1366 unsigned int ptr)
1367{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001368 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1369
1370 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371}
1372
1373/*
1374 * Check if PTE can be written to, if not branch to LABEL. Regardless
1375 * restore PTE with value from PTR when done.
1376 */
1377static void __init
1378build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1379 unsigned int pte, unsigned int ptr, enum label_id lid)
1380{
1381 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1382 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1383 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001384 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385}
1386
1387/* Make PTE writable, update software status bits as well, then store
1388 * at PTR.
1389 */
1390static void __init
1391build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1392 unsigned int ptr)
1393{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001394 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1395 | _PAGE_DIRTY);
1396
1397 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398}
1399
1400/*
1401 * Check if PTE can be modified, if not branch to LABEL. Regardless
1402 * restore PTE with value from PTR when done.
1403 */
1404static void __init
1405build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1406 unsigned int pte, unsigned int ptr, enum label_id lid)
1407{
1408 i_andi(p, pte, pte, _PAGE_WRITE);
1409 il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001410 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411}
1412
1413/*
1414 * R3000 style TLB load/store/modify handlers.
1415 */
1416
1417/* This places the pte in the page table at PTR into ENTRYLO0. */
1418static void __init
1419build_r3000_pte_reload(u32 **p, unsigned int ptr)
1420{
1421 i_lw(p, ptr, 0, ptr);
1422 i_nop(p); /* load delay */
1423 i_mtc0(p, ptr, C0_ENTRYLO0);
1424 i_nop(p); /* cp0 delay */
1425}
1426
1427/*
1428 * The index register may have the probe fail bit set,
1429 * because we would trap on access kseg2, i.e. without refill.
1430 */
1431static void __init
1432build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r,
1433 unsigned int tmp)
1434{
1435 i_mfc0(p, tmp, C0_INDEX);
1436 i_nop(p); /* cp0 delay */
1437 il_bltz(p, r, tmp, label_r3000_write_probe_fail);
1438 i_nop(p); /* branch delay */
1439 i_tlbwi(p);
1440 il_b(p, r, label_r3000_write_probe_ok);
1441 i_nop(p); /* branch delay */
1442 l_r3000_write_probe_fail(l, *p);
1443 i_tlbwr(p);
1444 l_r3000_write_probe_ok(l, *p);
1445}
1446
1447static void __init
1448build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1449 unsigned int ptr)
1450{
1451 long pgdc = (long)pgd_current;
1452
1453 i_mfc0(p, pte, C0_BADVADDR);
1454 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1455 i_lw(p, ptr, rel_lo(pgdc), ptr);
1456 i_srl(p, pte, pte, 22); /* load delay */
1457 i_sll(p, pte, pte, 2);
1458 i_addu(p, ptr, ptr, pte);
1459 i_mfc0(p, pte, C0_CONTEXT);
1460 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1461 i_andi(p, pte, pte, 0xffc); /* load delay */
1462 i_addu(p, ptr, ptr, pte);
1463 i_lw(p, pte, 0, ptr);
1464 i_nop(p); /* load delay */
1465 i_tlbp(p);
1466}
1467
1468static void __init
1469build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp)
1470{
1471 i_mfc0(p, tmp, C0_EPC);
1472 i_nop(p); /* cp0 delay */
1473 i_jr(p, tmp);
1474 i_rfe(p); /* branch delay */
1475}
1476
1477static void __init build_r3000_tlb_load_handler(void)
1478{
1479 u32 *p = handle_tlbl;
1480 struct label *l = labels;
1481 struct reloc *r = relocs;
1482
1483 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1484 memset(labels, 0, sizeof(labels));
1485 memset(relocs, 0, sizeof(relocs));
1486
1487 build_r3000_tlbchange_handler_head(&p, K0, K1);
1488 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001489 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490 build_make_valid(&p, &r, K0, K1);
1491 build_r3000_pte_reload(&p, K1);
1492 build_r3000_tlb_write(&p, &l, &r, K0);
1493 build_r3000_tlbchange_handler_tail(&p, K0);
1494
1495 l_nopage_tlbl(&l, p);
1496 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1497 i_nop(&p);
1498
1499 if ((p - handle_tlbl) > FASTPATH_SIZE)
1500 panic("TLB load handler fastpath space exceeded");
1501
1502 resolve_relocs(relocs, labels);
1503 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1504 (unsigned int)(p - handle_tlbl));
1505
1506#ifdef DEBUG_TLB
1507 {
1508 int i;
1509
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001510 for (i = 0; i < (p - handle_tlbl); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 printk("%08x\n", handle_tlbl[i]);
1512 }
1513#endif
1514
1515 flush_icache_range((unsigned long)handle_tlbl,
1516 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1517}
1518
1519static void __init build_r3000_tlb_store_handler(void)
1520{
1521 u32 *p = handle_tlbs;
1522 struct label *l = labels;
1523 struct reloc *r = relocs;
1524
1525 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1526 memset(labels, 0, sizeof(labels));
1527 memset(relocs, 0, sizeof(relocs));
1528
1529 build_r3000_tlbchange_handler_head(&p, K0, K1);
1530 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001531 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 build_make_write(&p, &r, K0, K1);
1533 build_r3000_pte_reload(&p, K1);
1534 build_r3000_tlb_write(&p, &l, &r, K0);
1535 build_r3000_tlbchange_handler_tail(&p, K0);
1536
1537 l_nopage_tlbs(&l, p);
1538 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1539 i_nop(&p);
1540
1541 if ((p - handle_tlbs) > FASTPATH_SIZE)
1542 panic("TLB store handler fastpath space exceeded");
1543
1544 resolve_relocs(relocs, labels);
1545 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1546 (unsigned int)(p - handle_tlbs));
1547
1548#ifdef DEBUG_TLB
1549 {
1550 int i;
1551
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001552 for (i = 0; i < (p - handle_tlbs); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 printk("%08x\n", handle_tlbs[i]);
1554 }
1555#endif
1556
1557 flush_icache_range((unsigned long)handle_tlbs,
1558 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1559}
1560
1561static void __init build_r3000_tlb_modify_handler(void)
1562{
1563 u32 *p = handle_tlbm;
1564 struct label *l = labels;
1565 struct reloc *r = relocs;
1566
1567 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1568 memset(labels, 0, sizeof(labels));
1569 memset(relocs, 0, sizeof(relocs));
1570
1571 build_r3000_tlbchange_handler_head(&p, K0, K1);
1572 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001573 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574 build_make_write(&p, &r, K0, K1);
1575 build_r3000_pte_reload(&p, K1);
1576 i_tlbwi(&p);
1577 build_r3000_tlbchange_handler_tail(&p, K0);
1578
1579 l_nopage_tlbm(&l, p);
1580 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1581 i_nop(&p);
1582
1583 if ((p - handle_tlbm) > FASTPATH_SIZE)
1584 panic("TLB modify handler fastpath space exceeded");
1585
1586 resolve_relocs(relocs, labels);
1587 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1588 (unsigned int)(p - handle_tlbm));
1589
1590#ifdef DEBUG_TLB
1591 {
1592 int i;
1593
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001594 for (i = 0; i < (p - handle_tlbm); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595 printk("%08x\n", handle_tlbm[i]);
1596 }
1597#endif
1598
1599 flush_icache_range((unsigned long)handle_tlbm,
1600 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1601}
1602
1603/*
1604 * R4000 style TLB load/store/modify handlers.
1605 */
1606static void __init
1607build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1608 struct reloc **r, unsigned int pte,
1609 unsigned int ptr)
1610{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001611#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1613#else
1614 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1615#endif
1616
1617 i_MFC0(p, pte, C0_BADVADDR);
1618 i_LW(p, ptr, 0, ptr);
1619 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1620 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1621 i_ADDU(p, ptr, ptr, pte);
1622
1623#ifdef CONFIG_SMP
1624 l_smp_pgtable_change(l, *p);
1625# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001626 iPTE_LW(p, l, pte, ptr); /* get even pte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627 build_tlb_probe_entry(p);
1628}
1629
1630static void __init
1631build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1632 struct reloc **r, unsigned int tmp,
1633 unsigned int ptr)
1634{
1635 i_ori(p, ptr, ptr, sizeof(pte_t));
1636 i_xori(p, ptr, ptr, sizeof(pte_t));
1637 build_update_entries(p, tmp, ptr);
1638 build_tlb_write_entry(p, l, r, tlb_indexed);
1639 l_leave(l, *p);
1640 i_eret(p); /* return from trap */
1641
Ralf Baechle875d43e2005-09-03 15:56:16 -07001642#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001643 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1644#endif
1645}
1646
1647static void __init build_r4000_tlb_load_handler(void)
1648{
1649 u32 *p = handle_tlbl;
1650 struct label *l = labels;
1651 struct reloc *r = relocs;
1652
1653 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1654 memset(labels, 0, sizeof(labels));
1655 memset(relocs, 0, sizeof(relocs));
1656
1657 if (bcm1250_m3_war()) {
1658 i_MFC0(&p, K0, C0_BADVADDR);
1659 i_MFC0(&p, K1, C0_ENTRYHI);
1660 i_xor(&p, K0, K0, K1);
1661 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1662 il_bnez(&p, &r, K0, label_leave);
1663 /* No need for i_nop */
1664 }
1665
1666 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1667 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1668 build_make_valid(&p, &r, K0, K1);
1669 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1670
1671 l_nopage_tlbl(&l, p);
1672 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1673 i_nop(&p);
1674
1675 if ((p - handle_tlbl) > FASTPATH_SIZE)
1676 panic("TLB load handler fastpath space exceeded");
1677
1678 resolve_relocs(relocs, labels);
1679 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1680 (unsigned int)(p - handle_tlbl));
1681
1682#ifdef DEBUG_TLB
1683 {
1684 int i;
1685
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001686 for (i = 0; i < (p - handle_tlbl); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 printk("%08x\n", handle_tlbl[i]);
1688 }
1689#endif
1690
1691 flush_icache_range((unsigned long)handle_tlbl,
1692 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1693}
1694
1695static void __init build_r4000_tlb_store_handler(void)
1696{
1697 u32 *p = handle_tlbs;
1698 struct label *l = labels;
1699 struct reloc *r = relocs;
1700
1701 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1702 memset(labels, 0, sizeof(labels));
1703 memset(relocs, 0, sizeof(relocs));
1704
1705 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1706 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1707 build_make_write(&p, &r, K0, K1);
1708 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1709
1710 l_nopage_tlbs(&l, p);
1711 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1712 i_nop(&p);
1713
1714 if ((p - handle_tlbs) > FASTPATH_SIZE)
1715 panic("TLB store handler fastpath space exceeded");
1716
1717 resolve_relocs(relocs, labels);
1718 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1719 (unsigned int)(p - handle_tlbs));
1720
1721#ifdef DEBUG_TLB
1722 {
1723 int i;
1724
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001725 for (i = 0; i < (p - handle_tlbs); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726 printk("%08x\n", handle_tlbs[i]);
1727 }
1728#endif
1729
1730 flush_icache_range((unsigned long)handle_tlbs,
1731 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1732}
1733
1734static void __init build_r4000_tlb_modify_handler(void)
1735{
1736 u32 *p = handle_tlbm;
1737 struct label *l = labels;
1738 struct reloc *r = relocs;
1739
1740 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1741 memset(labels, 0, sizeof(labels));
1742 memset(relocs, 0, sizeof(relocs));
1743
1744 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1745 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1746 /* Present and writable bits set, set accessed and dirty bits. */
1747 build_make_write(&p, &r, K0, K1);
1748 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1749
1750 l_nopage_tlbm(&l, p);
1751 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1752 i_nop(&p);
1753
1754 if ((p - handle_tlbm) > FASTPATH_SIZE)
1755 panic("TLB modify handler fastpath space exceeded");
1756
1757 resolve_relocs(relocs, labels);
1758 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1759 (unsigned int)(p - handle_tlbm));
1760
1761#ifdef DEBUG_TLB
1762 {
1763 int i;
1764
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001765 for (i = 0; i < (p - handle_tlbm); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 printk("%08x\n", handle_tlbm[i]);
1767 }
1768#endif
1769
1770 flush_icache_range((unsigned long)handle_tlbm,
1771 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1772}
1773
1774void __init build_tlb_refill_handler(void)
1775{
1776 /*
1777 * The refill handler is generated per-CPU, multi-node systems
1778 * may have local storage for it. The other handlers are only
1779 * needed once.
1780 */
1781 static int run_once = 0;
1782
1783 switch (current_cpu_data.cputype) {
1784 case CPU_R2000:
1785 case CPU_R3000:
1786 case CPU_R3000A:
1787 case CPU_R3081E:
1788 case CPU_TX3912:
1789 case CPU_TX3922:
1790 case CPU_TX3927:
1791 build_r3000_tlb_refill_handler();
1792 if (!run_once) {
1793 build_r3000_tlb_load_handler();
1794 build_r3000_tlb_store_handler();
1795 build_r3000_tlb_modify_handler();
1796 run_once++;
1797 }
1798 break;
1799
1800 case CPU_R6000:
1801 case CPU_R6000A:
1802 panic("No R6000 TLB refill handler yet");
1803 break;
1804
1805 case CPU_R8000:
1806 panic("No R8000 TLB refill handler yet");
1807 break;
1808
1809 default:
1810 build_r4000_tlb_refill_handler();
1811 if (!run_once) {
1812 build_r4000_tlb_load_handler();
1813 build_r4000_tlb_store_handler();
1814 build_r4000_tlb_modify_handler();
1815 run_once++;
1816 }
1817 }
1818}