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Mugunthan V Ndf828592012-03-18 20:17:54 +00001/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
Richard Cochran2e5b38a2012-10-29 08:45:20 +000027#include <linux/net_tstamp.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000028#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
Mugunthan V Nf150bd72012-07-17 08:09:50 +000031#include <linux/pm_runtime.h>
Mugunthan V N2eb32b02012-07-30 10:17:14 +000032#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
Mugunthan V N3b72c2f2013-02-05 08:26:48 +000035#include <linux/if_vlan.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000036
37#include <linux/platform_data/cpsw.h>
Mugunthan V N739683b2013-06-06 23:45:14 +053038#include <linux/pinctrl/consumer.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000039
40#include "cpsw_ale.h"
Richard Cochran2e5b38a2012-10-29 08:45:20 +000041#include "cpts.h"
Mugunthan V Ndf828592012-03-18 20:17:54 +000042#include "davinci_cpdma.h"
43
44#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
51 NETIF_MSG_RX_STATUS)
52
53#define cpsw_info(priv, type, format, ...) \
54do { \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
57} while (0)
58
59#define cpsw_err(priv, type, format, ...) \
60do { \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
63} while (0)
64
65#define cpsw_dbg(priv, type, format, ...) \
66do { \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
69} while (0)
70
71#define cpsw_notice(priv, type, format, ...) \
72do { \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
75} while (0)
76
Mugunthan V N5c50a852012-10-29 08:45:11 +000077#define ALE_ALL_PORTS 0x7
78
Mugunthan V Ndf828592012-03-18 20:17:54 +000079#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
82
Richard Cochrane90cfac2012-10-29 08:45:14 +000083#define CPSW_VERSION_1 0x19010a
84#define CPSW_VERSION_2 0x19010c
Richard Cochran549985e2012-11-14 09:07:56 +000085
86#define HOST_PORT_NUM 0
87#define SLIVER_SIZE 0x40
88
89#define CPSW1_HOST_PORT_OFFSET 0x028
90#define CPSW1_SLAVE_OFFSET 0x050
91#define CPSW1_SLAVE_SIZE 0x040
92#define CPSW1_CPDMA_OFFSET 0x100
93#define CPSW1_STATERAM_OFFSET 0x200
Mugunthan V Nd9718542013-07-23 15:38:17 +053094#define CPSW1_HW_STATS 0x400
Richard Cochran549985e2012-11-14 09:07:56 +000095#define CPSW1_CPTS_OFFSET 0x500
96#define CPSW1_ALE_OFFSET 0x600
97#define CPSW1_SLIVER_OFFSET 0x700
98
99#define CPSW2_HOST_PORT_OFFSET 0x108
100#define CPSW2_SLAVE_OFFSET 0x200
101#define CPSW2_SLAVE_SIZE 0x100
102#define CPSW2_CPDMA_OFFSET 0x800
Mugunthan V Nd9718542013-07-23 15:38:17 +0530103#define CPSW2_HW_STATS 0x900
Richard Cochran549985e2012-11-14 09:07:56 +0000104#define CPSW2_STATERAM_OFFSET 0xa00
105#define CPSW2_CPTS_OFFSET 0xc00
106#define CPSW2_ALE_OFFSET 0xd00
107#define CPSW2_SLIVER_OFFSET 0xd80
108#define CPSW2_BD_OFFSET 0x2000
109
Mugunthan V Ndf828592012-03-18 20:17:54 +0000110#define CPDMA_RXTHRESH 0x0c0
111#define CPDMA_RXFREE 0x0e0
112#define CPDMA_TXHDP 0x00
113#define CPDMA_RXHDP 0x20
114#define CPDMA_TXCP 0x40
115#define CPDMA_RXCP 0x60
116
Mugunthan V Ndf828592012-03-18 20:17:54 +0000117#define CPSW_POLL_WEIGHT 64
118#define CPSW_MIN_PACKET_SIZE 60
119#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
120
121#define RX_PRIORITY_MAPPING 0x76543210
122#define TX_PRIORITY_MAPPING 0x33221100
123#define CPDMA_TX_PRIORITY_MAP 0x76543210
124
Mugunthan V N3b72c2f2013-02-05 08:26:48 +0000125#define CPSW_VLAN_AWARE BIT(1)
126#define CPSW_ALE_VLAN_AWARE 1
127
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000128#define CPSW_FIFO_NORMAL_MODE (0 << 15)
129#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
130#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
131
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000132#define CPSW_INTPACEEN (0x3f << 16)
133#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
134#define CPSW_CMINTMAX_CNT 63
135#define CPSW_CMINTMIN_CNT 2
136#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
137#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
138
Mugunthan V Ndf828592012-03-18 20:17:54 +0000139#define cpsw_enable_irq(priv) \
140 do { \
141 u32 i; \
142 for (i = 0; i < priv->num_irqs; i++) \
143 enable_irq(priv->irqs_table[i]); \
144 } while (0);
145#define cpsw_disable_irq(priv) \
146 do { \
147 u32 i; \
148 for (i = 0; i < priv->num_irqs; i++) \
149 disable_irq_nosync(priv->irqs_table[i]); \
150 } while (0);
151
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +0000152#define cpsw_slave_index(priv) \
153 ((priv->data.dual_emac) ? priv->emac_port : \
154 priv->data.active_slave)
155
Mugunthan V Ndf828592012-03-18 20:17:54 +0000156static int debug_level;
157module_param(debug_level, int, 0);
158MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
159
160static int ale_ageout = 10;
161module_param(ale_ageout, int, 0);
162MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
163
164static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
165module_param(rx_packet_max, int, 0);
166MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
167
Richard Cochran996a5c22012-10-29 08:45:12 +0000168struct cpsw_wr_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000169 u32 id_ver;
170 u32 soft_reset;
171 u32 control;
172 u32 int_control;
173 u32 rx_thresh_en;
174 u32 rx_en;
175 u32 tx_en;
176 u32 misc_en;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000177 u32 mem_allign1[8];
178 u32 rx_thresh_stat;
179 u32 rx_stat;
180 u32 tx_stat;
181 u32 misc_stat;
182 u32 mem_allign2[8];
183 u32 rx_imax;
184 u32 tx_imax;
185
Mugunthan V Ndf828592012-03-18 20:17:54 +0000186};
187
Richard Cochran996a5c22012-10-29 08:45:12 +0000188struct cpsw_ss_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000189 u32 id_ver;
190 u32 control;
191 u32 soft_reset;
192 u32 stat_port_en;
193 u32 ptype;
Richard Cochranbd357af2012-10-29 08:45:13 +0000194 u32 soft_idle;
195 u32 thru_rate;
196 u32 gap_thresh;
197 u32 tx_start_wds;
198 u32 flow_control;
199 u32 vlan_ltype;
200 u32 ts_ltype;
201 u32 dlr_ltype;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000202};
203
Richard Cochran9750a3a2012-10-29 08:45:15 +0000204/* CPSW_PORT_V1 */
205#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
206#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
207#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
208#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
209#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
210#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
211#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
212#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
213
214/* CPSW_PORT_V2 */
215#define CPSW2_CONTROL 0x00 /* Control Register */
216#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
217#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
218#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
219#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
220#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
221#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
222
223/* CPSW_PORT_V1 and V2 */
224#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
225#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
226#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
227
228/* CPSW_PORT_V2 only */
229#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
230#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
231#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
237
238/* Bit definitions for the CPSW2_CONTROL register */
239#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
240#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
241#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
242#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
243#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
244#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
245#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
246#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
247#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
248#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
249#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
250#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
251#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
252#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
253#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
254#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
255
256#define CTRL_TS_BITS \
257 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
258 TS_ANNEX_D_EN | TS_LTYPE1_EN)
259
260#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
261#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
262#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
263
264/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
265#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
266#define TS_SEQ_ID_OFFSET_MASK (0x3f)
267#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
268#define TS_MSG_TYPE_EN_MASK (0xffff)
269
270/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
271#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
Mugunthan V Ndf828592012-03-18 20:17:54 +0000272
Richard Cochran2e5b38a2012-10-29 08:45:20 +0000273/* Bit definitions for the CPSW1_TS_CTL register */
274#define CPSW_V1_TS_RX_EN BIT(0)
275#define CPSW_V1_TS_TX_EN BIT(4)
276#define CPSW_V1_MSG_TYPE_OFS 16
277
278/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
279#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
280
Mugunthan V Ndf828592012-03-18 20:17:54 +0000281struct cpsw_host_regs {
282 u32 max_blks;
283 u32 blk_cnt;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000284 u32 tx_in_ctl;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000285 u32 port_vlan;
286 u32 tx_pri_map;
287 u32 cpdma_tx_pri_map;
288 u32 cpdma_rx_chan_map;
289};
290
291struct cpsw_sliver_regs {
292 u32 id_ver;
293 u32 mac_control;
294 u32 mac_status;
295 u32 soft_reset;
296 u32 rx_maxlen;
297 u32 __reserved_0;
298 u32 rx_pause;
299 u32 tx_pause;
300 u32 __reserved_1;
301 u32 rx_pri_map;
302};
303
Mugunthan V Nd9718542013-07-23 15:38:17 +0530304struct cpsw_hw_stats {
305 u32 rxgoodframes;
306 u32 rxbroadcastframes;
307 u32 rxmulticastframes;
308 u32 rxpauseframes;
309 u32 rxcrcerrors;
310 u32 rxaligncodeerrors;
311 u32 rxoversizedframes;
312 u32 rxjabberframes;
313 u32 rxundersizedframes;
314 u32 rxfragments;
315 u32 __pad_0[2];
316 u32 rxoctets;
317 u32 txgoodframes;
318 u32 txbroadcastframes;
319 u32 txmulticastframes;
320 u32 txpauseframes;
321 u32 txdeferredframes;
322 u32 txcollisionframes;
323 u32 txsinglecollframes;
324 u32 txmultcollframes;
325 u32 txexcessivecollisions;
326 u32 txlatecollisions;
327 u32 txunderrun;
328 u32 txcarriersenseerrors;
329 u32 txoctets;
330 u32 octetframes64;
331 u32 octetframes65t127;
332 u32 octetframes128t255;
333 u32 octetframes256t511;
334 u32 octetframes512t1023;
335 u32 octetframes1024tup;
336 u32 netoctets;
337 u32 rxsofoverruns;
338 u32 rxmofoverruns;
339 u32 rxdmaoverruns;
340};
341
Mugunthan V Ndf828592012-03-18 20:17:54 +0000342struct cpsw_slave {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000343 void __iomem *regs;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000344 struct cpsw_sliver_regs __iomem *sliver;
345 int slave_num;
346 u32 mac_control;
347 struct cpsw_slave_data *data;
348 struct phy_device *phy;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000349 struct net_device *ndev;
350 u32 port_vlan;
351 u32 open_stat;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000352};
353
Richard Cochran9750a3a2012-10-29 08:45:15 +0000354static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
355{
356 return __raw_readl(slave->regs + offset);
357}
358
359static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
360{
361 __raw_writel(val, slave->regs + offset);
362}
363
Mugunthan V Ndf828592012-03-18 20:17:54 +0000364struct cpsw_priv {
365 spinlock_t lock;
366 struct platform_device *pdev;
367 struct net_device *ndev;
368 struct resource *cpsw_res;
Richard Cochrana65dd5b2012-11-02 22:25:29 +0000369 struct resource *cpsw_wr_res;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000370 struct napi_struct napi;
371 struct device *dev;
372 struct cpsw_platform_data data;
Richard Cochran996a5c22012-10-29 08:45:12 +0000373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +0530375 u8 __iomem *hw_stats;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
Richard Cochrane90cfac2012-10-29 08:45:14 +0000378 u32 version;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000379 u32 coal_intvl;
380 u32 bus_freq_mhz;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000381 struct net_device_stats stats;
382 int rx_packet_max;
383 int host_port;
384 struct clk *clk;
385 u8 mac_addr[ETH_ALEN];
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpdma_chan *txch, *rxch;
389 struct cpsw_ale *ale;
390 /* snapshot of IRQ numbers */
391 u32 irqs_table[4];
392 u32 num_irqs;
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000393 bool irq_enabled;
Mugunthan V N9232b162013-02-11 09:52:19 +0000394 struct cpts *cpts;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000395 u32 emac_port;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000396};
397
Mugunthan V Nd9718542013-07-23 15:38:17 +0530398struct cpsw_stats {
399 char stat_string[ETH_GSTRING_LEN];
400 int type;
401 int sizeof_stat;
402 int stat_offset;
403};
404
405enum {
406 CPSW_STATS,
407 CPDMA_RX_STATS,
408 CPDMA_TX_STATS,
409};
410
411#define CPSW_STAT(m) CPSW_STATS, \
412 sizeof(((struct cpsw_hw_stats *)0)->m), \
413 offsetof(struct cpsw_hw_stats, m)
414#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
415 sizeof(((struct cpdma_chan_stats *)0)->m), \
416 offsetof(struct cpdma_chan_stats, m)
417#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
418 sizeof(((struct cpdma_chan_stats *)0)->m), \
419 offsetof(struct cpdma_chan_stats, m)
420
421static const struct cpsw_stats cpsw_gstrings_stats[] = {
422 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
423 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
424 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
425 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
426 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
427 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
428 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
429 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
430 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
431 { "Rx Fragments", CPSW_STAT(rxfragments) },
432 { "Rx Octets", CPSW_STAT(rxoctets) },
433 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
434 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
435 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
436 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
437 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
438 { "Collisions", CPSW_STAT(txcollisionframes) },
439 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
440 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
441 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
442 { "Late Collisions", CPSW_STAT(txlatecollisions) },
443 { "Tx Underrun", CPSW_STAT(txunderrun) },
444 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
445 { "Tx Octets", CPSW_STAT(txoctets) },
446 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
447 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
448 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
449 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
450 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
451 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
452 { "Net Octets", CPSW_STAT(netoctets) },
453 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
454 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
455 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
456 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
457 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
458 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
459 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
460 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
461 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
462 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
463 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
464 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
465 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
466 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
467 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
468 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
469 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
470 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
471 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
472 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
473 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
474 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
475 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
476 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
477 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
478 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
479 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
480 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
481 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
482};
483
484#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
485
Mugunthan V Ndf828592012-03-18 20:17:54 +0000486#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000487#define for_each_slave(priv, func, arg...) \
488 do { \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000489 struct cpsw_slave *slave; \
490 int n; \
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000491 if (priv->data.dual_emac) \
492 (func)((priv)->slaves + priv->emac_port, ##arg);\
493 else \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000494 for (n = (priv)->data.slaves, \
495 slave = (priv)->slaves; \
496 n; n--) \
497 (func)(slave++, ##arg); \
Mugunthan V Ndf828592012-03-18 20:17:54 +0000498 } while (0)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000499#define cpsw_get_slave_ndev(priv, __slave_no__) \
500 (priv->slaves[__slave_no__].ndev)
501#define cpsw_get_slave_priv(priv, __slave_no__) \
502 ((priv->slaves[__slave_no__].ndev) ? \
503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
504
505#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
506 do { \
507 if (!priv->data.dual_emac) \
508 break; \
509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
510 ndev = cpsw_get_slave_ndev(priv, 0); \
511 priv = netdev_priv(ndev); \
512 skb->dev = ndev; \
513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
514 ndev = cpsw_get_slave_ndev(priv, 1); \
515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } \
518 } while (0)
519#define cpsw_add_mcast(priv, addr) \
520 do { \
521 if (priv->data.dual_emac) { \
522 struct cpsw_slave *slave = priv->slaves + \
523 priv->emac_port; \
524 int slave_port = cpsw_get_slave_port(priv, \
525 slave->slave_num); \
526 cpsw_ale_add_mcast(priv->ale, addr, \
527 1 << slave_port | 1 << priv->host_port, \
528 ALE_VLAN, slave->port_vlan, 0); \
529 } else { \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 ALE_ALL_PORTS << priv->host_port, \
532 0, 0, 0); \
533 } \
534 } while (0)
535
536static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
537{
538 if (priv->host_port == 0)
539 return slave_num + 1;
540 else
541 return slave_num;
542}
Mugunthan V Ndf828592012-03-18 20:17:54 +0000543
Mugunthan V N5c50a852012-10-29 08:45:11 +0000544static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
545{
546 struct cpsw_priv *priv = netdev_priv(ndev);
547
548 if (ndev->flags & IFF_PROMISC) {
549 /* Enable promiscuous mode */
550 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
551 return;
552 }
553
554 /* Clear all mcast from ALE */
555 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
556
557 if (!netdev_mc_empty(ndev)) {
558 struct netdev_hw_addr *ha;
559
560 /* program multicast address list into ALE register */
561 netdev_for_each_mc_addr(ha, ndev) {
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000562 cpsw_add_mcast(priv, (u8 *)ha->addr);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000563 }
564 }
565}
566
Mugunthan V Ndf828592012-03-18 20:17:54 +0000567static void cpsw_intr_enable(struct cpsw_priv *priv)
568{
Richard Cochran996a5c22012-10-29 08:45:12 +0000569 __raw_writel(0xFF, &priv->wr_regs->tx_en);
570 __raw_writel(0xFF, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000571
572 cpdma_ctlr_int_ctrl(priv->dma, true);
573 return;
574}
575
576static void cpsw_intr_disable(struct cpsw_priv *priv)
577{
Richard Cochran996a5c22012-10-29 08:45:12 +0000578 __raw_writel(0, &priv->wr_regs->tx_en);
579 __raw_writel(0, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000580
581 cpdma_ctlr_int_ctrl(priv->dma, false);
582 return;
583}
584
585void cpsw_tx_handler(void *token, int len, int status)
586{
587 struct sk_buff *skb = token;
588 struct net_device *ndev = skb->dev;
589 struct cpsw_priv *priv = netdev_priv(ndev);
590
Mugunthan V Nfae50822013-01-17 06:31:34 +0000591 /* Check whether the queue is stopped due to stalled tx dma, if the
592 * queue is stopped then start the queue as we have free desc for tx
593 */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000594 if (unlikely(netif_queue_stopped(ndev)))
Mugunthan V Nb56d6b3f2013-03-27 04:41:59 +0000595 netif_wake_queue(ndev);
Mugunthan V N9232b162013-02-11 09:52:19 +0000596 cpts_tx_timestamp(priv->cpts, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000597 priv->stats.tx_packets++;
598 priv->stats.tx_bytes += len;
599 dev_kfree_skb_any(skb);
600}
601
602void cpsw_rx_handler(void *token, int len, int status)
603{
604 struct sk_buff *skb = token;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000605 struct sk_buff *new_skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000606 struct net_device *ndev = skb->dev;
607 struct cpsw_priv *priv = netdev_priv(ndev);
608 int ret = 0;
609
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000610 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
611
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000612 if (unlikely(status < 0)) {
613 /* the interface is going down, skbs are purged */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000614 dev_kfree_skb_any(skb);
615 return;
616 }
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000617
618 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
619 if (new_skb) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000620 skb_put(skb, len);
Mugunthan V N9232b162013-02-11 09:52:19 +0000621 cpts_rx_timestamp(priv->cpts, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000622 skb->protocol = eth_type_trans(skb, ndev);
623 netif_receive_skb(skb);
624 priv->stats.rx_bytes += len;
625 priv->stats.rx_packets++;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000626 } else {
627 priv->stats.rx_dropped++;
628 new_skb = skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000629 }
630
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000631 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
632 skb_tailroom(new_skb), 0);
633 if (WARN_ON(ret < 0))
634 dev_kfree_skb_any(new_skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000635}
636
637static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
638{
639 struct cpsw_priv *priv = dev_id;
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000640 u32 rx, tx, rx_thresh;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000641
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000642 rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
643 rx = __raw_readl(&priv->wr_regs->rx_stat);
644 tx = __raw_readl(&priv->wr_regs->tx_stat);
645 if (!rx_thresh && !rx && !tx)
646 return IRQ_NONE;
647
648 cpsw_intr_disable(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000649 if (priv->irq_enabled == true) {
650 cpsw_disable_irq(priv);
651 priv->irq_enabled = false;
652 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000653
654 if (netif_running(priv->ndev)) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000655 napi_schedule(&priv->napi);
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000656 return IRQ_HANDLED;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000657 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000658
659 priv = cpsw_get_slave_priv(priv, 1);
660 if (!priv)
661 return IRQ_NONE;
662
663 if (netif_running(priv->ndev)) {
664 napi_schedule(&priv->napi);
665 return IRQ_HANDLED;
666 }
667 return IRQ_NONE;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000668}
669
Mugunthan V Ndf828592012-03-18 20:17:54 +0000670static int cpsw_poll(struct napi_struct *napi, int budget)
671{
672 struct cpsw_priv *priv = napi_to_priv(napi);
673 int num_tx, num_rx;
674
675 num_tx = cpdma_chan_process(priv->txch, 128);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000676 if (num_tx)
677 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
678
Mugunthan V Ndf828592012-03-18 20:17:54 +0000679 num_rx = cpdma_chan_process(priv->rxch, budget);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000680 if (num_rx < budget) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000681 struct cpsw_priv *prim_cpsw;
682
Mugunthan V N510a1e722013-02-17 22:19:20 +0000683 napi_complete(napi);
684 cpsw_intr_enable(priv);
685 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000686 prim_cpsw = cpsw_get_slave_priv(priv, 0);
687 if (prim_cpsw->irq_enabled == false) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000688 prim_cpsw->irq_enabled = true;
Mugunthan V Naf5c6df2013-05-02 01:52:11 +0000689 cpsw_enable_irq(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000690 }
Mugunthan V N510a1e722013-02-17 22:19:20 +0000691 }
Mugunthan V Ndf828592012-03-18 20:17:54 +0000692
693 if (num_rx || num_tx)
694 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
695 num_rx, num_tx);
696
Mugunthan V Ndf828592012-03-18 20:17:54 +0000697 return num_rx;
698}
699
700static inline void soft_reset(const char *module, void __iomem *reg)
701{
702 unsigned long timeout = jiffies + HZ;
703
704 __raw_writel(1, reg);
705 do {
706 cpu_relax();
707 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
708
709 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
710}
711
712#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
713 ((mac)[2] << 16) | ((mac)[3] << 24))
714#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
715
716static void cpsw_set_slave_mac(struct cpsw_slave *slave,
717 struct cpsw_priv *priv)
718{
Richard Cochran9750a3a2012-10-29 08:45:15 +0000719 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
720 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000721}
722
723static void _cpsw_adjust_link(struct cpsw_slave *slave,
724 struct cpsw_priv *priv, bool *link)
725{
726 struct phy_device *phy = slave->phy;
727 u32 mac_control = 0;
728 u32 slave_port;
729
730 if (!phy)
731 return;
732
733 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
734
735 if (phy->link) {
736 mac_control = priv->data.mac_control;
737
738 /* enable forwarding */
739 cpsw_ale_control_set(priv->ale, slave_port,
740 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
741
742 if (phy->speed == 1000)
743 mac_control |= BIT(7); /* GIGABITEN */
744 if (phy->duplex)
745 mac_control |= BIT(0); /* FULLDUPLEXEN */
Daniel Mack342b7b72012-09-27 09:19:34 +0000746
747 /* set speed_in input in case RMII mode is used in 100Mbps */
748 if (phy->speed == 100)
749 mac_control |= BIT(15);
750
Mugunthan V Ndf828592012-03-18 20:17:54 +0000751 *link = true;
752 } else {
753 mac_control = 0;
754 /* disable forwarding */
755 cpsw_ale_control_set(priv->ale, slave_port,
756 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
757 }
758
759 if (mac_control != slave->mac_control) {
760 phy_print_status(phy);
761 __raw_writel(mac_control, &slave->sliver->mac_control);
762 }
763
764 slave->mac_control = mac_control;
765}
766
767static void cpsw_adjust_link(struct net_device *ndev)
768{
769 struct cpsw_priv *priv = netdev_priv(ndev);
770 bool link = false;
771
772 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
773
774 if (link) {
775 netif_carrier_on(ndev);
776 if (netif_running(ndev))
777 netif_wake_queue(ndev);
778 } else {
779 netif_carrier_off(ndev);
780 netif_stop_queue(ndev);
781 }
782}
783
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000784static int cpsw_get_coalesce(struct net_device *ndev,
785 struct ethtool_coalesce *coal)
786{
787 struct cpsw_priv *priv = netdev_priv(ndev);
788
789 coal->rx_coalesce_usecs = priv->coal_intvl;
790 return 0;
791}
792
793static int cpsw_set_coalesce(struct net_device *ndev,
794 struct ethtool_coalesce *coal)
795{
796 struct cpsw_priv *priv = netdev_priv(ndev);
797 u32 int_ctrl;
798 u32 num_interrupts = 0;
799 u32 prescale = 0;
800 u32 addnl_dvdr = 1;
801 u32 coal_intvl = 0;
802
803 if (!coal->rx_coalesce_usecs)
804 return -EINVAL;
805
806 coal_intvl = coal->rx_coalesce_usecs;
807
808 int_ctrl = readl(&priv->wr_regs->int_control);
809 prescale = priv->bus_freq_mhz * 4;
810
811 if (coal_intvl < CPSW_CMINTMIN_INTVL)
812 coal_intvl = CPSW_CMINTMIN_INTVL;
813
814 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
815 /* Interrupt pacer works with 4us Pulse, we can
816 * throttle further by dilating the 4us pulse.
817 */
818 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
819
820 if (addnl_dvdr > 1) {
821 prescale *= addnl_dvdr;
822 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
823 coal_intvl = (CPSW_CMINTMAX_INTVL
824 * addnl_dvdr);
825 } else {
826 addnl_dvdr = 1;
827 coal_intvl = CPSW_CMINTMAX_INTVL;
828 }
829 }
830
831 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
832 writel(num_interrupts, &priv->wr_regs->rx_imax);
833 writel(num_interrupts, &priv->wr_regs->tx_imax);
834
835 int_ctrl |= CPSW_INTPACEEN;
836 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
837 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
838 writel(int_ctrl, &priv->wr_regs->int_control);
839
840 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
841 if (priv->data.dual_emac) {
842 int i;
843
844 for (i = 0; i < priv->data.slaves; i++) {
845 priv = netdev_priv(priv->slaves[i].ndev);
846 priv->coal_intvl = coal_intvl;
847 }
848 } else {
849 priv->coal_intvl = coal_intvl;
850 }
851
852 return 0;
853}
854
Mugunthan V Nd9718542013-07-23 15:38:17 +0530855static int cpsw_get_sset_count(struct net_device *ndev, int sset)
856{
857 switch (sset) {
858 case ETH_SS_STATS:
859 return CPSW_STATS_LEN;
860 default:
861 return -EOPNOTSUPP;
862 }
863}
864
865static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
866{
867 u8 *p = data;
868 int i;
869
870 switch (stringset) {
871 case ETH_SS_STATS:
872 for (i = 0; i < CPSW_STATS_LEN; i++) {
873 memcpy(p, cpsw_gstrings_stats[i].stat_string,
874 ETH_GSTRING_LEN);
875 p += ETH_GSTRING_LEN;
876 }
877 break;
878 }
879}
880
881static void cpsw_get_ethtool_stats(struct net_device *ndev,
882 struct ethtool_stats *stats, u64 *data)
883{
884 struct cpsw_priv *priv = netdev_priv(ndev);
885 struct cpdma_chan_stats rx_stats;
886 struct cpdma_chan_stats tx_stats;
887 u32 val;
888 u8 *p;
889 int i;
890
891 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
892 cpdma_chan_get_stats(priv->rxch, &rx_stats);
893 cpdma_chan_get_stats(priv->txch, &tx_stats);
894
895 for (i = 0; i < CPSW_STATS_LEN; i++) {
896 switch (cpsw_gstrings_stats[i].type) {
897 case CPSW_STATS:
898 val = readl(priv->hw_stats +
899 cpsw_gstrings_stats[i].stat_offset);
900 data[i] = val;
901 break;
902
903 case CPDMA_RX_STATS:
904 p = (u8 *)&rx_stats +
905 cpsw_gstrings_stats[i].stat_offset;
906 data[i] = *(u32 *)p;
907 break;
908
909 case CPDMA_TX_STATS:
910 p = (u8 *)&tx_stats +
911 cpsw_gstrings_stats[i].stat_offset;
912 data[i] = *(u32 *)p;
913 break;
914 }
915 }
916}
917
Mugunthan V Ndf828592012-03-18 20:17:54 +0000918static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
919{
920 static char *leader = "........................................";
921
922 if (!val)
923 return 0;
924 else
925 return snprintf(buf, maxlen, "%s %s %10d\n", name,
926 leader + strlen(name), val);
927}
928
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000929static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
930{
931 u32 i;
932 u32 usage_count = 0;
933
934 if (!priv->data.dual_emac)
935 return 0;
936
937 for (i = 0; i < priv->data.slaves; i++)
938 if (priv->slaves[i].open_stat)
939 usage_count++;
940
941 return usage_count;
942}
943
944static inline int cpsw_tx_packet_submit(struct net_device *ndev,
945 struct cpsw_priv *priv, struct sk_buff *skb)
946{
947 if (!priv->data.dual_emac)
948 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +0000949 skb->len, 0);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000950
951 if (ndev == cpsw_get_slave_ndev(priv, 0))
952 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +0000953 skb->len, 1);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000954 else
955 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +0000956 skb->len, 2);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000957}
958
959static inline void cpsw_add_dual_emac_def_ale_entries(
960 struct cpsw_priv *priv, struct cpsw_slave *slave,
961 u32 slave_port)
962{
963 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
964
965 if (priv->version == CPSW_VERSION_1)
966 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
967 else
968 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
969 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
970 port_mask, port_mask, 0);
971 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
972 port_mask, ALE_VLAN, slave->port_vlan, 0);
973 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
974 priv->host_port, ALE_VLAN, slave->port_vlan);
975}
976
Mugunthan V Ndf828592012-03-18 20:17:54 +0000977static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
978{
979 char name[32];
980 u32 slave_port;
981
982 sprintf(name, "slave-%d", slave->slave_num);
983
984 soft_reset(name, &slave->sliver->soft_reset);
985
986 /* setup priority mapping */
987 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
Richard Cochran9750a3a2012-10-29 08:45:15 +0000988
989 switch (priv->version) {
990 case CPSW_VERSION_1:
991 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
992 break;
993 case CPSW_VERSION_2:
994 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
995 break;
996 }
Mugunthan V Ndf828592012-03-18 20:17:54 +0000997
998 /* setup max packet size, and mac address */
999 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1000 cpsw_set_slave_mac(slave, priv);
1001
1002 slave->mac_control = 0; /* no link yet */
1003
1004 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1005
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001006 if (priv->data.dual_emac)
1007 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1008 else
1009 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1010 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001011
1012 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
Florian Fainellif9a8f832013-01-14 00:52:52 +00001013 &cpsw_adjust_link, slave->data->phy_if);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001014 if (IS_ERR(slave->phy)) {
1015 dev_err(priv->dev, "phy %s not found on slave %d\n",
1016 slave->data->phy_id, slave->slave_num);
1017 slave->phy = NULL;
1018 } else {
1019 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1020 slave->phy->phy_id);
1021 phy_start(slave->phy);
1022 }
1023}
1024
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001025static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1026{
1027 const int vlan = priv->data.default_vlan;
1028 const int port = priv->host_port;
1029 u32 reg;
1030 int i;
1031
1032 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1033 CPSW2_PORT_VLAN;
1034
1035 writel(vlan, &priv->host_port_regs->port_vlan);
1036
Daniel Mack0237c112013-02-26 04:06:20 +00001037 for (i = 0; i < priv->data.slaves; i++)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001038 slave_write(priv->slaves + i, vlan, reg);
1039
1040 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1041 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1042 (ALE_PORT_1 | ALE_PORT_2) << port);
1043}
1044
Mugunthan V Ndf828592012-03-18 20:17:54 +00001045static void cpsw_init_host_port(struct cpsw_priv *priv)
1046{
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001047 u32 control_reg;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001048 u32 fifo_mode;
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001049
Mugunthan V Ndf828592012-03-18 20:17:54 +00001050 /* soft reset the controller and initialize ale */
1051 soft_reset("cpsw", &priv->regs->soft_reset);
1052 cpsw_ale_start(priv->ale);
1053
1054 /* switch to vlan unaware mode */
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001055 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1056 CPSW_ALE_VLAN_AWARE);
1057 control_reg = readl(&priv->regs->control);
1058 control_reg |= CPSW_VLAN_AWARE;
1059 writel(control_reg, &priv->regs->control);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001060 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1061 CPSW_FIFO_NORMAL_MODE;
1062 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001063
1064 /* setup host port priority mapping */
1065 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1066 &priv->host_port_regs->cpdma_tx_pri_map);
1067 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1068
1069 cpsw_ale_control_set(priv->ale, priv->host_port,
1070 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1071
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001072 if (!priv->data.dual_emac) {
1073 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1074 0, 0);
1075 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1076 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1077 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001078}
1079
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001080static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1081{
1082 if (!slave->phy)
1083 return;
1084 phy_stop(slave->phy);
1085 phy_disconnect(slave->phy);
1086 slave->phy = NULL;
1087}
1088
Mugunthan V Ndf828592012-03-18 20:17:54 +00001089static int cpsw_ndo_open(struct net_device *ndev)
1090{
1091 struct cpsw_priv *priv = netdev_priv(ndev);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001092 struct cpsw_priv *prim_cpsw;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001093 int i, ret;
1094 u32 reg;
1095
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001096 if (!cpsw_common_res_usage_state(priv))
1097 cpsw_intr_disable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001098 netif_carrier_off(ndev);
1099
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001100 pm_runtime_get_sync(&priv->pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001101
Richard Cochran549985e2012-11-14 09:07:56 +00001102 reg = priv->version;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001103
1104 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1105 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1106 CPSW_RTL_VERSION(reg));
1107
1108 /* initialize host and slave ports */
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001109 if (!cpsw_common_res_usage_state(priv))
1110 cpsw_init_host_port(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001111 for_each_slave(priv, cpsw_slave_open, priv);
1112
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001113 /* Add default VLAN */
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001114 if (!priv->data.dual_emac)
1115 cpsw_add_default_vlan(priv);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001116
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001117 if (!cpsw_common_res_usage_state(priv)) {
1118 /* setup tx dma to fixed prio and zero offset */
1119 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1120 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001121
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001122 /* disable priority elevation */
1123 __raw_writel(0, &priv->regs->ptype);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001124
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001125 /* enable statistics collection only on all ports */
1126 __raw_writel(0x7, &priv->regs->stat_port_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001127
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001128 if (WARN_ON(!priv->data.rx_descs))
1129 priv->data.rx_descs = 128;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001130
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001131 for (i = 0; i < priv->data.rx_descs; i++) {
1132 struct sk_buff *skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001133
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001134 ret = -ENOMEM;
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001135 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1136 priv->rx_packet_max, GFP_KERNEL);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001137 if (!skb)
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001138 goto err_cleanup;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001139 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001140 skb_tailroom(skb), 0);
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001141 if (ret < 0) {
1142 kfree_skb(skb);
1143 goto err_cleanup;
1144 }
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001145 }
1146 /* continue even if we didn't manage to submit all
1147 * receive descs
1148 */
1149 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001150 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001151
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001152 /* Enable Interrupt pacing if configured */
1153 if (priv->coal_intvl != 0) {
1154 struct ethtool_coalesce coal;
1155
1156 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1157 cpsw_set_coalesce(ndev, &coal);
1158 }
1159
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001160 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1161 if (prim_cpsw->irq_enabled == false) {
1162 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1163 prim_cpsw->irq_enabled = true;
1164 cpsw_enable_irq(prim_cpsw);
1165 }
1166 }
1167
Mugunthan V Ndf828592012-03-18 20:17:54 +00001168 cpdma_ctlr_start(priv->dma);
1169 cpsw_intr_enable(priv);
1170 napi_enable(&priv->napi);
Mugunthan V N510a1e722013-02-17 22:19:20 +00001171 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1172 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001173
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001174 if (priv->data.dual_emac)
1175 priv->slaves[priv->emac_port].open_stat = true;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001176 return 0;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001177
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001178err_cleanup:
1179 cpdma_ctlr_stop(priv->dma);
1180 for_each_slave(priv, cpsw_slave_stop, priv);
1181 pm_runtime_put_sync(&priv->pdev->dev);
1182 netif_carrier_off(priv->ndev);
1183 return ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001184}
1185
1186static int cpsw_ndo_stop(struct net_device *ndev)
1187{
1188 struct cpsw_priv *priv = netdev_priv(ndev);
1189
1190 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
Mugunthan V Ndf828592012-03-18 20:17:54 +00001191 netif_stop_queue(priv->ndev);
1192 napi_disable(&priv->napi);
1193 netif_carrier_off(priv->ndev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001194
1195 if (cpsw_common_res_usage_state(priv) <= 1) {
1196 cpsw_intr_disable(priv);
1197 cpdma_ctlr_int_ctrl(priv->dma, false);
1198 cpdma_ctlr_stop(priv->dma);
1199 cpsw_ale_stop(priv->ale);
1200 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001201 for_each_slave(priv, cpsw_slave_stop, priv);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001202 pm_runtime_put_sync(&priv->pdev->dev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001203 if (priv->data.dual_emac)
1204 priv->slaves[priv->emac_port].open_stat = false;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001205 return 0;
1206}
1207
1208static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1209 struct net_device *ndev)
1210{
1211 struct cpsw_priv *priv = netdev_priv(ndev);
1212 int ret;
1213
1214 ndev->trans_start = jiffies;
1215
1216 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1217 cpsw_err(priv, tx_err, "packet pad failed\n");
1218 priv->stats.tx_dropped++;
1219 return NETDEV_TX_OK;
1220 }
1221
Mugunthan V N9232b162013-02-11 09:52:19 +00001222 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1223 priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001224 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1225
1226 skb_tx_timestamp(skb);
1227
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001228 ret = cpsw_tx_packet_submit(ndev, priv, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001229 if (unlikely(ret != 0)) {
1230 cpsw_err(priv, tx_err, "desc submit failed\n");
1231 goto fail;
1232 }
1233
Mugunthan V Nfae50822013-01-17 06:31:34 +00001234 /* If there is no more tx desc left free then we need to
1235 * tell the kernel to stop sending us tx frames.
1236 */
Daniel Mackd35162f2013-03-12 06:31:19 +00001237 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
Mugunthan V Nfae50822013-01-17 06:31:34 +00001238 netif_stop_queue(ndev);
1239
Mugunthan V Ndf828592012-03-18 20:17:54 +00001240 return NETDEV_TX_OK;
1241fail:
1242 priv->stats.tx_dropped++;
1243 netif_stop_queue(ndev);
1244 return NETDEV_TX_BUSY;
1245}
1246
1247static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1248{
1249 /*
1250 * The switch cannot operate in promiscuous mode without substantial
1251 * headache. For promiscuous mode to work, we would need to put the
1252 * ALE in bypass mode and route all traffic to the host port.
1253 * Subsequently, the host will need to operate as a "bridge", learn,
1254 * and flood as needed. For now, we simply complain here and
1255 * do nothing about it :-)
1256 */
1257 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1258 dev_err(&ndev->dev, "promiscuity ignored!\n");
1259
1260 /*
1261 * The switch cannot filter multicast traffic unless it is configured
1262 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1263 * whole bunch of additional logic that this driver does not implement
1264 * at present.
1265 */
1266 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1267 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1268}
1269
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001270#ifdef CONFIG_TI_CPTS
1271
1272static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1273{
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001274 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001275 u32 ts_en, seq_id;
1276
Mugunthan V N9232b162013-02-11 09:52:19 +00001277 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001278 slave_write(slave, 0, CPSW1_TS_CTL);
1279 return;
1280 }
1281
1282 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1283 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1284
Mugunthan V N9232b162013-02-11 09:52:19 +00001285 if (priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001286 ts_en |= CPSW_V1_TS_TX_EN;
1287
Mugunthan V N9232b162013-02-11 09:52:19 +00001288 if (priv->cpts->rx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001289 ts_en |= CPSW_V1_TS_RX_EN;
1290
1291 slave_write(slave, ts_en, CPSW1_TS_CTL);
1292 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1293}
1294
1295static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1296{
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001297 struct cpsw_slave *slave;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001298 u32 ctrl, mtype;
1299
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001300 if (priv->data.dual_emac)
1301 slave = &priv->slaves[priv->emac_port];
1302 else
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001303 slave = &priv->slaves[priv->data.active_slave];
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001304
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001305 ctrl = slave_read(slave, CPSW2_CONTROL);
1306 ctrl &= ~CTRL_ALL_TS_MASK;
1307
Mugunthan V N9232b162013-02-11 09:52:19 +00001308 if (priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001309 ctrl |= CTRL_TX_TS_BITS;
1310
Mugunthan V N9232b162013-02-11 09:52:19 +00001311 if (priv->cpts->rx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001312 ctrl |= CTRL_RX_TS_BITS;
1313
1314 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1315
1316 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1317 slave_write(slave, ctrl, CPSW2_CONTROL);
1318 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1319}
1320
Mugunthan V N3177bf62012-11-27 07:53:40 +00001321static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001322{
Mugunthan V N3177bf62012-11-27 07:53:40 +00001323 struct cpsw_priv *priv = netdev_priv(dev);
Mugunthan V N9232b162013-02-11 09:52:19 +00001324 struct cpts *cpts = priv->cpts;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001325 struct hwtstamp_config cfg;
1326
1327 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1328 return -EFAULT;
1329
1330 /* reserved for future extensions */
1331 if (cfg.flags)
1332 return -EINVAL;
1333
1334 switch (cfg.tx_type) {
1335 case HWTSTAMP_TX_OFF:
1336 cpts->tx_enable = 0;
1337 break;
1338 case HWTSTAMP_TX_ON:
1339 cpts->tx_enable = 1;
1340 break;
1341 default:
1342 return -ERANGE;
1343 }
1344
1345 switch (cfg.rx_filter) {
1346 case HWTSTAMP_FILTER_NONE:
1347 cpts->rx_enable = 0;
1348 break;
1349 case HWTSTAMP_FILTER_ALL:
1350 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1351 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1352 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1353 return -ERANGE;
1354 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1355 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1356 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1357 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1358 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1359 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1360 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1361 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1362 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1363 cpts->rx_enable = 1;
1364 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1365 break;
1366 default:
1367 return -ERANGE;
1368 }
1369
1370 switch (priv->version) {
1371 case CPSW_VERSION_1:
1372 cpsw_hwtstamp_v1(priv);
1373 break;
1374 case CPSW_VERSION_2:
1375 cpsw_hwtstamp_v2(priv);
1376 break;
1377 default:
1378 return -ENOTSUPP;
1379 }
1380
1381 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1382}
1383
1384#endif /*CONFIG_TI_CPTS*/
1385
1386static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1387{
Mugunthan V N11f2c982013-03-11 23:16:38 +00001388 struct cpsw_priv *priv = netdev_priv(dev);
1389 struct mii_ioctl_data *data = if_mii(req);
1390 int slave_no = cpsw_slave_index(priv);
1391
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001392 if (!netif_running(dev))
1393 return -EINVAL;
1394
Mugunthan V N11f2c982013-03-11 23:16:38 +00001395 switch (cmd) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001396#ifdef CONFIG_TI_CPTS
Mugunthan V N11f2c982013-03-11 23:16:38 +00001397 case SIOCSHWTSTAMP:
Mugunthan V N3177bf62012-11-27 07:53:40 +00001398 return cpsw_hwtstamp_ioctl(dev, req);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001399#endif
Mugunthan V N11f2c982013-03-11 23:16:38 +00001400 case SIOCGMIIPHY:
1401 data->phy_id = priv->slaves[slave_no].phy->addr;
1402 break;
1403 default:
1404 return -ENOTSUPP;
1405 }
1406
1407 return 0;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001408}
1409
Mugunthan V Ndf828592012-03-18 20:17:54 +00001410static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1411{
1412 struct cpsw_priv *priv = netdev_priv(ndev);
1413
1414 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1415 priv->stats.tx_errors++;
1416 cpsw_intr_disable(priv);
1417 cpdma_ctlr_int_ctrl(priv->dma, false);
1418 cpdma_chan_stop(priv->txch);
1419 cpdma_chan_start(priv->txch);
1420 cpdma_ctlr_int_ctrl(priv->dma, true);
1421 cpsw_intr_enable(priv);
Mugunthan V N510a1e722013-02-17 22:19:20 +00001422 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1423 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1424
Mugunthan V Ndf828592012-03-18 20:17:54 +00001425}
1426
1427static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1428{
1429 struct cpsw_priv *priv = netdev_priv(ndev);
1430 return &priv->stats;
1431}
1432
1433#ifdef CONFIG_NET_POLL_CONTROLLER
1434static void cpsw_ndo_poll_controller(struct net_device *ndev)
1435{
1436 struct cpsw_priv *priv = netdev_priv(ndev);
1437
1438 cpsw_intr_disable(priv);
1439 cpdma_ctlr_int_ctrl(priv->dma, false);
1440 cpsw_interrupt(ndev->irq, priv);
1441 cpdma_ctlr_int_ctrl(priv->dma, true);
1442 cpsw_intr_enable(priv);
Mugunthan V N510a1e722013-02-17 22:19:20 +00001443 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1444 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1445
Mugunthan V Ndf828592012-03-18 20:17:54 +00001446}
1447#endif
1448
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001449static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1450 unsigned short vid)
1451{
1452 int ret;
1453
1454 ret = cpsw_ale_add_vlan(priv->ale, vid,
1455 ALE_ALL_PORTS << priv->host_port,
1456 0, ALE_ALL_PORTS << priv->host_port,
1457 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1458 if (ret != 0)
1459 return ret;
1460
1461 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1462 priv->host_port, ALE_VLAN, vid);
1463 if (ret != 0)
1464 goto clean_vid;
1465
1466 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1467 ALE_ALL_PORTS << priv->host_port,
1468 ALE_VLAN, vid, 0);
1469 if (ret != 0)
1470 goto clean_vlan_ucast;
1471 return 0;
1472
1473clean_vlan_ucast:
1474 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1475 priv->host_port, ALE_VLAN, vid);
1476clean_vid:
1477 cpsw_ale_del_vlan(priv->ale, vid, 0);
1478 return ret;
1479}
1480
1481static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001482 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001483{
1484 struct cpsw_priv *priv = netdev_priv(ndev);
1485
1486 if (vid == priv->data.default_vlan)
1487 return 0;
1488
1489 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1490 return cpsw_add_vlan_ale_entry(priv, vid);
1491}
1492
1493static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001494 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001495{
1496 struct cpsw_priv *priv = netdev_priv(ndev);
1497 int ret;
1498
1499 if (vid == priv->data.default_vlan)
1500 return 0;
1501
1502 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1503 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1504 if (ret != 0)
1505 return ret;
1506
1507 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1508 priv->host_port, ALE_VLAN, vid);
1509 if (ret != 0)
1510 return ret;
1511
1512 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1513 0, ALE_VLAN, vid);
1514}
1515
Mugunthan V Ndf828592012-03-18 20:17:54 +00001516static const struct net_device_ops cpsw_netdev_ops = {
1517 .ndo_open = cpsw_ndo_open,
1518 .ndo_stop = cpsw_ndo_stop,
1519 .ndo_start_xmit = cpsw_ndo_start_xmit,
1520 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001521 .ndo_do_ioctl = cpsw_ndo_ioctl,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001522 .ndo_validate_addr = eth_validate_addr,
David S. Miller5c473ed2012-03-20 00:33:59 -04001523 .ndo_change_mtu = eth_change_mtu,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001524 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1525 .ndo_get_stats = cpsw_ndo_get_stats,
Mugunthan V N5c50a852012-10-29 08:45:11 +00001526 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001527#ifdef CONFIG_NET_POLL_CONTROLLER
1528 .ndo_poll_controller = cpsw_ndo_poll_controller,
1529#endif
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001530 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1531 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001532};
1533
1534static void cpsw_get_drvinfo(struct net_device *ndev,
1535 struct ethtool_drvinfo *info)
1536{
1537 struct cpsw_priv *priv = netdev_priv(ndev);
Jiri Pirko7826d432013-01-06 00:44:26 +00001538
1539 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1540 strlcpy(info->version, "1.0", sizeof(info->version));
1541 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
Mugunthan V Ndf828592012-03-18 20:17:54 +00001542}
1543
1544static u32 cpsw_get_msglevel(struct net_device *ndev)
1545{
1546 struct cpsw_priv *priv = netdev_priv(ndev);
1547 return priv->msg_enable;
1548}
1549
1550static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1551{
1552 struct cpsw_priv *priv = netdev_priv(ndev);
1553 priv->msg_enable = value;
1554}
1555
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001556static int cpsw_get_ts_info(struct net_device *ndev,
1557 struct ethtool_ts_info *info)
1558{
1559#ifdef CONFIG_TI_CPTS
1560 struct cpsw_priv *priv = netdev_priv(ndev);
1561
1562 info->so_timestamping =
1563 SOF_TIMESTAMPING_TX_HARDWARE |
1564 SOF_TIMESTAMPING_TX_SOFTWARE |
1565 SOF_TIMESTAMPING_RX_HARDWARE |
1566 SOF_TIMESTAMPING_RX_SOFTWARE |
1567 SOF_TIMESTAMPING_SOFTWARE |
1568 SOF_TIMESTAMPING_RAW_HARDWARE;
Mugunthan V N9232b162013-02-11 09:52:19 +00001569 info->phc_index = priv->cpts->phc_index;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001570 info->tx_types =
1571 (1 << HWTSTAMP_TX_OFF) |
1572 (1 << HWTSTAMP_TX_ON);
1573 info->rx_filters =
1574 (1 << HWTSTAMP_FILTER_NONE) |
1575 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1576#else
1577 info->so_timestamping =
1578 SOF_TIMESTAMPING_TX_SOFTWARE |
1579 SOF_TIMESTAMPING_RX_SOFTWARE |
1580 SOF_TIMESTAMPING_SOFTWARE;
1581 info->phc_index = -1;
1582 info->tx_types = 0;
1583 info->rx_filters = 0;
1584#endif
1585 return 0;
1586}
1587
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001588static int cpsw_get_settings(struct net_device *ndev,
1589 struct ethtool_cmd *ecmd)
1590{
1591 struct cpsw_priv *priv = netdev_priv(ndev);
1592 int slave_no = cpsw_slave_index(priv);
1593
1594 if (priv->slaves[slave_no].phy)
1595 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1596 else
1597 return -EOPNOTSUPP;
1598}
1599
1600static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1601{
1602 struct cpsw_priv *priv = netdev_priv(ndev);
1603 int slave_no = cpsw_slave_index(priv);
1604
1605 if (priv->slaves[slave_no].phy)
1606 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1607 else
1608 return -EOPNOTSUPP;
1609}
1610
Mugunthan V Ndf828592012-03-18 20:17:54 +00001611static const struct ethtool_ops cpsw_ethtool_ops = {
1612 .get_drvinfo = cpsw_get_drvinfo,
1613 .get_msglevel = cpsw_get_msglevel,
1614 .set_msglevel = cpsw_set_msglevel,
1615 .get_link = ethtool_op_get_link,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001616 .get_ts_info = cpsw_get_ts_info,
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001617 .get_settings = cpsw_get_settings,
1618 .set_settings = cpsw_set_settings,
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001619 .get_coalesce = cpsw_get_coalesce,
1620 .set_coalesce = cpsw_set_coalesce,
Mugunthan V Nd9718542013-07-23 15:38:17 +05301621 .get_sset_count = cpsw_get_sset_count,
1622 .get_strings = cpsw_get_strings,
1623 .get_ethtool_stats = cpsw_get_ethtool_stats,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001624};
1625
Richard Cochran549985e2012-11-14 09:07:56 +00001626static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1627 u32 slave_reg_ofs, u32 sliver_reg_ofs)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001628{
1629 void __iomem *regs = priv->regs;
1630 int slave_num = slave->slave_num;
1631 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1632
1633 slave->data = data;
Richard Cochran549985e2012-11-14 09:07:56 +00001634 slave->regs = regs + slave_reg_ofs;
1635 slave->sliver = regs + sliver_reg_ofs;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001636 slave->port_vlan = data->dual_emac_res_vlan;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001637}
1638
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001639static int cpsw_probe_dt(struct cpsw_platform_data *data,
1640 struct platform_device *pdev)
1641{
1642 struct device_node *node = pdev->dev.of_node;
1643 struct device_node *slave_node;
1644 int i = 0, ret;
1645 u32 prop;
1646
1647 if (!node)
1648 return -EINVAL;
1649
1650 if (of_property_read_u32(node, "slaves", &prop)) {
1651 pr_err("Missing slaves property in the DT.\n");
1652 return -EINVAL;
1653 }
1654 data->slaves = prop;
1655
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001656 if (of_property_read_u32(node, "active_slave", &prop)) {
1657 pr_err("Missing active_slave property in the DT.\n");
Richard Cochran78ca0b22012-10-29 08:45:18 +00001658 ret = -EINVAL;
1659 goto error_ret;
1660 }
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001661 data->active_slave = prop;
Richard Cochran78ca0b22012-10-29 08:45:18 +00001662
Richard Cochran00ab94e2012-10-29 08:45:19 +00001663 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1664 pr_err("Missing cpts_clock_mult property in the DT.\n");
1665 ret = -EINVAL;
1666 goto error_ret;
1667 }
1668 data->cpts_clock_mult = prop;
1669
1670 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1671 pr_err("Missing cpts_clock_shift property in the DT.\n");
1672 ret = -EINVAL;
1673 goto error_ret;
1674 }
1675 data->cpts_clock_shift = prop;
1676
Joe Perchesb2adaca2013-02-03 17:43:58 +00001677 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1678 GFP_KERNEL);
1679 if (!data->slave_data)
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001680 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001681
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001682 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1683 pr_err("Missing cpdma_channels property in the DT.\n");
1684 ret = -EINVAL;
1685 goto error_ret;
1686 }
1687 data->channels = prop;
1688
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001689 if (of_property_read_u32(node, "ale_entries", &prop)) {
1690 pr_err("Missing ale_entries property in the DT.\n");
1691 ret = -EINVAL;
1692 goto error_ret;
1693 }
1694 data->ale_entries = prop;
1695
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001696 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1697 pr_err("Missing bd_ram_size property in the DT.\n");
1698 ret = -EINVAL;
1699 goto error_ret;
1700 }
1701 data->bd_ram_size = prop;
1702
1703 if (of_property_read_u32(node, "rx_descs", &prop)) {
1704 pr_err("Missing rx_descs property in the DT.\n");
1705 ret = -EINVAL;
1706 goto error_ret;
1707 }
1708 data->rx_descs = prop;
1709
1710 if (of_property_read_u32(node, "mac_control", &prop)) {
1711 pr_err("Missing mac_control property in the DT.\n");
1712 ret = -EINVAL;
1713 goto error_ret;
1714 }
1715 data->mac_control = prop;
1716
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001717 if (!of_property_read_u32(node, "dual_emac", &prop))
1718 data->dual_emac = prop;
1719
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00001720 /*
1721 * Populate all the child nodes here...
1722 */
1723 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1724 /* We do not want to force this, as in some cases may not have child */
1725 if (ret)
1726 pr_warn("Doesn't have any child node\n");
1727
Richard Cochran549985e2012-11-14 09:07:56 +00001728 for_each_node_by_name(slave_node, "slave") {
1729 struct cpsw_slave_data *slave_data = data->slave_data + i;
1730 const void *mac_addr = NULL;
1731 u32 phyid;
1732 int lenp;
1733 const __be32 *parp;
1734 struct device_node *mdio_node;
1735 struct platform_device *mdio;
1736
1737 parp = of_get_property(slave_node, "phy_id", &lenp);
Lothar Waßmannce162942013-03-21 02:20:11 +00001738 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
Richard Cochran549985e2012-11-14 09:07:56 +00001739 pr_err("Missing slave[%d] phy_id property\n", i);
1740 ret = -EINVAL;
1741 goto error_ret;
1742 }
1743 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1744 phyid = be32_to_cpup(parp+1);
1745 mdio = of_find_device_by_node(mdio_node);
1746 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1747 PHY_ID_FMT, mdio->name, phyid);
1748
1749 mac_addr = of_get_mac_address(slave_node);
1750 if (mac_addr)
1751 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1752
Mugunthan V Nc5ceea72013-06-03 20:10:10 +00001753 slave_data->phy_if = of_get_phy_mode(slave_node);
1754
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001755 if (data->dual_emac) {
Mugunthan V N91c41662013-04-15 07:31:28 +00001756 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001757 &prop)) {
1758 pr_err("Missing dual_emac_res_vlan in DT.\n");
1759 slave_data->dual_emac_res_vlan = i+1;
1760 pr_err("Using %d as Reserved VLAN for %d slave\n",
1761 slave_data->dual_emac_res_vlan, i);
1762 } else {
1763 slave_data->dual_emac_res_vlan = prop;
1764 }
1765 }
1766
Richard Cochran549985e2012-11-14 09:07:56 +00001767 i++;
1768 }
1769
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001770 return 0;
1771
1772error_ret:
1773 kfree(data->slave_data);
1774 return ret;
1775}
1776
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001777static int cpsw_probe_dual_emac(struct platform_device *pdev,
1778 struct cpsw_priv *priv)
1779{
1780 struct cpsw_platform_data *data = &priv->data;
1781 struct net_device *ndev;
1782 struct cpsw_priv *priv_sl2;
1783 int ret = 0, i;
1784
1785 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1786 if (!ndev) {
1787 pr_err("cpsw: error allocating net_device\n");
1788 return -ENOMEM;
1789 }
1790
1791 priv_sl2 = netdev_priv(ndev);
1792 spin_lock_init(&priv_sl2->lock);
1793 priv_sl2->data = *data;
1794 priv_sl2->pdev = pdev;
1795 priv_sl2->ndev = ndev;
1796 priv_sl2->dev = &ndev->dev;
1797 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1798 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1799
1800 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1801 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1802 ETH_ALEN);
1803 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1804 } else {
1805 random_ether_addr(priv_sl2->mac_addr);
1806 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1807 }
1808 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1809
1810 priv_sl2->slaves = priv->slaves;
1811 priv_sl2->clk = priv->clk;
1812
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001813 priv_sl2->coal_intvl = 0;
1814 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1815
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001816 priv_sl2->cpsw_res = priv->cpsw_res;
1817 priv_sl2->regs = priv->regs;
1818 priv_sl2->host_port = priv->host_port;
1819 priv_sl2->host_port_regs = priv->host_port_regs;
1820 priv_sl2->wr_regs = priv->wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +05301821 priv_sl2->hw_stats = priv->hw_stats;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001822 priv_sl2->dma = priv->dma;
1823 priv_sl2->txch = priv->txch;
1824 priv_sl2->rxch = priv->rxch;
1825 priv_sl2->ale = priv->ale;
1826 priv_sl2->emac_port = 1;
1827 priv->slaves[1].ndev = ndev;
1828 priv_sl2->cpts = priv->cpts;
1829 priv_sl2->version = priv->version;
1830
1831 for (i = 0; i < priv->num_irqs; i++) {
1832 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1833 priv_sl2->num_irqs = priv->num_irqs;
1834 }
Patrick McHardyf6469682013-04-19 02:04:27 +00001835 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001836
1837 ndev->netdev_ops = &cpsw_netdev_ops;
1838 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1839 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1840
1841 /* register the network device */
1842 SET_NETDEV_DEV(ndev, &pdev->dev);
1843 ret = register_netdev(ndev);
1844 if (ret) {
1845 pr_err("cpsw: error registering net device\n");
1846 free_netdev(ndev);
1847 ret = -ENODEV;
1848 }
1849
1850 return ret;
1851}
1852
Bill Pemberton663e12e2012-12-03 09:23:45 -05001853static int cpsw_probe(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001854{
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00001855 struct cpsw_platform_data *data;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001856 struct net_device *ndev;
1857 struct cpsw_priv *priv;
1858 struct cpdma_params dma_params;
1859 struct cpsw_ale_params ale_params;
Richard Cochran549985e2012-11-14 09:07:56 +00001860 void __iomem *ss_regs, *wr_regs;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001861 struct resource *res;
Richard Cochran549985e2012-11-14 09:07:56 +00001862 u32 slave_offset, sliver_offset, slave_size;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001863 int ret = 0, i, k = 0;
1864
Mugunthan V Ndf828592012-03-18 20:17:54 +00001865 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1866 if (!ndev) {
1867 pr_err("error allocating net_device\n");
1868 return -ENOMEM;
1869 }
1870
1871 platform_set_drvdata(pdev, ndev);
1872 priv = netdev_priv(ndev);
1873 spin_lock_init(&priv->lock);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001874 priv->pdev = pdev;
1875 priv->ndev = ndev;
1876 priv->dev = &ndev->dev;
1877 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1878 priv->rx_packet_max = max(rx_packet_max, 128);
Mugunthan V N9232b162013-02-11 09:52:19 +00001879 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
Mugunthan V N7dcf3132013-04-29 23:27:28 +00001880 priv->irq_enabled = true;
Sebastian Siewiorab8e99d2013-06-17 19:31:52 +02001881 if (!priv->cpts) {
Mugunthan V N9232b162013-02-11 09:52:19 +00001882 pr_err("error allocating cpts\n");
1883 goto clean_ndev_ret;
1884 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001885
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00001886 /*
1887 * This may be required here for child devices.
1888 */
1889 pm_runtime_enable(&pdev->dev);
1890
Mugunthan V N739683b2013-06-06 23:45:14 +05301891 /* Select default pin state */
1892 pinctrl_pm_select_default_state(&pdev->dev);
1893
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001894 if (cpsw_probe_dt(&priv->data, pdev)) {
1895 pr_err("cpsw: platform data missing\n");
1896 ret = -ENODEV;
1897 goto clean_ndev_ret;
1898 }
1899 data = &priv->data;
1900
Mugunthan V Ndf828592012-03-18 20:17:54 +00001901 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1902 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
Daniel Mackcf6122b2013-06-27 11:40:47 +02001903 pr_info("Detected MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001904 } else {
Joe Perches7efd26d2012-07-12 19:33:06 +00001905 eth_random_addr(priv->mac_addr);
Daniel Mackcf6122b2013-06-27 11:40:47 +02001906 pr_info("Random MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001907 }
1908
1909 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1910
1911 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1912 GFP_KERNEL);
1913 if (!priv->slaves) {
1914 ret = -EBUSY;
1915 goto clean_ndev_ret;
1916 }
1917 for (i = 0; i < data->slaves; i++)
1918 priv->slaves[i].slave_num = i;
1919
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001920 priv->slaves[0].ndev = ndev;
1921 priv->emac_port = 0;
1922
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001923 priv->clk = clk_get(&pdev->dev, "fck");
Mugunthan V Ndf828592012-03-18 20:17:54 +00001924 if (IS_ERR(priv->clk)) {
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001925 dev_err(&pdev->dev, "fck is not found\n");
1926 ret = -ENODEV;
1927 goto clean_slave_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001928 }
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001929 priv->coal_intvl = 0;
1930 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001931
1932 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1933 if (!priv->cpsw_res) {
1934 dev_err(priv->dev, "error getting i/o resource\n");
1935 ret = -ENOENT;
1936 goto clean_clk_ret;
1937 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001938 if (!request_mem_region(priv->cpsw_res->start,
1939 resource_size(priv->cpsw_res), ndev->name)) {
1940 dev_err(priv->dev, "failed request i/o region\n");
1941 ret = -ENXIO;
1942 goto clean_clk_ret;
1943 }
Richard Cochran549985e2012-11-14 09:07:56 +00001944 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1945 if (!ss_regs) {
Mugunthan V Ndf828592012-03-18 20:17:54 +00001946 dev_err(priv->dev, "unable to map i/o region\n");
1947 goto clean_cpsw_iores_ret;
1948 }
Richard Cochran549985e2012-11-14 09:07:56 +00001949 priv->regs = ss_regs;
1950 priv->version = __raw_readl(&priv->regs->id_ver);
1951 priv->host_port = HOST_PORT_NUM;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001952
Richard Cochrana65dd5b2012-11-02 22:25:29 +00001953 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1954 if (!priv->cpsw_wr_res) {
Mugunthan V Ndf828592012-03-18 20:17:54 +00001955 dev_err(priv->dev, "error getting i/o resource\n");
1956 ret = -ENOENT;
Richard Cochran5250c962012-11-02 22:25:30 +00001957 goto clean_iomap_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001958 }
Richard Cochrana65dd5b2012-11-02 22:25:29 +00001959 if (!request_mem_region(priv->cpsw_wr_res->start,
1960 resource_size(priv->cpsw_wr_res), ndev->name)) {
Mugunthan V Ndf828592012-03-18 20:17:54 +00001961 dev_err(priv->dev, "failed request i/o region\n");
1962 ret = -ENXIO;
Richard Cochran5250c962012-11-02 22:25:30 +00001963 goto clean_iomap_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001964 }
Richard Cochran549985e2012-11-14 09:07:56 +00001965 wr_regs = ioremap(priv->cpsw_wr_res->start,
Richard Cochrana65dd5b2012-11-02 22:25:29 +00001966 resource_size(priv->cpsw_wr_res));
Richard Cochran549985e2012-11-14 09:07:56 +00001967 if (!wr_regs) {
Mugunthan V Ndf828592012-03-18 20:17:54 +00001968 dev_err(priv->dev, "unable to map i/o region\n");
Richard Cochrana65dd5b2012-11-02 22:25:29 +00001969 goto clean_cpsw_wr_iores_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001970 }
Richard Cochran549985e2012-11-14 09:07:56 +00001971 priv->wr_regs = wr_regs;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001972
1973 memset(&dma_params, 0, sizeof(dma_params));
Richard Cochran549985e2012-11-14 09:07:56 +00001974 memset(&ale_params, 0, sizeof(ale_params));
1975
1976 switch (priv->version) {
1977 case CPSW_VERSION_1:
1978 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05301979 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
1980 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00001981 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
1982 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
1983 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
1984 slave_offset = CPSW1_SLAVE_OFFSET;
1985 slave_size = CPSW1_SLAVE_SIZE;
1986 sliver_offset = CPSW1_SLIVER_OFFSET;
1987 dma_params.desc_mem_phys = 0;
1988 break;
1989 case CPSW_VERSION_2:
1990 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05301991 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
1992 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00001993 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
1994 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
1995 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
1996 slave_offset = CPSW2_SLAVE_OFFSET;
1997 slave_size = CPSW2_SLAVE_SIZE;
1998 sliver_offset = CPSW2_SLIVER_OFFSET;
1999 dma_params.desc_mem_phys =
2000 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
2001 break;
2002 default:
2003 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2004 ret = -ENODEV;
2005 goto clean_cpsw_wr_iores_ret;
2006 }
2007 for (i = 0; i < priv->data.slaves; i++) {
2008 struct cpsw_slave *slave = &priv->slaves[i];
2009 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2010 slave_offset += slave_size;
2011 sliver_offset += SLIVER_SIZE;
2012 }
2013
Mugunthan V Ndf828592012-03-18 20:17:54 +00002014 dma_params.dev = &pdev->dev;
Richard Cochran549985e2012-11-14 09:07:56 +00002015 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2016 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2017 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2018 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2019 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002020
2021 dma_params.num_chan = data->channels;
2022 dma_params.has_soft_reset = true;
2023 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2024 dma_params.desc_mem_size = data->bd_ram_size;
2025 dma_params.desc_align = 16;
2026 dma_params.has_ext_regs = true;
Richard Cochran549985e2012-11-14 09:07:56 +00002027 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002028
2029 priv->dma = cpdma_ctlr_create(&dma_params);
2030 if (!priv->dma) {
2031 dev_err(priv->dev, "error initializing dma\n");
2032 ret = -ENOMEM;
Richard Cochran5250c962012-11-02 22:25:30 +00002033 goto clean_wr_iomap_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002034 }
2035
2036 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2037 cpsw_tx_handler);
2038 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2039 cpsw_rx_handler);
2040
2041 if (WARN_ON(!priv->txch || !priv->rxch)) {
2042 dev_err(priv->dev, "error initializing dma channels\n");
2043 ret = -ENOMEM;
2044 goto clean_dma_ret;
2045 }
2046
Mugunthan V Ndf828592012-03-18 20:17:54 +00002047 ale_params.dev = &ndev->dev;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002048 ale_params.ale_ageout = ale_ageout;
2049 ale_params.ale_entries = data->ale_entries;
2050 ale_params.ale_ports = data->slaves;
2051
2052 priv->ale = cpsw_ale_create(&ale_params);
2053 if (!priv->ale) {
2054 dev_err(priv->dev, "error initializing ale engine\n");
2055 ret = -ENODEV;
2056 goto clean_dma_ret;
2057 }
2058
2059 ndev->irq = platform_get_irq(pdev, 0);
2060 if (ndev->irq < 0) {
2061 dev_err(priv->dev, "error getting irq resource\n");
2062 ret = -ENOENT;
2063 goto clean_ale_ret;
2064 }
2065
2066 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2067 for (i = res->start; i <= res->end; i++) {
2068 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
2069 dev_name(&pdev->dev), priv)) {
2070 dev_err(priv->dev, "error attaching irq\n");
2071 goto clean_ale_ret;
2072 }
2073 priv->irqs_table[k] = i;
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002074 priv->num_irqs = k + 1;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002075 }
2076 k++;
2077 }
2078
Patrick McHardyf6469682013-04-19 02:04:27 +00002079 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002080
2081 ndev->netdev_ops = &cpsw_netdev_ops;
2082 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
2083 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2084
2085 /* register the network device */
2086 SET_NETDEV_DEV(ndev, &pdev->dev);
2087 ret = register_netdev(ndev);
2088 if (ret) {
2089 dev_err(priv->dev, "error registering net device\n");
2090 ret = -ENODEV;
2091 goto clean_irq_ret;
2092 }
2093
Mugunthan V N9232b162013-02-11 09:52:19 +00002094 if (cpts_register(&pdev->dev, priv->cpts,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00002095 data->cpts_clock_mult, data->cpts_clock_shift))
2096 dev_err(priv->dev, "error registering cpts device\n");
2097
Mugunthan V Ndf828592012-03-18 20:17:54 +00002098 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
2099 priv->cpsw_res->start, ndev->irq);
2100
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002101 if (priv->data.dual_emac) {
2102 ret = cpsw_probe_dual_emac(pdev, priv);
2103 if (ret) {
2104 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2105 goto clean_irq_ret;
2106 }
2107 }
2108
Mugunthan V Ndf828592012-03-18 20:17:54 +00002109 return 0;
2110
2111clean_irq_ret:
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002112 for (i = 0; i < priv->num_irqs; i++)
2113 free_irq(priv->irqs_table[i], priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002114clean_ale_ret:
2115 cpsw_ale_destroy(priv->ale);
2116clean_dma_ret:
2117 cpdma_chan_destroy(priv->txch);
2118 cpdma_chan_destroy(priv->rxch);
2119 cpdma_ctlr_destroy(priv->dma);
Richard Cochran5250c962012-11-02 22:25:30 +00002120clean_wr_iomap_ret:
2121 iounmap(priv->wr_regs);
Richard Cochrana65dd5b2012-11-02 22:25:29 +00002122clean_cpsw_wr_iores_ret:
2123 release_mem_region(priv->cpsw_wr_res->start,
2124 resource_size(priv->cpsw_wr_res));
Richard Cochran5250c962012-11-02 22:25:30 +00002125clean_iomap_ret:
2126 iounmap(priv->regs);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002127clean_cpsw_iores_ret:
2128 release_mem_region(priv->cpsw_res->start,
2129 resource_size(priv->cpsw_res));
2130clean_clk_ret:
2131 clk_put(priv->clk);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002132clean_slave_ret:
2133 pm_runtime_disable(&pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002134 kfree(priv->slaves);
2135clean_ndev_ret:
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002136 kfree(priv->data.slave_data);
2137 free_netdev(priv->ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002138 return ret;
2139}
2140
Bill Pemberton663e12e2012-12-03 09:23:45 -05002141static int cpsw_remove(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00002142{
2143 struct net_device *ndev = platform_get_drvdata(pdev);
2144 struct cpsw_priv *priv = netdev_priv(ndev);
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002145 int i;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002146
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002147 if (priv->data.dual_emac)
2148 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2149 unregister_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002150
Mugunthan V N9232b162013-02-11 09:52:19 +00002151 cpts_unregister(priv->cpts);
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002152 for (i = 0; i < priv->num_irqs; i++)
2153 free_irq(priv->irqs_table[i], priv);
2154
Mugunthan V Ndf828592012-03-18 20:17:54 +00002155 cpsw_ale_destroy(priv->ale);
2156 cpdma_chan_destroy(priv->txch);
2157 cpdma_chan_destroy(priv->rxch);
2158 cpdma_ctlr_destroy(priv->dma);
2159 iounmap(priv->regs);
2160 release_mem_region(priv->cpsw_res->start,
2161 resource_size(priv->cpsw_res));
Richard Cochran5250c962012-11-02 22:25:30 +00002162 iounmap(priv->wr_regs);
Richard Cochrana65dd5b2012-11-02 22:25:29 +00002163 release_mem_region(priv->cpsw_wr_res->start,
2164 resource_size(priv->cpsw_wr_res));
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002165 pm_runtime_disable(&pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002166 clk_put(priv->clk);
2167 kfree(priv->slaves);
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002168 kfree(priv->data.slave_data);
2169 if (priv->data.dual_emac)
2170 free_netdev(cpsw_get_slave_ndev(priv, 1));
Mugunthan V Ndf828592012-03-18 20:17:54 +00002171 free_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002172 return 0;
2173}
2174
2175static int cpsw_suspend(struct device *dev)
2176{
2177 struct platform_device *pdev = to_platform_device(dev);
2178 struct net_device *ndev = platform_get_drvdata(pdev);
Mugunthan V Nb90fc272013-06-21 19:15:09 +05302179 struct cpsw_priv *priv = netdev_priv(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002180
2181 if (netif_running(ndev))
2182 cpsw_ndo_stop(ndev);
Mugunthan V N6d3d76f2013-06-18 15:04:35 +05302183 soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
2184 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002185 pm_runtime_put_sync(&pdev->dev);
2186
Mugunthan V N739683b2013-06-06 23:45:14 +05302187 /* Select sleep pin state */
2188 pinctrl_pm_select_sleep_state(&pdev->dev);
2189
Mugunthan V Ndf828592012-03-18 20:17:54 +00002190 return 0;
2191}
2192
2193static int cpsw_resume(struct device *dev)
2194{
2195 struct platform_device *pdev = to_platform_device(dev);
2196 struct net_device *ndev = platform_get_drvdata(pdev);
2197
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002198 pm_runtime_get_sync(&pdev->dev);
Mugunthan V N739683b2013-06-06 23:45:14 +05302199
2200 /* Select default pin state */
2201 pinctrl_pm_select_default_state(&pdev->dev);
2202
Mugunthan V Ndf828592012-03-18 20:17:54 +00002203 if (netif_running(ndev))
2204 cpsw_ndo_open(ndev);
2205 return 0;
2206}
2207
2208static const struct dev_pm_ops cpsw_pm_ops = {
2209 .suspend = cpsw_suspend,
2210 .resume = cpsw_resume,
2211};
2212
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002213static const struct of_device_id cpsw_of_mtable[] = {
2214 { .compatible = "ti,cpsw", },
2215 { /* sentinel */ },
2216};
Sebastian Siewior4bc21d42013-04-24 08:48:22 +00002217MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002218
Mugunthan V Ndf828592012-03-18 20:17:54 +00002219static struct platform_driver cpsw_driver = {
2220 .driver = {
2221 .name = "cpsw",
2222 .owner = THIS_MODULE,
2223 .pm = &cpsw_pm_ops,
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002224 .of_match_table = of_match_ptr(cpsw_of_mtable),
Mugunthan V Ndf828592012-03-18 20:17:54 +00002225 },
2226 .probe = cpsw_probe,
Bill Pemberton663e12e2012-12-03 09:23:45 -05002227 .remove = cpsw_remove,
Mugunthan V Ndf828592012-03-18 20:17:54 +00002228};
2229
2230static int __init cpsw_init(void)
2231{
2232 return platform_driver_register(&cpsw_driver);
2233}
2234late_initcall(cpsw_init);
2235
2236static void __exit cpsw_exit(void)
2237{
2238 platform_driver_unregister(&cpsw_driver);
2239}
2240module_exit(cpsw_exit);
2241
2242MODULE_LICENSE("GPL");
2243MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2244MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2245MODULE_DESCRIPTION("TI CPSW Ethernet driver");