| Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 1 | /* |
| Russell King | 4baa992 | 2008-08-02 10:55:55 +0100 | [diff] [blame] | 2 | * arch/arm/include/asm/hardware/cache-l2x0.h |
| Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 ARM Limited |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __ASM_ARM_HARDWARE_L2X0_H |
| 21 | #define __ASM_ARM_HARDWARE_L2X0_H |
| 22 | |
| 23 | #define L2X0_CACHE_ID 0x000 |
| 24 | #define L2X0_CACHE_TYPE 0x004 |
| 25 | #define L2X0_CTRL 0x100 |
| 26 | #define L2X0_AUX_CTRL 0x104 |
| Colin Tuckley | 1b504bb | 2009-05-30 13:56:12 +0100 | [diff] [blame] | 27 | #define L2X0_TAG_LATENCY_CTRL 0x108 |
| 28 | #define L2X0_DATA_LATENCY_CTRL 0x10C |
| Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 29 | #define L2X0_EVENT_CNT_CTRL 0x200 |
| 30 | #define L2X0_EVENT_CNT1_CFG 0x204 |
| 31 | #define L2X0_EVENT_CNT0_CFG 0x208 |
| 32 | #define L2X0_EVENT_CNT1_VAL 0x20C |
| 33 | #define L2X0_EVENT_CNT0_VAL 0x210 |
| 34 | #define L2X0_INTR_MASK 0x214 |
| 35 | #define L2X0_MASKED_INTR_STAT 0x218 |
| 36 | #define L2X0_RAW_INTR_STAT 0x21C |
| 37 | #define L2X0_INTR_CLEAR 0x220 |
| 38 | #define L2X0_CACHE_SYNC 0x730 |
| 39 | #define L2X0_INV_LINE_PA 0x770 |
| 40 | #define L2X0_INV_WAY 0x77C |
| 41 | #define L2X0_CLEAN_LINE_PA 0x7B0 |
| 42 | #define L2X0_CLEAN_LINE_IDX 0x7B8 |
| 43 | #define L2X0_CLEAN_WAY 0x7BC |
| 44 | #define L2X0_CLEAN_INV_LINE_PA 0x7F0 |
| 45 | #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 |
| 46 | #define L2X0_CLEAN_INV_WAY 0x7FC |
| 47 | #define L2X0_LOCKDOWN_WAY_D 0x900 |
| 48 | #define L2X0_LOCKDOWN_WAY_I 0x904 |
| 49 | #define L2X0_TEST_OPERATION 0xF00 |
| 50 | #define L2X0_LINE_DATA 0xF10 |
| 51 | #define L2X0_LINE_TAG 0xF30 |
| 52 | #define L2X0_DEBUG_CTRL 0xF40 |
| 53 | |
| 54 | #ifndef __ASSEMBLY__ |
| 55 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); |
| 56 | #endif |
| 57 | |
| 58 | #endif |