blob: b015129e4045847a3e62b72fb001a71e8b80c55c [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guoff4ab232014-05-20 15:34:06 +080013#include <linux/io.h>
Shawn Guo9daaf312011-10-17 08:42:17 +080014#include <linux/irq.h>
Shawn Guo9daaf312011-10-17 08:42:17 +080015#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
Shawn Guo9daaf312011-10-17 08:42:17 +080019
Shawn Guoe3372472012-09-13 21:01:00 +080020#include "common.h"
Shawn Guoff4ab232014-05-20 15:34:06 +080021#include "hardware.h"
Shawn Guoe3372472012-09-13 21:01:00 +080022
Shawn Guoff4ab232014-05-20 15:34:06 +080023static void __init imx51_init_early(void)
24{
25 mxc_set_cpu_type(MXC_CPU_MX51);
26}
27
28/*
29 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
30 * the Freescale marketing division. However this did not remove the
31 * hardware from the chip which still needs to be configured for proper
32 * IPU support.
33 */
34#define MX51_MIPI_HSC_BASE 0x83fdc000
35static void __init imx51_ipu_mipi_setup(void)
36{
37 void __iomem *hsc_addr;
38
39 hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
40 WARN_ON(!hsc_addr);
41
42 /* setup MIPI module to legacy mode */
43 __raw_writel(0xf00, hsc_addr);
44
45 /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
46 __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
47 hsc_addr + 0x800);
48
49 iounmap(hsc_addr);
50}
51
Shawn Guo9daaf312011-10-17 08:42:17 +080052static void __init imx51_dt_init(void)
53{
Viresh Kumarbbcf0712014-09-09 19:58:03 +053054 struct platform_device_info devinfo = { .name = "cpufreq-dt", };
Markus Pargmann371b3f12013-03-27 14:01:33 +010055
Shawn Guoff4ab232014-05-20 15:34:06 +080056 imx51_ipu_mipi_setup();
57 imx_src_init();
Shawn Guo18cb6802013-05-10 09:13:44 +080058
Fabio Estevamf40f38d2012-11-21 13:43:05 -020059 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
Markus Pargmann371b3f12013-03-27 14:01:33 +010060 platform_device_register_full(&devinfo);
Shawn Guo9daaf312011-10-17 08:42:17 +080061}
62
Shawn Guoff4ab232014-05-20 15:34:06 +080063static void __init imx51_init_late(void)
64{
65 mx51_neon_fixup();
66 imx51_pm_init();
67}
68
Shawn Guo8756dd92014-07-01 16:03:00 +080069static const char * const imx51_dt_board_compat[] __initconst = {
Sascha Hauer3f8976d2012-02-17 12:07:00 +010070 "fsl,imx51",
Shawn Guo9daaf312011-10-17 08:42:17 +080071 NULL
72};
73
74DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
Shawn Guo9daaf312011-10-17 08:42:17 +080075 .init_early = imx51_init_early,
Shawn Guofffa0512014-05-19 20:19:06 +080076 .init_irq = tzic_init_irq,
Shawn Guo9daaf312011-10-17 08:42:17 +080077 .init_machine = imx51_dt_init,
Shawn Guo8321b752012-04-26 11:42:34 +080078 .init_late = imx51_init_late,
Shawn Guo9daaf312011-10-17 08:42:17 +080079 .dt_compat = imx51_dt_board_compat,
Shawn Guo9daaf312011-10-17 08:42:17 +080080MACHINE_END