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Marc Zyngier140b0862015-11-26 17:19:25 +00001/*
2 * Copyright (C) 2015, 2016 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/irqchip/arm-gic.h>
18#include <linux/kvm.h>
19#include <linux/kvm_host.h>
Eric Auger90977732015-12-01 15:02:35 +010020#include <kvm/arm_vgic.h>
21#include <asm/kvm_mmu.h>
Marc Zyngier140b0862015-11-26 17:19:25 +000022
23#include "vgic.h"
24
Christoffer Dall5b0d2cc2017-03-18 13:56:56 +010025static inline void vgic_v2_write_lr(int lr, u32 val)
26{
27 void __iomem *base = kvm_vgic_global_state.vctrl_base;
28
29 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
30}
31
32void vgic_v2_init_lrs(void)
33{
34 int i;
35
36 for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
37 vgic_v2_write_lr(i, 0);
38}
39
Marc Zyngier140b0862015-11-26 17:19:25 +000040void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
41{
42 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
43
44 cpuif->vgic_hcr |= GICH_HCR_UIE;
45}
46
Christoffer Dallaf061492016-12-29 15:44:27 +010047static bool lr_signals_eoi_mi(u32 lr_val)
48{
49 return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
50 !(lr_val & GICH_LR_HW);
51}
52
Marc Zyngier140b0862015-11-26 17:19:25 +000053/*
54 * transfer the content of the LRs back into the corresponding ap_list:
55 * - active bit is transferred as is
56 * - pending bit is
57 * - transferred as is in case of edge sensitive IRQs
58 * - set to the line-level (resample time) for level sensitive IRQs
59 */
60void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
61{
Christoffer Dall8ac76ef2017-03-18 13:48:42 +010062 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
63 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
Marc Zyngier140b0862015-11-26 17:19:25 +000064 int lr;
65
Christoffer Dallaf061492016-12-29 15:44:27 +010066 cpuif->vgic_hcr &= ~GICH_HCR_UIE;
67
Christoffer Dall8ac76ef2017-03-18 13:48:42 +010068 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
Marc Zyngier140b0862015-11-26 17:19:25 +000069 u32 val = cpuif->vgic_lr[lr];
70 u32 intid = val & GICH_LR_VIRTUALID;
71 struct vgic_irq *irq;
72
Christoffer Dallaf061492016-12-29 15:44:27 +010073 /* Notify fds when the guest EOI'ed a level-triggered SPI */
74 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
75 kvm_notify_acked_irq(vcpu->kvm, 0,
76 intid - VGIC_NR_PRIVATE_IRQS);
77
Marc Zyngier140b0862015-11-26 17:19:25 +000078 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
79
80 spin_lock(&irq->irq_lock);
81
82 /* Always preserve the active bit */
83 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
84
85 /* Edge is the only case where we preserve the pending bit */
86 if (irq->config == VGIC_CONFIG_EDGE &&
87 (val & GICH_LR_PENDING_BIT)) {
Christoffer Dall8694e4d2017-01-23 14:07:18 +010088 irq->pending_latch = true;
Marc Zyngier140b0862015-11-26 17:19:25 +000089
90 if (vgic_irq_is_sgi(intid)) {
91 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
92
93 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
94 irq->source |= (1 << cpuid);
95 }
96 }
97
Marc Zyngierdf7942d2016-05-25 15:26:35 +010098 /*
99 * Clear soft pending state when level irqs have been acked.
100 * Always regenerate the pending state.
101 */
102 if (irq->config == VGIC_CONFIG_LEVEL) {
103 if (!(val & GICH_LR_PENDING_BIT))
Christoffer Dall8694e4d2017-01-23 14:07:18 +0100104 irq->pending_latch = false;
Marc Zyngier140b0862015-11-26 17:19:25 +0000105 }
106
107 spin_unlock(&irq->irq_lock);
Andre Przywara5dd4b922016-07-15 12:43:27 +0100108 vgic_put_irq(vcpu->kvm, irq);
Marc Zyngier140b0862015-11-26 17:19:25 +0000109 }
Christoffer Dall8ac76ef2017-03-18 13:48:42 +0100110
111 vgic_cpu->used_lrs = 0;
Marc Zyngier140b0862015-11-26 17:19:25 +0000112}
113
114/*
115 * Populates the particular LR with the state of a given IRQ:
116 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
117 * - for a level sensitive IRQ the pending state value is unchanged;
118 * it is dictated directly by the input level
119 *
120 * If @irq describes an SGI with multiple sources, we choose the
121 * lowest-numbered source VCPU and clear that bit in the source bitmap.
122 *
123 * The irq_lock must be held by the caller.
124 */
125void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
126{
127 u32 val = irq->intid;
128
Christoffer Dall8694e4d2017-01-23 14:07:18 +0100129 if (irq_is_pending(irq)) {
Marc Zyngier140b0862015-11-26 17:19:25 +0000130 val |= GICH_LR_PENDING_BIT;
131
132 if (irq->config == VGIC_CONFIG_EDGE)
Christoffer Dall8694e4d2017-01-23 14:07:18 +0100133 irq->pending_latch = false;
Marc Zyngier140b0862015-11-26 17:19:25 +0000134
135 if (vgic_irq_is_sgi(irq->intid)) {
136 u32 src = ffs(irq->source);
137
138 BUG_ON(!src);
139 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
140 irq->source &= ~(1 << (src - 1));
141 if (irq->source)
Christoffer Dall8694e4d2017-01-23 14:07:18 +0100142 irq->pending_latch = true;
Marc Zyngier140b0862015-11-26 17:19:25 +0000143 }
144 }
145
146 if (irq->active)
147 val |= GICH_LR_ACTIVE_BIT;
148
149 if (irq->hw) {
150 val |= GICH_LR_HW;
151 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
Marc Zyngierddf42d02017-05-02 14:30:39 +0100152 /*
153 * Never set pending+active on a HW interrupt, as the
154 * pending state is kept at the physical distributor
155 * level.
156 */
157 if (irq->active && irq_is_pending(irq))
158 val &= ~GICH_LR_PENDING_BIT;
Marc Zyngier140b0862015-11-26 17:19:25 +0000159 } else {
160 if (irq->config == VGIC_CONFIG_LEVEL)
161 val |= GICH_LR_EOI;
162 }
163
164 /* The GICv2 LR only holds five bits of priority. */
165 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
166
167 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
168}
169
170void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
171{
172 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
173}
Andre Przywarae4823a72015-12-03 11:47:37 +0000174
175void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
176{
Christoffer Dall328e5662016-03-24 11:21:04 +0100177 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
Andre Przywarae4823a72015-12-03 11:47:37 +0000178 u32 vmcr;
179
180 vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
181 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
182 GICH_VMCR_ALIAS_BINPOINT_MASK;
183 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
184 GICH_VMCR_BINPOINT_MASK;
Christoffer Dall6d561112017-03-21 22:05:22 +0100185 vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
186 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
Andre Przywarae4823a72015-12-03 11:47:37 +0000187
Christoffer Dall328e5662016-03-24 11:21:04 +0100188 cpu_if->vgic_vmcr = vmcr;
Andre Przywarae4823a72015-12-03 11:47:37 +0000189}
190
191void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
192{
Christoffer Dall328e5662016-03-24 11:21:04 +0100193 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
194 u32 vmcr;
195
196 vmcr = cpu_if->vgic_vmcr;
Andre Przywarae4823a72015-12-03 11:47:37 +0000197
198 vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
199 GICH_VMCR_CTRL_SHIFT;
200 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
201 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
202 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
203 GICH_VMCR_BINPOINT_SHIFT;
Christoffer Dall6d561112017-03-21 22:05:22 +0100204 vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
205 GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
Andre Przywarae4823a72015-12-03 11:47:37 +0000206}
Eric Auger90977732015-12-01 15:02:35 +0100207
Eric Augerad275b8b2015-12-21 18:09:38 +0100208void vgic_v2_enable(struct kvm_vcpu *vcpu)
209{
Eric Augerf7b69852015-12-02 10:30:13 +0100210 /*
211 * By forcing VMCR to zero, the GIC will restore the binary
212 * points to their reset values. Anything else resets to zero
213 * anyway.
214 */
215 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
216 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
217
218 /* Get the show on the road... */
219 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
Eric Augerad275b8b2015-12-21 18:09:38 +0100220}
221
Eric Augerb0442ee2015-12-21 15:04:42 +0100222/* check for overlapping regions and for regions crossing the end of memory */
223static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
224{
225 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
226 return false;
227 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
228 return false;
229
230 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
231 return true;
232 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
233 return true;
234
235 return false;
236}
237
238int vgic_v2_map_resources(struct kvm *kvm)
239{
240 struct vgic_dist *dist = &kvm->arch.vgic;
241 int ret = 0;
242
243 if (vgic_ready(kvm))
244 goto out;
245
246 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
247 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
248 kvm_err("Need to set vgic cpu and dist addresses first\n");
249 ret = -ENXIO;
250 goto out;
251 }
252
253 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
254 kvm_err("VGIC CPU and dist frames overlap\n");
255 ret = -EINVAL;
256 goto out;
257 }
258
259 /*
260 * Initialize the vgic if this hasn't already been done on demand by
261 * accessing the vgic state from userspace.
262 */
263 ret = vgic_init(kvm);
264 if (ret) {
265 kvm_err("Unable to initialize VGIC dynamic data structures\n");
266 goto out;
267 }
268
269 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
270 if (ret) {
271 kvm_err("Unable to register VGIC MMIO regions\n");
272 goto out;
273 }
274
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100275 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
276 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
277 kvm_vgic_global_state.vcpu_base,
278 KVM_VGIC_V2_CPU_SIZE, true);
279 if (ret) {
280 kvm_err("Unable to remap VGIC CPU to VCPU\n");
281 goto out;
282 }
Eric Augerb0442ee2015-12-21 15:04:42 +0100283 }
284
285 dist->ready = true;
286
287out:
Eric Augerb0442ee2015-12-21 15:04:42 +0100288 return ret;
289}
290
Marc Zyngierfb5ee362016-09-06 09:28:45 +0100291DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
292
Eric Auger90977732015-12-01 15:02:35 +0100293/**
294 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
295 * @node: pointer to the DT node
296 *
297 * Returns 0 if a GICv2 has been found, returns an error code otherwise
298 */
299int vgic_v2_probe(const struct gic_kvm_info *info)
300{
301 int ret;
302 u32 vtr;
303
304 if (!info->vctrl.start) {
305 kvm_err("GICH not present in the firmware table\n");
306 return -ENXIO;
307 }
308
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100309 if (!PAGE_ALIGNED(info->vcpu.start) ||
310 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
311 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
312 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
313 resource_size(&info->vcpu));
314 if (!kvm_vgic_global_state.vcpu_base_va) {
315 kvm_err("Cannot ioremap GICV\n");
316 return -ENOMEM;
317 }
Eric Auger90977732015-12-01 15:02:35 +0100318
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100319 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
320 kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
321 info->vcpu.start);
322 if (ret) {
323 kvm_err("Cannot map GICV into hyp\n");
324 goto out;
325 }
326
327 static_branch_enable(&vgic_v2_cpuif_trap);
Eric Auger90977732015-12-01 15:02:35 +0100328 }
329
330 kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
331 resource_size(&info->vctrl));
332 if (!kvm_vgic_global_state.vctrl_base) {
333 kvm_err("Cannot ioremap GICH\n");
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100334 ret = -ENOMEM;
335 goto out;
Eric Auger90977732015-12-01 15:02:35 +0100336 }
337
338 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
339 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
340
341 ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
342 kvm_vgic_global_state.vctrl_base +
343 resource_size(&info->vctrl),
344 info->vctrl.start);
Eric Auger90977732015-12-01 15:02:35 +0100345 if (ret) {
346 kvm_err("Cannot map VCTRL into hyp\n");
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100347 goto out;
348 }
349
350 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
351 if (ret) {
352 kvm_err("Cannot register GICv2 KVM device\n");
353 goto out;
Eric Auger90977732015-12-01 15:02:35 +0100354 }
355
356 kvm_vgic_global_state.can_emulate_gicv2 = true;
Eric Auger90977732015-12-01 15:02:35 +0100357 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
358 kvm_vgic_global_state.type = VGIC_V2;
359 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
360
361 kvm_info("vgic-v2@%llx\n", info->vctrl.start);
362
363 return 0;
Marc Zyngiera07d3b02016-09-06 09:28:47 +0100364out:
365 if (kvm_vgic_global_state.vctrl_base)
366 iounmap(kvm_vgic_global_state.vctrl_base);
367 if (kvm_vgic_global_state.vcpu_base_va)
368 iounmap(kvm_vgic_global_state.vcpu_base_va);
369
370 return ret;
Eric Auger90977732015-12-01 15:02:35 +0100371}
Christoffer Dall328e5662016-03-24 11:21:04 +0100372
373void vgic_v2_load(struct kvm_vcpu *vcpu)
374{
375 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
376 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
377
378 writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
379}
380
381void vgic_v2_put(struct kvm_vcpu *vcpu)
382{
383 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
384 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
385
386 cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
387}