Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC |
| 3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, |
| 4 | * AT91SAM9X25, AT91SAM9X35 SoC |
| 5 | * |
| 6 | * Copyright (C) 2012 Atmel, |
| 7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> |
| 8 | * |
| 9 | * Licensed under GPLv2 or later. |
| 10 | */ |
| 11 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 12 | #include "skeleton.dtsi" |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 13 | #include <dt-bindings/dma/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 14 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 16 | #include <dt-bindings/gpio/gpio.h> |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Atmel AT91SAM9x5 family SoC"; |
| 20 | compatible = "atmel,at91sam9x5"; |
| 21 | interrupt-parent = <&aic>; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &dbgu; |
| 25 | serial1 = &usart0; |
| 26 | serial2 = &usart1; |
| 27 | serial3 = &usart2; |
| 28 | gpio0 = &pioA; |
| 29 | gpio1 = &pioB; |
| 30 | gpio2 = &pioC; |
| 31 | gpio3 = &pioD; |
| 32 | tcb0 = &tcb0; |
| 33 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 34 | i2c0 = &i2c0; |
| 35 | i2c1 = &i2c1; |
| 36 | i2c2 = &i2c2; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 37 | ssc0 = &ssc0; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 38 | }; |
| 39 | cpus { |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 40 | #address-cells = <0>; |
| 41 | #size-cells = <0>; |
| 42 | |
| 43 | cpu { |
| 44 | compatible = "arm,arm926ej-s"; |
| 45 | device_type = "cpu"; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 46 | }; |
| 47 | }; |
| 48 | |
Ludovic Desroches | dcce6ce | 2012-04-02 20:44:20 +0200 | [diff] [blame] | 49 | memory { |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 50 | reg = <0x20000000 0x10000000>; |
| 51 | }; |
| 52 | |
| 53 | ahb { |
| 54 | compatible = "simple-bus"; |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <1>; |
| 57 | ranges; |
| 58 | |
| 59 | apb { |
| 60 | compatible = "simple-bus"; |
| 61 | #address-cells = <1>; |
| 62 | #size-cells = <1>; |
| 63 | ranges; |
| 64 | |
| 65 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 66 | #interrupt-cells = <3>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 67 | compatible = "atmel,at91rm9200-aic"; |
| 68 | interrupt-controller; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 69 | reg = <0xfffff000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | c657394 | 2012-04-09 19:36:36 +0800 | [diff] [blame] | 70 | atmel,external-irqs = <31>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 71 | }; |
| 72 | |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 73 | ramc0: ramc@ffffe800 { |
| 74 | compatible = "atmel,at91sam9g45-ddramc"; |
| 75 | reg = <0xffffe800 0x200>; |
| 76 | }; |
| 77 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 78 | pmc: pmc@fffffc00 { |
| 79 | compatible = "atmel,at91rm9200-pmc"; |
| 80 | reg = <0xfffffc00 0x100>; |
| 81 | }; |
| 82 | |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 83 | rstc@fffffe00 { |
| 84 | compatible = "atmel,at91sam9g45-rstc"; |
| 85 | reg = <0xfffffe00 0x10>; |
| 86 | }; |
| 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 88 | shdwc@fffffe10 { |
| 89 | compatible = "atmel,at91sam9x5-shdwc"; |
| 90 | reg = <0xfffffe10 0x10>; |
| 91 | }; |
| 92 | |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 93 | pit: timer@fffffe30 { |
| 94 | compatible = "atmel,at91sam9260-pit"; |
| 95 | reg = <0xfffffe30 0xf>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 96 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | tcb0: timer@f8008000 { |
| 100 | compatible = "atmel,at91sam9x5-tcb"; |
| 101 | reg = <0xf8008000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 102 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | tcb1: timer@f800c000 { |
| 106 | compatible = "atmel,at91sam9x5-tcb"; |
| 107 | reg = <0xf800c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 108 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | dma0: dma-controller@ffffec00 { |
| 112 | compatible = "atmel,at91sam9g45-dma"; |
| 113 | reg = <0xffffec00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 114 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 115 | #dma-cells = <2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | dma1: dma-controller@ffffee00 { |
| 119 | compatible = "atmel,at91sam9g45-dma"; |
| 120 | reg = <0xffffee00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 121 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 122 | #dma-cells = <2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 123 | }; |
| 124 | |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 125 | pinctrl@fffff400 { |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 126 | #address-cells = <1>; |
| 127 | #size-cells = <1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 128 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 129 | ranges = <0xfffff400 0xfffff400 0x800>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 130 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 131 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 132 | dbgu { |
| 133 | pinctrl_dbgu: dbgu-0 { |
| 134 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 135 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 136 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 137 | }; |
| 138 | }; |
| 139 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 140 | usart0 { |
| 141 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 142 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 143 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ |
| 144 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 145 | }; |
| 146 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 147 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 148 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 149 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | pinctrl_usart0_cts: usart0_cts-0 { |
| 153 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 154 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 155 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 156 | |
| 157 | pinctrl_usart0_sck: usart0_sck-0 { |
| 158 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 159 | <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 160 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 161 | }; |
| 162 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 163 | usart1 { |
| 164 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 165 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 166 | <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ |
| 167 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 168 | }; |
| 169 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 170 | pinctrl_usart1_rts: usart1_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 171 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 172 | <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | pinctrl_usart1_cts: usart1_cts-0 { |
| 176 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 177 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 178 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 179 | |
| 180 | pinctrl_usart1_sck: usart1_sck-0 { |
| 181 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 182 | <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 183 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 184 | }; |
| 185 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 186 | usart2 { |
| 187 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 188 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 189 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 190 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 191 | }; |
| 192 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 193 | pinctrl_uart2_rts: uart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 194 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 195 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | pinctrl_uart2_cts: uart2_cts-0 { |
| 199 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 200 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 201 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 202 | |
| 203 | pinctrl_usart2_sck: usart2_sck-0 { |
| 204 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 205 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 206 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 207 | }; |
| 208 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 209 | usart3 { |
Robert Nelson | 65a0fe0 | 2013-01-28 09:43:36 -0600 | [diff] [blame] | 210 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 211 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 212 | <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ |
| 213 | AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 214 | }; |
| 215 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 216 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 217 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 218 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | pinctrl_usart3_cts: usart3_cts-0 { |
| 222 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 223 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 224 | }; |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 225 | |
| 226 | pinctrl_usart3_sck: usart3_sck-0 { |
| 227 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 228 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ |
Richard Genoud | 1bab02e | 2013-01-18 16:42:28 +0000 | [diff] [blame] | 229 | }; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 230 | }; |
| 231 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 232 | uart0 { |
| 233 | pinctrl_uart0: uart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 234 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 235 | <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ |
| 236 | AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 237 | }; |
| 238 | }; |
| 239 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 240 | uart1 { |
| 241 | pinctrl_uart1: uart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 242 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 243 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ |
| 244 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 245 | }; |
| 246 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 247 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 248 | nand { |
| 249 | pinctrl_nand: nand-0 { |
| 250 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 251 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ |
| 252 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ |
| 253 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ |
| 254 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ |
| 255 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ |
| 256 | AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ |
| 257 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ |
| 258 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ |
| 259 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ |
| 260 | AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ |
| 261 | AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ |
| 262 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ |
| 263 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ |
| 264 | AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ |
Richard Genoud | 7f06472 | 2013-03-11 15:12:40 +0100 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | pinctrl_nand_16bits: nand_16bits-0 { |
| 268 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 269 | <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ |
| 270 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ |
| 271 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ |
| 272 | AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ |
| 273 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ |
| 274 | AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ |
| 275 | AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ |
| 276 | AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 277 | }; |
| 278 | }; |
| 279 | |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 280 | macb0 { |
| 281 | pinctrl_macb0_rmii: macb0_rmii-0 { |
| 282 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 283 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ |
| 284 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ |
| 285 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ |
| 286 | AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ |
| 287 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| 288 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ |
| 289 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
| 290 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ |
| 291 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
| 292 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 293 | }; |
| 294 | |
| 295 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { |
| 296 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 297 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ |
| 298 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ |
| 299 | AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 300 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ |
| 301 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ |
| 302 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ |
| 303 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ |
| 304 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 305 | }; |
| 306 | }; |
| 307 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 308 | mmc0 { |
| 309 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 310 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 311 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 312 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 313 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 317 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 318 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 319 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 320 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 321 | }; |
| 322 | }; |
| 323 | |
| 324 | mmc1 { |
| 325 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 326 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 327 | <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ |
| 328 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 329 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 333 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 334 | <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ |
| 335 | AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ |
| 336 | AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 337 | }; |
| 338 | }; |
| 339 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 340 | ssc0 { |
| 341 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 342 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 343 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 344 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 345 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 349 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 350 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 351 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 352 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 353 | }; |
| 354 | }; |
| 355 | |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 356 | spi0 { |
| 357 | pinctrl_spi0: spi0-0 { |
| 358 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 359 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 360 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 361 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 362 | }; |
| 363 | }; |
| 364 | |
| 365 | spi1 { |
| 366 | pinctrl_spi1: spi1-0 { |
| 367 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 368 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 369 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 370 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 371 | }; |
| 372 | }; |
| 373 | |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 374 | i2c0 { |
| 375 | pinctrl_i2c0: i2c0-0 { |
| 376 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 377 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ |
| 378 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 379 | }; |
| 380 | }; |
| 381 | |
| 382 | i2c1 { |
| 383 | pinctrl_i2c1: i2c1-0 { |
| 384 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 385 | <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ |
| 386 | AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 387 | }; |
| 388 | }; |
| 389 | |
| 390 | i2c2 { |
| 391 | pinctrl_i2c2: i2c2-0 { |
| 392 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 393 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ |
| 394 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 395 | }; |
| 396 | }; |
| 397 | |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 398 | i2c_gpio0 { |
| 399 | pinctrl_i2c_gpio0: i2c_gpio0-0 { |
| 400 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 401 | <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ |
| 402 | AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 403 | }; |
| 404 | }; |
| 405 | |
| 406 | i2c_gpio1 { |
| 407 | pinctrl_i2c_gpio1: i2c_gpio1-0 { |
| 408 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 409 | <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ |
| 410 | AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 411 | }; |
| 412 | }; |
| 413 | |
| 414 | i2c_gpio2 { |
| 415 | pinctrl_i2c_gpio2: i2c_gpio2-0 { |
| 416 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 417 | <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ |
| 418 | AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 419 | }; |
| 420 | }; |
| 421 | |
Boris BREZILLON | 028633c | 2013-05-24 10:05:56 +0000 | [diff] [blame] | 422 | tcb0 { |
| 423 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| 424 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 425 | }; |
| 426 | |
| 427 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { |
| 428 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 429 | }; |
| 430 | |
| 431 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { |
| 432 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 433 | }; |
| 434 | |
| 435 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { |
| 436 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 437 | }; |
| 438 | |
| 439 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { |
| 440 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 441 | }; |
| 442 | |
| 443 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { |
| 444 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 445 | }; |
| 446 | |
| 447 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { |
| 448 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 449 | }; |
| 450 | |
| 451 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { |
| 452 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 453 | }; |
| 454 | |
| 455 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { |
| 456 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 457 | }; |
| 458 | }; |
| 459 | |
| 460 | tcb1 { |
| 461 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { |
| 462 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 463 | }; |
| 464 | |
| 465 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { |
| 466 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 467 | }; |
| 468 | |
| 469 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { |
| 470 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 471 | }; |
| 472 | |
| 473 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { |
| 474 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 475 | }; |
| 476 | |
| 477 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { |
| 478 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 479 | }; |
| 480 | |
| 481 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { |
| 482 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 483 | }; |
| 484 | |
| 485 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { |
| 486 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 487 | }; |
| 488 | |
| 489 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { |
| 490 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 491 | }; |
| 492 | |
| 493 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { |
| 494 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; |
| 495 | }; |
| 496 | }; |
| 497 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 498 | pioA: gpio@fffff400 { |
| 499 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 500 | reg = <0xfffff400 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 501 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 502 | #gpio-cells = <2>; |
| 503 | gpio-controller; |
| 504 | interrupt-controller; |
| 505 | #interrupt-cells = <2>; |
| 506 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 507 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 508 | pioB: gpio@fffff600 { |
| 509 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 510 | reg = <0xfffff600 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 511 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 512 | #gpio-cells = <2>; |
| 513 | gpio-controller; |
Jean-Christophe PLAGNIOL-VILLARD | fc33ff4 | 2012-07-14 15:26:08 +0800 | [diff] [blame] | 514 | #gpio-lines = <19>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 515 | interrupt-controller; |
| 516 | #interrupt-cells = <2>; |
| 517 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 518 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 519 | pioC: gpio@fffff800 { |
| 520 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 521 | reg = <0xfffff800 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 522 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 523 | #gpio-cells = <2>; |
| 524 | gpio-controller; |
| 525 | interrupt-controller; |
| 526 | #interrupt-cells = <2>; |
| 527 | }; |
| 528 | |
| 529 | pioD: gpio@fffffa00 { |
| 530 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 531 | reg = <0xfffffa00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 532 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 533 | #gpio-cells = <2>; |
| 534 | gpio-controller; |
Jean-Christophe PLAGNIOL-VILLARD | fc33ff4 | 2012-07-14 15:26:08 +0800 | [diff] [blame] | 535 | #gpio-lines = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 536 | interrupt-controller; |
| 537 | #interrupt-cells = <2>; |
| 538 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 539 | }; |
| 540 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 541 | ssc0: ssc@f0010000 { |
| 542 | compatible = "atmel,at91sam9g45-ssc"; |
| 543 | reg = <0xf0010000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 544 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
Richard Genoud | 7da49ad | 2013-08-12 14:30:59 +0200 | [diff] [blame] | 545 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, |
| 546 | <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; |
| 547 | dma-names = "tx", "rx"; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 548 | pinctrl-names = "default"; |
| 549 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 550 | status = "disabled"; |
| 551 | }; |
| 552 | |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 553 | mmc0: mmc@f0008000 { |
| 554 | compatible = "atmel,hsmci"; |
| 555 | reg = <0xf0008000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 556 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 557 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 558 | dma-names = "rxtx"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 559 | #address-cells = <1>; |
| 560 | #size-cells = <0>; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | |
| 564 | mmc1: mmc@f000c000 { |
| 565 | compatible = "atmel,hsmci"; |
| 566 | reg = <0xf000c000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 567 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 568 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 569 | dma-names = "rxtx"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 570 | #address-cells = <1>; |
| 571 | #size-cells = <0>; |
| 572 | status = "disabled"; |
| 573 | }; |
| 574 | |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 575 | dbgu: serial@fffff200 { |
| 576 | compatible = "atmel,at91sam9260-usart"; |
| 577 | reg = <0xfffff200 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 578 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 579 | pinctrl-names = "default"; |
| 580 | pinctrl-0 = <&pinctrl_dbgu>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 581 | status = "disabled"; |
| 582 | }; |
| 583 | |
| 584 | usart0: serial@f801c000 { |
| 585 | compatible = "atmel,at91sam9260-usart"; |
| 586 | reg = <0xf801c000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 587 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 588 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 589 | pinctrl-0 = <&pinctrl_usart0>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 590 | status = "disabled"; |
| 591 | }; |
| 592 | |
| 593 | usart1: serial@f8020000 { |
| 594 | compatible = "atmel,at91sam9260-usart"; |
| 595 | reg = <0xf8020000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 596 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 597 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 598 | pinctrl-0 = <&pinctrl_usart1>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 599 | status = "disabled"; |
| 600 | }; |
| 601 | |
| 602 | usart2: serial@f8024000 { |
| 603 | compatible = "atmel,at91sam9260-usart"; |
| 604 | reg = <0xf8024000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 605 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 606 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 607 | pinctrl-0 = <&pinctrl_usart2>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 608 | status = "disabled"; |
| 609 | }; |
| 610 | |
| 611 | macb0: ethernet@f802c000 { |
| 612 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 613 | reg = <0xf802c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 614 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 615 | pinctrl-names = "default"; |
| 616 | pinctrl-0 = <&pinctrl_macb0_rmii>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 617 | status = "disabled"; |
| 618 | }; |
| 619 | |
| 620 | macb1: ethernet@f8030000 { |
| 621 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 622 | reg = <0xf8030000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 623 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 624 | status = "disabled"; |
| 625 | }; |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 626 | |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 627 | i2c0: i2c@f8010000 { |
| 628 | compatible = "atmel,at91sam9x5-i2c"; |
| 629 | reg = <0xf8010000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 630 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 631 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, |
| 632 | <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 633 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 634 | #address-cells = <1>; |
| 635 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 636 | pinctrl-names = "default"; |
| 637 | pinctrl-0 = <&pinctrl_i2c0>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 638 | status = "disabled"; |
| 639 | }; |
| 640 | |
| 641 | i2c1: i2c@f8014000 { |
| 642 | compatible = "atmel,at91sam9x5-i2c"; |
| 643 | reg = <0xf8014000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 644 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 645 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, |
| 646 | <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 647 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 648 | #address-cells = <1>; |
| 649 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 650 | pinctrl-names = "default"; |
| 651 | pinctrl-0 = <&pinctrl_i2c1>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 652 | status = "disabled"; |
| 653 | }; |
| 654 | |
| 655 | i2c2: i2c@f8018000 { |
| 656 | compatible = "atmel,at91sam9x5-i2c"; |
| 657 | reg = <0xf8018000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 658 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 659 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, |
| 660 | <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; |
Ludovic Desroches | d9a63a4 | 2013-04-16 15:03:08 +0200 | [diff] [blame] | 661 | dma-names = "tx", "rx"; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 662 | #address-cells = <1>; |
| 663 | #size-cells = <0>; |
Richard Genoud | e9a72ee | 2013-03-12 17:54:45 +0100 | [diff] [blame] | 664 | pinctrl-names = "default"; |
| 665 | pinctrl-0 = <&pinctrl_i2c2>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 666 | status = "disabled"; |
| 667 | }; |
| 668 | |
Nicolas Ferre | 06723db | 2013-04-18 10:52:45 +0200 | [diff] [blame] | 669 | uart0: serial@f8040000 { |
| 670 | compatible = "atmel,at91sam9260-usart"; |
| 671 | reg = <0xf8040000 0x200>; |
| 672 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 673 | pinctrl-names = "default"; |
| 674 | pinctrl-0 = <&pinctrl_uart0>; |
| 675 | status = "disabled"; |
| 676 | }; |
| 677 | |
| 678 | uart1: serial@f8044000 { |
| 679 | compatible = "atmel,at91sam9260-usart"; |
| 680 | reg = <0xf8044000 0x200>; |
| 681 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 682 | pinctrl-names = "default"; |
| 683 | pinctrl-0 = <&pinctrl_uart1>; |
| 684 | status = "disabled"; |
| 685 | }; |
| 686 | |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 687 | adc0: adc@f804c000 { |
| 688 | compatible = "atmel,at91sam9260-adc"; |
| 689 | reg = <0xf804c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 690 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 691 | atmel,adc-use-external; |
| 692 | atmel,adc-channels-used = <0xffff>; |
| 693 | atmel,adc-vref = <3300>; |
| 694 | atmel,adc-num-channels = <12>; |
| 695 | atmel,adc-startup-time = <40>; |
| 696 | atmel,adc-channel-base = <0x50>; |
| 697 | atmel,adc-drdy-mask = <0x1000000>; |
| 698 | atmel,adc-status-register = <0x30>; |
| 699 | atmel,adc-trigger-register = <0xc0>; |
Ludovic Desroches | 4b50da6 | 2013-03-29 10:13:19 +0100 | [diff] [blame] | 700 | atmel,adc-res = <8 10>; |
| 701 | atmel,adc-res-names = "lowres", "highres"; |
| 702 | atmel,adc-use-res = "highres"; |
Maxime Ripard | d029f37 | 2012-05-11 15:35:39 +0200 | [diff] [blame] | 703 | |
| 704 | trigger@0 { |
| 705 | trigger-name = "external-rising"; |
| 706 | trigger-value = <0x1>; |
| 707 | trigger-external; |
| 708 | }; |
| 709 | |
| 710 | trigger@1 { |
| 711 | trigger-name = "external-falling"; |
| 712 | trigger-value = <0x2>; |
| 713 | trigger-external; |
| 714 | }; |
| 715 | |
| 716 | trigger@2 { |
| 717 | trigger-name = "external-any"; |
| 718 | trigger-value = <0x3>; |
| 719 | trigger-external; |
| 720 | }; |
| 721 | |
| 722 | trigger@3 { |
| 723 | trigger-name = "continuous"; |
| 724 | trigger-value = <0x6>; |
| 725 | }; |
| 726 | }; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 727 | |
| 728 | spi0: spi@f0000000 { |
| 729 | #address-cells = <1>; |
| 730 | #size-cells = <0>; |
| 731 | compatible = "atmel,at91rm9200-spi"; |
| 732 | reg = <0xf0000000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 733 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
Richard Genoud | 6b2a999 | 2013-05-31 17:02:00 +0200 | [diff] [blame] | 734 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, |
| 735 | <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; |
| 736 | dma-names = "tx", "rx"; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 737 | pinctrl-names = "default"; |
| 738 | pinctrl-0 = <&pinctrl_spi0>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 739 | status = "disabled"; |
| 740 | }; |
| 741 | |
| 742 | spi1: spi@f0004000 { |
| 743 | #address-cells = <1>; |
| 744 | #size-cells = <0>; |
| 745 | compatible = "atmel,at91rm9200-spi"; |
| 746 | reg = <0xf0004000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 747 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
Richard Genoud | 6b2a999 | 2013-05-31 17:02:00 +0200 | [diff] [blame] | 748 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, |
| 749 | <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; |
| 750 | dma-names = "tx", "rx"; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 751 | pinctrl-names = "default"; |
| 752 | pinctrl-0 = <&pinctrl_spi1>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 753 | status = "disabled"; |
| 754 | }; |
Linus Torvalds | dfab34a | 2013-05-02 09:28:03 -0700 | [diff] [blame] | 755 | |
Jean-Christophe PLAGNIOL-VILLARD | aecca65 | 2013-05-03 20:49:51 +0800 | [diff] [blame] | 756 | usb2: gadget@f803c000 { |
| 757 | #address-cells = <1>; |
| 758 | #size-cells = <0>; |
| 759 | compatible = "atmel,at91sam9rl-udc"; |
| 760 | reg = <0x00500000 0x80000 |
| 761 | 0xf803c000 0x400>; |
| 762 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; |
| 763 | status = "disabled"; |
| 764 | |
| 765 | ep0 { |
| 766 | reg = <0>; |
| 767 | atmel,fifo-size = <64>; |
| 768 | atmel,nb-banks = <1>; |
| 769 | }; |
| 770 | |
| 771 | ep1 { |
| 772 | reg = <1>; |
| 773 | atmel,fifo-size = <1024>; |
| 774 | atmel,nb-banks = <2>; |
| 775 | atmel,can-dma; |
| 776 | atmel,can-isoc; |
| 777 | }; |
| 778 | |
| 779 | ep2 { |
| 780 | reg = <2>; |
| 781 | atmel,fifo-size = <1024>; |
| 782 | atmel,nb-banks = <2>; |
| 783 | atmel,can-dma; |
| 784 | atmel,can-isoc; |
| 785 | }; |
| 786 | |
| 787 | ep3 { |
| 788 | reg = <3>; |
| 789 | atmel,fifo-size = <1024>; |
| 790 | atmel,nb-banks = <3>; |
| 791 | atmel,can-dma; |
| 792 | }; |
| 793 | |
| 794 | ep4 { |
| 795 | reg = <4>; |
| 796 | atmel,fifo-size = <1024>; |
| 797 | atmel,nb-banks = <3>; |
| 798 | atmel,can-dma; |
| 799 | }; |
| 800 | |
| 801 | ep5 { |
| 802 | reg = <5>; |
| 803 | atmel,fifo-size = <1024>; |
| 804 | atmel,nb-banks = <3>; |
| 805 | atmel,can-dma; |
| 806 | atmel,can-isoc; |
| 807 | }; |
| 808 | |
| 809 | ep6 { |
| 810 | reg = <6>; |
| 811 | atmel,fifo-size = <1024>; |
| 812 | atmel,nb-banks = <3>; |
| 813 | atmel,can-dma; |
| 814 | atmel,can-isoc; |
| 815 | }; |
| 816 | }; |
| 817 | |
Wenyou Yang | 136d355 | 2013-05-31 11:10:02 +0800 | [diff] [blame] | 818 | watchdog@fffffe40 { |
| 819 | compatible = "atmel,at91sam9260-wdt"; |
| 820 | reg = <0xfffffe40 0x10>; |
| 821 | status = "disabled"; |
| 822 | }; |
| 823 | |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 824 | rtc@fffffeb0 { |
Nicolas Ferre | 23fb05c | 2013-04-18 10:13:21 +0200 | [diff] [blame] | 825 | compatible = "atmel,at91sam9x5-rtc"; |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 826 | reg = <0xfffffeb0 0x40>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 827 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Nicolas Ferre | b909c6c | 2013-03-22 10:16:56 +0100 | [diff] [blame] | 828 | status = "disabled"; |
| 829 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 830 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 831 | |
| 832 | nand0: nand@40000000 { |
| 833 | compatible = "atmel,at91rm9200-nand"; |
| 834 | #address-cells = <1>; |
| 835 | #size-cells = <1>; |
| 836 | reg = <0x40000000 0x10000000 |
Josh Wu | 5314bc2 | 2013-01-23 20:47:09 +0800 | [diff] [blame] | 837 | 0xffffe000 0x600 /* PMECC Registers */ |
| 838 | 0xffffe600 0x200 /* PMECC Error Location Registers */ |
| 839 | 0x00108000 0x18000 /* PMECC looup table in ROM code */ |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 840 | >; |
Josh Wu | 5314bc2 | 2013-01-23 20:47:09 +0800 | [diff] [blame] | 841 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 842 | atmel,nand-addr-offset = <21>; |
| 843 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 844 | pinctrl-names = "default"; |
| 845 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 846 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 847 | &pioD 4 GPIO_ACTIVE_HIGH |
Jean-Christophe PLAGNIOL-VILLARD | 86a89f4 | 2012-02-21 21:38:18 +0800 | [diff] [blame] | 848 | 0 |
| 849 | >; |
| 850 | status = "disabled"; |
| 851 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 852 | |
| 853 | usb0: ohci@00600000 { |
| 854 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 855 | reg = <0x00600000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 856 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 857 | status = "disabled"; |
| 858 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 859 | |
| 860 | usb1: ehci@00700000 { |
| 861 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 862 | reg = <0x00700000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 863 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 864 | status = "disabled"; |
| 865 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 866 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 867 | |
| 868 | i2c@0 { |
| 869 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 870 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 871 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 872 | >; |
| 873 | i2c-gpio,sda-open-drain; |
| 874 | i2c-gpio,scl-open-drain; |
| 875 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 876 | #address-cells = <1>; |
| 877 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 878 | pinctrl-names = "default"; |
| 879 | pinctrl-0 = <&pinctrl_i2c_gpio0>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 880 | status = "disabled"; |
| 881 | }; |
| 882 | |
| 883 | i2c@1 { |
| 884 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 885 | gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ |
| 886 | &pioC 1 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 887 | >; |
| 888 | i2c-gpio,sda-open-drain; |
| 889 | i2c-gpio,scl-open-drain; |
| 890 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 891 | #address-cells = <1>; |
| 892 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 893 | pinctrl-names = "default"; |
| 894 | pinctrl-0 = <&pinctrl_i2c_gpio1>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 895 | status = "disabled"; |
| 896 | }; |
| 897 | |
| 898 | i2c@2 { |
| 899 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 900 | gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ |
| 901 | &pioB 5 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 902 | >; |
| 903 | i2c-gpio,sda-open-drain; |
| 904 | i2c-gpio,scl-open-drain; |
| 905 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 906 | #address-cells = <1>; |
| 907 | #size-cells = <0>; |
Richard Genoud | 463c9c7 | 2013-03-12 17:54:46 +0100 | [diff] [blame] | 908 | pinctrl-names = "default"; |
| 909 | pinctrl-0 = <&pinctrl_i2c_gpio2>; |
Jean-Christophe PLAGNIOL-VILLARD | 10f71c2 | 2012-02-23 22:50:32 +0800 | [diff] [blame] | 910 | status = "disabled"; |
| 911 | }; |
Nicolas Ferre | 467f1cf | 2012-01-26 11:59:20 +0100 | [diff] [blame] | 912 | }; |