arch/powerpc/boot/dts/p1025twr.dtsi

/*
 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
 *
 * Copyright 2013 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/{
       aliases {
		ethernet3 = &enet3;
		ethernet4 = &enet4;
       };
};

&lbc {
	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x4000000>;
		bank-width = <2>;
		device-width = <1>;

		partition@0 {
			/* This location must not be altered  */
			/* 256KB for Vitesse 7385 Switch firmware */
			reg = <0x0 0x00040000>;
			label = "NOR Vitesse-7385 Firmware";
			read-only;
		};

		partition@40000 {
			/* 256KB for DTB Image */
			reg = <0x00040000 0x00040000>;
			label = "NOR DTB Image";
		};

		partition@80000 {
			/* 5.5 MB for Linux Kernel Image */
			reg = <0x00080000 0x00580000>;
			label = "NOR Linux Kernel Image";
		};

		partition@400000 {
			/* 56.75MB for Root file System */
			reg = <0x00600000 0x038c0000>;
			label = "NOR Root File System";
		};

		partition@ec0000 {
			/* This location must not be altered  */
			/* 256KB for QE ucode firmware*/
			reg = <0x03ec0000 0x00040000>;
			label = "NOR QE microcode firmware";
			read-only;
		};

		partition@f00000 {
			/* This location must not be altered  */
			/* 512KB for u-boot Bootloader Image */
			/* 512KB for u-boot Environment Variables */
			reg = <0x03f00000 0x00100000>;
			label = "NOR U-Boot Image";
			read-only;
		};
	};

	/* CS2 for Display */
	display@2,0 {
		compatible = "solomon,ssd1289fb";
		reg = <0x2 0x0000 0x0004>;
	};

};

&soc {
	usb@22000 {
		phy_type = "ulpi";
	};

	mdio@24000 {
		phy0: ethernet-phy@2 {
			interrupt-parent = <&mpic>;
			interrupts = <1 1 0 0>;
			reg = <0x2>;
		};

		phy1: ethernet-phy@1 {
			interrupt-parent = <&mpic>;
			interrupts = <2 1 0 0>;
			reg = <0x1>;
		};

		tbi0: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	mdio@25000 {
		tbi1: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	mdio@26000 {
		tbi2: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet0: ethernet@b0000 {
		phy-handle = <&phy0>;
		phy-connection-type = "rgmii-id";

	};

	enet1: ethernet@b1000 {
		status = "disabled";
	};

	enet2: ethernet@b2000 {
		phy-handle = <&phy1>;
		phy-connection-type = "rgmii-id";
	};

	par_io@e0100 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xe0100 0x60>;
		ranges = <0x0 0xe0100 0x60>;
		device_type = "par_io";
		num-ports = <3>;
		pio1: ucc_pin@01 {
			pio-map = <
		/* port  pin  dir  open_drain  assignment  has_irq */
				0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
				0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
				0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
				0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
				0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
				0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
				0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
				0x0  0xc  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
				0x0  0x6  0x2  0x0  0x2  0x0    /* ENET1_RXD0_SER1_RXD0 */
				0x0  0xa  0x2  0x0  0x2  0x0    /* ENET1_RXD1_SER1_RXD1 */
				0x0  0xe  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
				0x0  0xf  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
				0x0  0x5  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
				0x0  0xd  0x1  0x0  0x2  0x0    /* ENET1_TX_ER */
				0x0  0x4  0x2  0x0  0x2  0x0    /* ENET1_RX_DV_SER1_CTS_B */
				0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RX_ER_SER1_CD_B */
				0x0  0x11 0x2  0x0  0x2  0x0    /* ENET1_CRS */
				0x0  0x10 0x2  0x0  0x2  0x0>;    /* ENET1_COL */
		};

		pio2: ucc_pin@02 {
			pio-map = <
		/* port  pin  dir  open_drain  assignment  has_irq */
				0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
				0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
				0x1  0xb  0x2  0x0  0x1  0x0    /* CLK13 */
				0x1  0x7  0x1  0x0  0x2  0x0    /* ENET5_TXD0_SER5_TXD0 */
				0x1  0xa  0x1  0x0  0x2  0x0    /* ENET5_TXD1_SER5_TXD1 */
				0x1  0x6  0x2  0x0  0x2  0x0    /* ENET5_RXD0_SER5_RXD0 */
				0x1  0x9  0x2  0x0  0x2  0x0    /* ENET5_RXD1_SER5_RXD1 */
				0x1  0x5  0x1  0x0  0x2  0x0    /* ENET5_TX_EN_SER5_RTS_B */
				0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
				0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
		};

		pio3: ucc_pin@03 {
			pio-map = <
		/* port  pin  dir  open_drain  assignment  has_irq */
				0x0  0x16 0x2  0x0  0x2  0x0    /* SER7_CD_B*/
				0x0  0x12 0x2  0x0  0x2  0x0    /* SER7_CTS_B*/
				0x0  0x13 0x1  0x0  0x2  0x0    /* SER7_RTS_B*/
				0x0  0x14 0x2  0x0  0x2  0x0    /* SER7_RXD0*/
				0x0  0x15 0x1  0x0  0x2  0x0>;    /* SER7_TXD0*/
		};

		pio4: ucc_pin@04 {
			pio-map = <
		/* port  pin  dir  open_drain  assignment  has_irq */
				0x1  0x0  0x2  0x0  0x2  0x0    /* SER3_CD_B*/
				0x0  0x1c 0x2  0x0  0x2  0x0    /* SER3_CTS_B*/
				0x0  0x1d 0x1  0x0  0x2  0x0    /* SER3_RTS_B*/
				0x0  0x1e 0x2  0x0  0x2  0x0    /* SER3_RXD0*/
				0x0  0x1f 0x1  0x0  0x2  0x0>;    /* SER3_TXD0*/
		};
	};
};

&qe {
	enet3: ucc@2000 {
		device_type = "network";
		compatible = "ucc_geth";
		rx-clock-name = "clk12";
		tx-clock-name = "clk9";
		pio-handle = <&pio1>;
		phy-handle = <&qe_phy0>;
		phy-connection-type = "mii";
	};

	mdio@2120 {
		qe_phy0: ethernet-phy@18 {
			interrupt-parent = <&mpic>;
			interrupts = <4 1 0 0>;
			reg = <0x18>;
			device_type = "ethernet-phy";
		};
		qe_phy1: ethernet-phy@19 {
			interrupt-parent = <&mpic>;
			interrupts = <5 1 0 0>;
			reg = <0x19>;
			device_type = "ethernet-phy";
		};
		tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet4: ucc@2400 {
		device_type = "network";
		compatible = "ucc_geth";
		rx-clock-name = "none";
		tx-clock-name = "clk13";
		pio-handle = <&pio2>;
		phy-handle = <&qe_phy1>;
		phy-connection-type = "rmii";
	};

	serial2: ucc@2600 {
		device_type = "serial";
		compatible = "ucc_uart";
		port-number = <0>;
		rx-clock-name = "brg6";
		tx-clock-name = "brg6";
		pio-handle = <&pio3>;
	};

	serial3: ucc@2200 {
		device_type = "serial";
		compatible = "ucc_uart";
		port-number = <1>;
		rx-clock-name = "brg2";
		tx-clock-name = "brg2";
		pio-handle = <&pio4>;
	};
};