Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 |
| 3 | * |
| 4 | * Copyright 2008-2009 Analog Devices Inc. |
| 5 | * Licensed under the GPL-2 or later. |
| 6 | */ |
| 7 | |
| 8 | #define DRIVER_NAME "bfin-lq035q1" |
| 9 | #define pr_fmt(fmt) DRIVER_NAME ": " fmt |
| 10 | |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/string.h> |
| 15 | #include <linux/fb.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 16 | #include <linux/slab.h> |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 17 | #include <linux/init.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/device.h> |
| 21 | #include <linux/backlight.h> |
| 22 | #include <linux/lcd.h> |
| 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/spi/spi.h> |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 26 | |
| 27 | #include <asm/blackfin.h> |
| 28 | #include <asm/irq.h> |
| 29 | #include <asm/dma.h> |
| 30 | #include <asm/portmux.h> |
| 31 | #include <asm/gptimers.h> |
| 32 | |
| 33 | #include <asm/bfin-lq035q1.h> |
| 34 | |
| 35 | #if defined(BF533_FAMILY) || defined(BF538_FAMILY) |
| 36 | #define TIMER_HSYNC_id TIMER1_id |
| 37 | #define TIMER_HSYNCbit TIMER1bit |
| 38 | #define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 |
| 39 | #define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 |
| 40 | #define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 |
| 41 | |
| 42 | #define TIMER_VSYNC_id TIMER2_id |
| 43 | #define TIMER_VSYNCbit TIMER2bit |
| 44 | #define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2 |
| 45 | #define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2 |
| 46 | #define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2 |
| 47 | #else |
| 48 | #define TIMER_HSYNC_id TIMER0_id |
| 49 | #define TIMER_HSYNCbit TIMER0bit |
| 50 | #define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0 |
| 51 | #define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0 |
| 52 | #define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0 |
| 53 | |
| 54 | #define TIMER_VSYNC_id TIMER1_id |
| 55 | #define TIMER_VSYNCbit TIMER1bit |
| 56 | #define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 |
| 57 | #define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 |
| 58 | #define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 |
| 59 | #endif |
| 60 | |
| 61 | #define LCD_X_RES 320 /* Horizontal Resolution */ |
| 62 | #define LCD_Y_RES 240 /* Vertical Resolution */ |
| 63 | #define DMA_BUS_SIZE 16 |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 64 | #define U_LINE 4 /* Blanking Lines */ |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 65 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 66 | |
| 67 | /* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD) |
| 68 | * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 |
| 69 | */ |
| 70 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 71 | |
| 72 | #define BFIN_LCD_NBR_PALETTE_ENTRIES 256 |
| 73 | |
| 74 | #define PPI_TX_MODE 0x2 |
| 75 | #define PPI_XFER_TYPE_11 0xC |
| 76 | #define PPI_PORT_CFG_01 0x10 |
| 77 | #define PPI_POLS_1 0x8000 |
| 78 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 79 | #define LQ035_INDEX 0x74 |
| 80 | #define LQ035_DATA 0x76 |
| 81 | |
| 82 | #define LQ035_DRIVER_OUTPUT_CTL 0x1 |
| 83 | #define LQ035_SHUT_CTL 0x11 |
| 84 | |
| 85 | #define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV) |
| 86 | #define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK) |
| 87 | |
| 88 | #define LQ035_SHUT (1 << 0) /* Shutdown */ |
| 89 | #define LQ035_ON (0 << 0) /* Shutdown */ |
| 90 | |
| 91 | struct bfin_lq035q1fb_info { |
| 92 | struct fb_info *fb; |
| 93 | struct device *dev; |
| 94 | struct spi_driver spidrv; |
| 95 | struct bfin_lq035q1fb_disp_info *disp_info; |
| 96 | unsigned char *fb_buffer; /* RGB Buffer */ |
| 97 | dma_addr_t dma_handle; |
| 98 | int lq035_open_cnt; |
| 99 | int irq; |
| 100 | spinlock_t lock; /* lock */ |
| 101 | u32 pseudo_pal[16]; |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 102 | |
| 103 | u32 lcd_bpp; |
| 104 | u32 h_actpix; |
| 105 | u32 h_period; |
| 106 | u32 h_pulse; |
| 107 | u32 h_start; |
| 108 | u32 v_lines; |
| 109 | u32 v_pulse; |
| 110 | u32 v_period; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | static int nocursor; |
| 114 | module_param(nocursor, int, 0644); |
| 115 | MODULE_PARM_DESC(nocursor, "cursor enable/disable"); |
| 116 | |
| 117 | struct spi_control { |
| 118 | unsigned short mode; |
| 119 | }; |
| 120 | |
| 121 | static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value) |
| 122 | { |
| 123 | int ret; |
| 124 | u8 regs[3] = { LQ035_INDEX, 0, 0 }; |
| 125 | u8 dat[3] = { LQ035_DATA, 0, 0 }; |
| 126 | |
| 127 | if (!spi) |
| 128 | return -ENODEV; |
| 129 | |
| 130 | regs[2] = reg; |
| 131 | dat[1] = value >> 8; |
| 132 | dat[2] = value & 0xFF; |
| 133 | |
| 134 | ret = spi_write(spi, regs, ARRAY_SIZE(regs)); |
| 135 | ret |= spi_write(spi, dat, ARRAY_SIZE(dat)); |
| 136 | return ret; |
| 137 | } |
| 138 | |
| 139 | static int __devinit lq035q1_spidev_probe(struct spi_device *spi) |
| 140 | { |
| 141 | int ret; |
| 142 | struct spi_control *ctl; |
| 143 | struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver, |
| 144 | struct bfin_lq035q1fb_info, |
| 145 | spidrv.driver); |
| 146 | |
| 147 | ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); |
| 148 | |
| 149 | if (!ctl) |
| 150 | return -ENOMEM; |
| 151 | |
| 152 | ctl->mode = (info->disp_info->mode & |
| 153 | LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT; |
| 154 | |
| 155 | ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); |
| 156 | ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); |
Julia Lawall | a8c908d | 2011-04-01 14:23:47 +0000 | [diff] [blame] | 157 | if (ret) { |
| 158 | kfree(ctl); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 159 | return ret; |
Julia Lawall | a8c908d | 2011-04-01 14:23:47 +0000 | [diff] [blame] | 160 | } |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 161 | |
| 162 | spi_set_drvdata(spi, ctl); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static int lq035q1_spidev_remove(struct spi_device *spi) |
| 168 | { |
| 169 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); |
| 170 | } |
| 171 | |
| 172 | #ifdef CONFIG_PM |
| 173 | static int lq035q1_spidev_suspend(struct spi_device *spi, pm_message_t state) |
| 174 | { |
| 175 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); |
| 176 | } |
| 177 | |
| 178 | static int lq035q1_spidev_resume(struct spi_device *spi) |
| 179 | { |
| 180 | int ret; |
| 181 | struct spi_control *ctl = spi_get_drvdata(spi); |
| 182 | |
| 183 | ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); |
| 184 | if (ret) |
| 185 | return ret; |
| 186 | |
| 187 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); |
| 188 | } |
| 189 | #else |
| 190 | # define lq035q1_spidev_suspend NULL |
| 191 | # define lq035q1_spidev_resume NULL |
| 192 | #endif |
| 193 | |
| 194 | /* Power down all displays on reboot, poweroff or halt */ |
| 195 | static void lq035q1_spidev_shutdown(struct spi_device *spi) |
| 196 | { |
| 197 | lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); |
| 198 | } |
| 199 | |
| 200 | static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg) |
| 201 | { |
| 202 | if (info->disp_info->use_bl) |
| 203 | gpio_set_value(info->disp_info->gpio_bl, arg); |
| 204 | |
| 205 | return 0; |
| 206 | } |
| 207 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 208 | static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi) |
| 209 | { |
| 210 | unsigned long clocks_per_pix, cpld_pipeline_delay_cor; |
| 211 | |
| 212 | /* |
| 213 | * Interface 16/18-bit TFT over an 8-bit wide PPI using a small |
| 214 | * Programmable Logic Device (CPLD) |
| 215 | * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 |
| 216 | */ |
| 217 | |
| 218 | switch (fbi->disp_info->ppi_mode) { |
| 219 | case USE_RGB565_16_BIT_PPI: |
| 220 | fbi->lcd_bpp = 16; |
| 221 | clocks_per_pix = 1; |
| 222 | cpld_pipeline_delay_cor = 0; |
| 223 | break; |
| 224 | case USE_RGB565_8_BIT_PPI: |
| 225 | fbi->lcd_bpp = 16; |
| 226 | clocks_per_pix = 2; |
| 227 | cpld_pipeline_delay_cor = 3; |
| 228 | break; |
| 229 | case USE_RGB888_8_BIT_PPI: |
| 230 | fbi->lcd_bpp = 24; |
| 231 | clocks_per_pix = 3; |
| 232 | cpld_pipeline_delay_cor = 5; |
| 233 | break; |
| 234 | default: |
| 235 | return -EINVAL; |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * HS and VS timing parameters (all in number of PPI clk ticks) |
| 240 | */ |
| 241 | |
| 242 | fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */ |
| 243 | fbi->h_period = (336 * clocks_per_pix); /* HS period */ |
| 244 | fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */ |
| 245 | fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */ |
| 246 | |
| 247 | fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */ |
| 248 | fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */ |
| 249 | fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */ |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 254 | static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi) |
| 255 | { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 256 | unsigned ppi_pmode; |
| 257 | |
| 258 | if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI) |
| 259 | ppi_pmode = DLEN_16; |
| 260 | else |
| 261 | ppi_pmode = (DLEN_8 | PACK_EN); |
| 262 | |
| 263 | bfin_write_PPI_DELAY(fbi->h_start); |
| 264 | bfin_write_PPI_COUNT(fbi->h_actpix - 1); |
| 265 | bfin_write_PPI_FRAME(fbi->v_lines); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 266 | |
| 267 | bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */ |
| 268 | PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ |
| 269 | PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 270 | ppi_pmode | /* 8/16 bit data length / PACK_EN? */ |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 271 | PPI_POLS_1); /* faling edge syncs POLS */ |
| 272 | } |
| 273 | |
| 274 | static inline void bfin_lq035q1_disable_ppi(void) |
| 275 | { |
| 276 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); |
| 277 | } |
| 278 | |
| 279 | static inline void bfin_lq035q1_enable_ppi(void) |
| 280 | { |
| 281 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); |
| 282 | } |
| 283 | |
| 284 | static void bfin_lq035q1_start_timers(void) |
| 285 | { |
| 286 | enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit); |
| 287 | } |
| 288 | |
| 289 | static void bfin_lq035q1_stop_timers(void) |
| 290 | { |
| 291 | disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit); |
| 292 | |
| 293 | set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN | |
| 294 | TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL | |
| 295 | TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF); |
| 296 | |
| 297 | } |
| 298 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 299 | static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi) |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 300 | { |
| 301 | |
| 302 | bfin_lq035q1_stop_timers(); |
| 303 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 304 | set_gptimer_period(TIMER_HSYNC_id, fbi->h_period); |
| 305 | set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 306 | set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | |
| 307 | TIMER_TIN_SEL | TIMER_CLK_SEL| |
| 308 | TIMER_EMU_RUN); |
| 309 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 310 | set_gptimer_period(TIMER_VSYNC_id, fbi->v_period); |
| 311 | set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 312 | set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | |
| 313 | TIMER_TIN_SEL | TIMER_CLK_SEL | |
| 314 | TIMER_EMU_RUN); |
| 315 | |
| 316 | } |
| 317 | |
| 318 | static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi) |
| 319 | { |
| 320 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 321 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 322 | set_dma_config(CH_PPI, |
| 323 | set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, |
| 324 | INTR_DISABLE, DIMENSION_2D, |
| 325 | DATA_SIZE_16, |
| 326 | DMA_NOSYNC_KEEP_DMA_BUF)); |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 327 | set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 328 | set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8); |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 329 | set_dma_y_count(CH_PPI, fbi->v_lines); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 330 | |
| 331 | set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8); |
| 332 | set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer); |
| 333 | |
| 334 | } |
| 335 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 336 | static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, |
| 337 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, |
| 338 | P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, |
| 339 | P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, |
| 340 | P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, |
| 341 | P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, |
| 342 | P_PPI0_D15, 0}; |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 343 | |
| 344 | static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 345 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, |
| 346 | P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, |
| 347 | P_PPI0_D6, P_PPI0_D7, 0}; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 348 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 349 | static inline void bfin_lq035q1_free_ports(unsigned ppi16) |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 350 | { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 351 | if (ppi16) |
| 352 | peripheral_free_list(ppi0_req_16); |
| 353 | else |
| 354 | peripheral_free_list(ppi0_req_8); |
| 355 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 356 | if (ANOMALY_05000400) |
| 357 | gpio_free(P_IDENT(P_PPI0_FS3)); |
| 358 | } |
| 359 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 360 | static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev, |
| 361 | unsigned ppi16) |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 362 | { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 363 | int ret; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 364 | /* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode: |
| 365 | * Drive PPI_FS3 Low |
| 366 | */ |
| 367 | if (ANOMALY_05000400) { |
| 368 | int ret = gpio_request(P_IDENT(P_PPI0_FS3), "PPI_FS3"); |
| 369 | if (ret) |
| 370 | return ret; |
| 371 | gpio_direction_output(P_IDENT(P_PPI0_FS3), 0); |
| 372 | } |
| 373 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 374 | if (ppi16) |
| 375 | ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME); |
| 376 | else |
| 377 | ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME); |
| 378 | |
| 379 | if (ret) { |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 380 | dev_err(&pdev->dev, "requesting peripherals failed\n"); |
| 381 | return -EFAULT; |
| 382 | } |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static int bfin_lq035q1_fb_open(struct fb_info *info, int user) |
| 388 | { |
| 389 | struct bfin_lq035q1fb_info *fbi = info->par; |
| 390 | |
| 391 | spin_lock(&fbi->lock); |
| 392 | fbi->lq035_open_cnt++; |
| 393 | |
| 394 | if (fbi->lq035_open_cnt <= 1) { |
| 395 | |
| 396 | bfin_lq035q1_disable_ppi(); |
| 397 | SSYNC(); |
| 398 | |
| 399 | bfin_lq035q1_config_dma(fbi); |
| 400 | bfin_lq035q1_config_ppi(fbi); |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 401 | bfin_lq035q1_init_timers(fbi); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 402 | |
| 403 | /* start dma */ |
| 404 | enable_dma(CH_PPI); |
| 405 | bfin_lq035q1_enable_ppi(); |
| 406 | bfin_lq035q1_start_timers(); |
| 407 | lq035q1_backlight(fbi, 1); |
| 408 | } |
| 409 | |
| 410 | spin_unlock(&fbi->lock); |
| 411 | |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | static int bfin_lq035q1_fb_release(struct fb_info *info, int user) |
| 416 | { |
| 417 | struct bfin_lq035q1fb_info *fbi = info->par; |
| 418 | |
| 419 | spin_lock(&fbi->lock); |
| 420 | |
| 421 | fbi->lq035_open_cnt--; |
| 422 | |
| 423 | if (fbi->lq035_open_cnt <= 0) { |
| 424 | lq035q1_backlight(fbi, 0); |
| 425 | bfin_lq035q1_disable_ppi(); |
| 426 | SSYNC(); |
| 427 | disable_dma(CH_PPI); |
| 428 | bfin_lq035q1_stop_timers(); |
| 429 | } |
| 430 | |
| 431 | spin_unlock(&fbi->lock); |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var, |
| 437 | struct fb_info *info) |
| 438 | { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 439 | struct bfin_lq035q1fb_info *fbi = info->par; |
| 440 | |
| 441 | if (var->bits_per_pixel == fbi->lcd_bpp) { |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 442 | var->red.offset = info->var.red.offset; |
| 443 | var->green.offset = info->var.green.offset; |
| 444 | var->blue.offset = info->var.blue.offset; |
| 445 | var->red.length = info->var.red.length; |
| 446 | var->green.length = info->var.green.length; |
| 447 | var->blue.length = info->var.blue.length; |
| 448 | var->transp.offset = 0; |
| 449 | var->transp.length = 0; |
| 450 | var->transp.msb_right = 0; |
| 451 | var->red.msb_right = 0; |
| 452 | var->green.msb_right = 0; |
| 453 | var->blue.msb_right = 0; |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 454 | } else { |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 455 | pr_debug("%s: depth not supported: %u BPP\n", __func__, |
| 456 | var->bits_per_pixel); |
| 457 | return -EINVAL; |
| 458 | } |
| 459 | |
| 460 | if (info->var.xres != var->xres || info->var.yres != var->yres || |
| 461 | info->var.xres_virtual != var->xres_virtual || |
| 462 | info->var.yres_virtual != var->yres_virtual) { |
| 463 | pr_debug("%s: Resolution not supported: X%u x Y%u \n", |
| 464 | __func__, var->xres, var->yres); |
| 465 | return -EINVAL; |
| 466 | } |
| 467 | |
| 468 | /* |
| 469 | * Memory limit |
| 470 | */ |
| 471 | |
| 472 | if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { |
| 473 | pr_debug("%s: Memory Limit requested yres_virtual = %u\n", |
| 474 | __func__, var->yres_virtual); |
| 475 | return -ENOMEM; |
| 476 | } |
| 477 | |
| 478 | |
| 479 | return 0; |
| 480 | } |
| 481 | |
| 482 | int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) |
| 483 | { |
| 484 | if (nocursor) |
| 485 | return 0; |
| 486 | else |
| 487 | return -EINVAL; /* just to force soft_cursor() call */ |
| 488 | } |
| 489 | |
| 490 | static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green, |
| 491 | u_int blue, u_int transp, |
| 492 | struct fb_info *info) |
| 493 | { |
| 494 | if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) |
| 495 | return -EINVAL; |
| 496 | |
| 497 | if (info->var.grayscale) { |
| 498 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ |
| 499 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; |
| 500 | } |
| 501 | |
| 502 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { |
| 503 | |
| 504 | u32 value; |
| 505 | /* Place color in the pseudopalette */ |
| 506 | if (regno > 16) |
| 507 | return -EINVAL; |
| 508 | |
| 509 | red >>= (16 - info->var.red.length); |
| 510 | green >>= (16 - info->var.green.length); |
| 511 | blue >>= (16 - info->var.blue.length); |
| 512 | |
| 513 | value = (red << info->var.red.offset) | |
| 514 | (green << info->var.green.offset) | |
| 515 | (blue << info->var.blue.offset); |
| 516 | value &= 0xFFFFFF; |
| 517 | |
| 518 | ((u32 *) (info->pseudo_palette))[regno] = value; |
| 519 | |
| 520 | } |
| 521 | |
| 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | static struct fb_ops bfin_lq035q1_fb_ops = { |
| 526 | .owner = THIS_MODULE, |
| 527 | .fb_open = bfin_lq035q1_fb_open, |
| 528 | .fb_release = bfin_lq035q1_fb_release, |
| 529 | .fb_check_var = bfin_lq035q1_fb_check_var, |
| 530 | .fb_fillrect = cfb_fillrect, |
| 531 | .fb_copyarea = cfb_copyarea, |
| 532 | .fb_imageblit = cfb_imageblit, |
| 533 | .fb_cursor = bfin_lq035q1_fb_cursor, |
| 534 | .fb_setcolreg = bfin_lq035q1_fb_setcolreg, |
| 535 | }; |
| 536 | |
| 537 | static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id) |
| 538 | { |
| 539 | /*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/ |
| 540 | |
| 541 | u16 status = bfin_read_PPI_STATUS(); |
| 542 | bfin_write_PPI_STATUS(-1); |
| 543 | |
| 544 | if (status) { |
| 545 | bfin_lq035q1_disable_ppi(); |
| 546 | disable_dma(CH_PPI); |
| 547 | |
| 548 | /* start dma */ |
| 549 | enable_dma(CH_PPI); |
| 550 | bfin_lq035q1_enable_ppi(); |
| 551 | bfin_write_PPI_STATUS(-1); |
| 552 | } |
| 553 | |
| 554 | return IRQ_HANDLED; |
| 555 | } |
| 556 | |
| 557 | static int __devinit bfin_lq035q1_probe(struct platform_device *pdev) |
| 558 | { |
| 559 | struct bfin_lq035q1fb_info *info; |
| 560 | struct fb_info *fbinfo; |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 561 | u32 active_video_mem_offset; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 562 | int ret; |
| 563 | |
| 564 | ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI"); |
| 565 | if (ret < 0) { |
| 566 | dev_err(&pdev->dev, "PPI DMA unavailable\n"); |
| 567 | goto out1; |
| 568 | } |
| 569 | |
| 570 | fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev); |
| 571 | if (!fbinfo) { |
| 572 | ret = -ENOMEM; |
| 573 | goto out2; |
| 574 | } |
| 575 | |
| 576 | info = fbinfo->par; |
| 577 | info->fb = fbinfo; |
| 578 | info->dev = &pdev->dev; |
| 579 | |
| 580 | info->disp_info = pdev->dev.platform_data; |
| 581 | |
| 582 | platform_set_drvdata(pdev, fbinfo); |
| 583 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 584 | ret = bfin_lq035q1_calc_timing(info); |
| 585 | if (ret < 0) { |
| 586 | dev_err(&pdev->dev, "Failed PPI Mode\n"); |
| 587 | goto out3; |
| 588 | } |
| 589 | |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 590 | strcpy(fbinfo->fix.id, DRIVER_NAME); |
| 591 | |
| 592 | fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; |
| 593 | fbinfo->fix.type_aux = 0; |
| 594 | fbinfo->fix.xpanstep = 0; |
| 595 | fbinfo->fix.ypanstep = 0; |
| 596 | fbinfo->fix.ywrapstep = 0; |
| 597 | fbinfo->fix.accel = FB_ACCEL_NONE; |
| 598 | fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; |
| 599 | |
| 600 | fbinfo->var.nonstd = 0; |
| 601 | fbinfo->var.activate = FB_ACTIVATE_NOW; |
| 602 | fbinfo->var.height = -1; |
| 603 | fbinfo->var.width = -1; |
| 604 | fbinfo->var.accel_flags = 0; |
| 605 | fbinfo->var.vmode = FB_VMODE_NONINTERLACED; |
| 606 | |
| 607 | fbinfo->var.xres = LCD_X_RES; |
| 608 | fbinfo->var.xres_virtual = LCD_X_RES; |
| 609 | fbinfo->var.yres = LCD_Y_RES; |
| 610 | fbinfo->var.yres_virtual = LCD_Y_RES; |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 611 | fbinfo->var.bits_per_pixel = info->lcd_bpp; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 612 | |
| 613 | if (info->disp_info->mode & LQ035_BGR) { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 614 | if (info->lcd_bpp == 24) { |
| 615 | fbinfo->var.red.offset = 0; |
| 616 | fbinfo->var.green.offset = 8; |
| 617 | fbinfo->var.blue.offset = 16; |
| 618 | } else { |
| 619 | fbinfo->var.red.offset = 0; |
| 620 | fbinfo->var.green.offset = 5; |
| 621 | fbinfo->var.blue.offset = 11; |
| 622 | } |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 623 | } else { |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 624 | if (info->lcd_bpp == 24) { |
| 625 | fbinfo->var.red.offset = 16; |
| 626 | fbinfo->var.green.offset = 8; |
| 627 | fbinfo->var.blue.offset = 0; |
| 628 | } else { |
| 629 | fbinfo->var.red.offset = 11; |
| 630 | fbinfo->var.green.offset = 5; |
| 631 | fbinfo->var.blue.offset = 0; |
| 632 | } |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | fbinfo->var.transp.offset = 0; |
| 636 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 637 | if (info->lcd_bpp == 24) { |
| 638 | fbinfo->var.red.length = 8; |
| 639 | fbinfo->var.green.length = 8; |
| 640 | fbinfo->var.blue.length = 8; |
| 641 | } else { |
| 642 | fbinfo->var.red.length = 5; |
| 643 | fbinfo->var.green.length = 6; |
| 644 | fbinfo->var.blue.length = 5; |
| 645 | } |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 646 | |
| 647 | fbinfo->var.transp.length = 0; |
| 648 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 649 | active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8)); |
| 650 | |
| 651 | fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8 |
| 652 | + active_video_mem_offset; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 653 | |
| 654 | fbinfo->fix.line_length = fbinfo->var.xres_virtual * |
| 655 | fbinfo->var.bits_per_pixel / 8; |
| 656 | |
| 657 | |
| 658 | fbinfo->fbops = &bfin_lq035q1_fb_ops; |
| 659 | fbinfo->flags = FBINFO_FLAG_DEFAULT; |
| 660 | |
| 661 | info->fb_buffer = |
| 662 | dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle, |
| 663 | GFP_KERNEL); |
| 664 | |
| 665 | if (NULL == info->fb_buffer) { |
| 666 | dev_err(&pdev->dev, "couldn't allocate dma buffer\n"); |
| 667 | ret = -ENOMEM; |
| 668 | goto out3; |
| 669 | } |
| 670 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 671 | fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset; |
| 672 | fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset; |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 673 | |
| 674 | fbinfo->fbops = &bfin_lq035q1_fb_ops; |
| 675 | |
| 676 | fbinfo->pseudo_palette = &info->pseudo_pal; |
| 677 | |
| 678 | ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0); |
| 679 | if (ret < 0) { |
| 680 | dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n", |
| 681 | BFIN_LCD_NBR_PALETTE_ENTRIES); |
| 682 | goto out4; |
| 683 | } |
| 684 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 685 | ret = bfin_lq035q1_request_ports(pdev, |
| 686 | info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 687 | if (ret) { |
| 688 | dev_err(&pdev->dev, "couldn't request gpio port\n"); |
| 689 | goto out6; |
| 690 | } |
| 691 | |
| 692 | info->irq = platform_get_irq(pdev, 0); |
| 693 | if (info->irq < 0) { |
| 694 | ret = -EINVAL; |
| 695 | goto out7; |
| 696 | } |
| 697 | |
| 698 | ret = request_irq(info->irq, bfin_lq035q1_irq_error, IRQF_DISABLED, |
| 699 | DRIVER_NAME" PPI ERROR", info); |
| 700 | if (ret < 0) { |
| 701 | dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n"); |
| 702 | goto out7; |
| 703 | } |
| 704 | |
| 705 | info->spidrv.driver.name = DRIVER_NAME"-spi"; |
| 706 | info->spidrv.probe = lq035q1_spidev_probe; |
| 707 | info->spidrv.remove = __devexit_p(lq035q1_spidev_remove); |
| 708 | info->spidrv.shutdown = lq035q1_spidev_shutdown; |
| 709 | info->spidrv.suspend = lq035q1_spidev_suspend; |
| 710 | info->spidrv.resume = lq035q1_spidev_resume; |
| 711 | |
| 712 | ret = spi_register_driver(&info->spidrv); |
| 713 | if (ret < 0) { |
| 714 | dev_err(&pdev->dev, "couldn't register SPI Interface\n"); |
| 715 | goto out8; |
| 716 | } |
| 717 | |
| 718 | if (info->disp_info->use_bl) { |
| 719 | ret = gpio_request(info->disp_info->gpio_bl, "LQ035 Backlight"); |
| 720 | |
| 721 | if (ret) { |
| 722 | dev_err(&pdev->dev, "failed to request GPIO %d\n", |
| 723 | info->disp_info->gpio_bl); |
| 724 | goto out9; |
| 725 | } |
| 726 | gpio_direction_output(info->disp_info->gpio_bl, 0); |
| 727 | } |
| 728 | |
| 729 | ret = register_framebuffer(fbinfo); |
| 730 | if (ret < 0) { |
| 731 | dev_err(&pdev->dev, "unable to register framebuffer\n"); |
| 732 | goto out10; |
| 733 | } |
| 734 | |
| 735 | dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n", |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 736 | LCD_X_RES, LCD_Y_RES, info->lcd_bpp); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 737 | |
| 738 | return 0; |
| 739 | |
| 740 | out10: |
| 741 | if (info->disp_info->use_bl) |
| 742 | gpio_free(info->disp_info->gpio_bl); |
| 743 | out9: |
| 744 | spi_unregister_driver(&info->spidrv); |
| 745 | out8: |
| 746 | free_irq(info->irq, info); |
| 747 | out7: |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 748 | bfin_lq035q1_free_ports(info->disp_info->ppi_mode == |
| 749 | USE_RGB565_16_BIT_PPI); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 750 | out6: |
| 751 | fb_dealloc_cmap(&fbinfo->cmap); |
| 752 | out4: |
| 753 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, |
| 754 | info->dma_handle); |
| 755 | out3: |
| 756 | framebuffer_release(fbinfo); |
| 757 | out2: |
| 758 | free_dma(CH_PPI); |
| 759 | out1: |
| 760 | platform_set_drvdata(pdev, NULL); |
| 761 | |
| 762 | return ret; |
| 763 | } |
| 764 | |
| 765 | static int __devexit bfin_lq035q1_remove(struct platform_device *pdev) |
| 766 | { |
| 767 | struct fb_info *fbinfo = platform_get_drvdata(pdev); |
| 768 | struct bfin_lq035q1fb_info *info = fbinfo->par; |
| 769 | |
| 770 | if (info->disp_info->use_bl) |
| 771 | gpio_free(info->disp_info->gpio_bl); |
| 772 | |
| 773 | spi_unregister_driver(&info->spidrv); |
| 774 | |
| 775 | unregister_framebuffer(fbinfo); |
| 776 | |
| 777 | free_dma(CH_PPI); |
| 778 | free_irq(info->irq, info); |
| 779 | |
| 780 | if (info->fb_buffer != NULL) |
| 781 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, |
| 782 | info->dma_handle); |
| 783 | |
| 784 | fb_dealloc_cmap(&fbinfo->cmap); |
| 785 | |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 786 | bfin_lq035q1_free_ports(info->disp_info->ppi_mode == |
| 787 | USE_RGB565_16_BIT_PPI); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 788 | |
| 789 | platform_set_drvdata(pdev, NULL); |
| 790 | framebuffer_release(fbinfo); |
| 791 | |
| 792 | dev_info(&pdev->dev, "unregistered LCD driver\n"); |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | #ifdef CONFIG_PM |
| 798 | static int bfin_lq035q1_suspend(struct device *dev) |
| 799 | { |
| 800 | struct fb_info *fbinfo = dev_get_drvdata(dev); |
| 801 | struct bfin_lq035q1fb_info *info = fbinfo->par; |
| 802 | |
| 803 | if (info->lq035_open_cnt) { |
| 804 | lq035q1_backlight(info, 0); |
| 805 | bfin_lq035q1_disable_ppi(); |
| 806 | SSYNC(); |
| 807 | disable_dma(CH_PPI); |
| 808 | bfin_lq035q1_stop_timers(); |
| 809 | bfin_write_PPI_STATUS(-1); |
| 810 | } |
| 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | static int bfin_lq035q1_resume(struct device *dev) |
| 816 | { |
| 817 | struct fb_info *fbinfo = dev_get_drvdata(dev); |
| 818 | struct bfin_lq035q1fb_info *info = fbinfo->par; |
| 819 | |
| 820 | if (info->lq035_open_cnt) { |
| 821 | bfin_lq035q1_disable_ppi(); |
| 822 | SSYNC(); |
| 823 | |
| 824 | bfin_lq035q1_config_dma(info); |
| 825 | bfin_lq035q1_config_ppi(info); |
Michael Hennerich | fbd65e0 | 2010-05-24 14:33:52 -0700 | [diff] [blame] | 826 | bfin_lq035q1_init_timers(info); |
Michael Hennerich | 9cfe4a9 | 2009-12-15 16:46:21 -0800 | [diff] [blame] | 827 | |
| 828 | /* start dma */ |
| 829 | enable_dma(CH_PPI); |
| 830 | bfin_lq035q1_enable_ppi(); |
| 831 | bfin_lq035q1_start_timers(); |
| 832 | lq035q1_backlight(info, 1); |
| 833 | } |
| 834 | |
| 835 | return 0; |
| 836 | } |
| 837 | |
| 838 | static struct dev_pm_ops bfin_lq035q1_dev_pm_ops = { |
| 839 | .suspend = bfin_lq035q1_suspend, |
| 840 | .resume = bfin_lq035q1_resume, |
| 841 | }; |
| 842 | #endif |
| 843 | |
| 844 | static struct platform_driver bfin_lq035q1_driver = { |
| 845 | .probe = bfin_lq035q1_probe, |
| 846 | .remove = __devexit_p(bfin_lq035q1_remove), |
| 847 | .driver = { |
| 848 | .name = DRIVER_NAME, |
| 849 | #ifdef CONFIG_PM |
| 850 | .pm = &bfin_lq035q1_dev_pm_ops, |
| 851 | #endif |
| 852 | }, |
| 853 | }; |
| 854 | |
| 855 | static int __init bfin_lq035q1_driver_init(void) |
| 856 | { |
| 857 | return platform_driver_register(&bfin_lq035q1_driver); |
| 858 | } |
| 859 | module_init(bfin_lq035q1_driver_init); |
| 860 | |
| 861 | static void __exit bfin_lq035q1_driver_cleanup(void) |
| 862 | { |
| 863 | platform_driver_unregister(&bfin_lq035q1_driver); |
| 864 | } |
| 865 | module_exit(bfin_lq035q1_driver_cleanup); |
| 866 | |
| 867 | MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); |
| 868 | MODULE_LICENSE("GPL"); |