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Sebastian Siewiordb11e472008-04-24 00:37:04 +02001#ifndef _ISP1760_HCD_H_
2#define _ISP1760_HCD_H_
3
Laurent Pincharte19c99e2015-01-21 00:55:56 +02004#include <linux/spinlock.h>
Laurent Pinchart10c73f02015-01-21 00:55:45 +02005
Laurent Pincharte19c99e2015-01-21 00:55:56 +02006struct gpio_desc;
7struct isp1760_qh;
8struct isp1760_qtd;
9struct resource;
10struct usb_hcd;
Sebastian Siewiordb11e472008-04-24 00:37:04 +020011
12/*
13 * 60kb divided in:
14 * - 32 blocks @ 256 bytes
15 * - 20 blocks @ 1024 bytes
16 * - 4 blocks @ 8192 bytes
17 */
18
19#define BLOCK_1_NUM 32
20#define BLOCK_2_NUM 20
21#define BLOCK_3_NUM 4
22
23#define BLOCK_1_SIZE 256
24#define BLOCK_2_SIZE 1024
25#define BLOCK_3_SIZE 8192
26#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
Arvid Brodina041d8e2011-02-26 22:04:40 +010027#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
28#define PAYLOAD_AREA_SIZE 0xf000
Sebastian Siewiordb11e472008-04-24 00:37:04 +020029
Laurent Pincharte19c99e2015-01-21 00:55:56 +020030/*
31 * Device flags that can vary from board to board. All of these
32 * indicate the most "atypical" case, so that a devflags of 0 is
33 * a sane default configuration.
34 */
35#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
36#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
37#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
38#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
39#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
40#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
41#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
42#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
Sebastian Siewiordb11e472008-04-24 00:37:04 +020043
Laurent Pincharte19c99e2015-01-21 00:55:56 +020044struct isp1760_slotinfo {
45 struct isp1760_qh *qh;
46 struct isp1760_qtd *qtd;
47 unsigned long timestamp;
48};
Sebastian Siewiordb11e472008-04-24 00:37:04 +020049
Laurent Pincharte19c99e2015-01-21 00:55:56 +020050/* chip memory management */
51struct isp1760_memory_chunk {
52 unsigned int start;
53 unsigned int size;
54 unsigned int free;
55};
Sebastian Siewiordb11e472008-04-24 00:37:04 +020056
Laurent Pincharte19c99e2015-01-21 00:55:56 +020057enum isp1760_queue_head_types {
58 QH_CONTROL,
59 QH_BULK,
60 QH_INTERRUPT,
61 QH_END
62};
63
64struct isp1760_hcd {
65 struct usb_hcd *hcd;
66
67 u32 hcs_params;
68 spinlock_t lock;
69 struct isp1760_slotinfo atl_slots[32];
70 int atl_done_map;
71 struct isp1760_slotinfo int_slots[32];
72 int int_done_map;
73 struct isp1760_memory_chunk memory_pool[BLOCKS];
74 struct list_head qh_list[QH_END];
75
76 /* periodic schedule support */
77#define DEFAULT_I_TDPS 1024
78 unsigned periodic_size;
79 unsigned i_thresh;
80 unsigned long reset_done;
81 unsigned long next_statechange;
82 unsigned int devflags;
83
84 struct gpio_desc *rst_gpio;
85};
86
87/* exports for if */
88int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
89 struct device *dev, unsigned int devflags);
90void isp1760_unregister(struct device *dev);
91
92int isp1760_init_kmem_once(void);
93void isp1760_deinit_kmem_cache(void);
Sebastian Siewiordb11e472008-04-24 00:37:04 +020094
Arvid Brodin71a9f9d2011-04-26 21:48:30 +020095#endif /* _ISP1760_HCD_H_ */