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gerrit-public.fairphone.software / kernel / msm-4.19 / e1a8d7e2ea7c971f750b1adf0e98c3c8ed002623 / . / arch / arm / mach-davinci / da850.c
blob: 332cf7fadb1f5eedea25da6e4ccea4d0f7cb5f79 [file] [log] [blame]
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame^]1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/map.h>
20
21#include <mach/clock.h>
22#include <mach/psc.h>
23#include <mach/mux.h>
24#include <mach/irqs.h>
25#include <mach/cputype.h>
26#include <mach/common.h>
27#include <mach/time.h>
28#include <mach/da8xx.h>
29
30#include "clock.h"
31#include "mux.h"
32
33#define DA850_PLL1_BASE 0x01e1a000
34#define DA850_TIMER64P2_BASE 0x01f0c000
35#define DA850_TIMER64P3_BASE 0x01f0d000
36
37#define DA850_REF_FREQ 24000000
38
39static struct pll_data pll0_data = {
40 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE,
42 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
43};
44
45static struct clk ref_clk = {
46 .name = "ref_clk",
47 .rate = DA850_REF_FREQ,
48};
49
50static struct clk pll0_clk = {
51 .name = "pll0",
52 .parent = &ref_clk,
53 .pll_data = &pll0_data,
54 .flags = CLK_PLL,
55};
56
57static struct clk pll0_aux_clk = {
58 .name = "pll0_aux_clk",
59 .parent = &pll0_clk,
60 .flags = CLK_PLL | PRE_PLL,
61};
62
63static struct clk pll0_sysclk2 = {
64 .name = "pll0_sysclk2",
65 .parent = &pll0_clk,
66 .flags = CLK_PLL,
67 .div_reg = PLLDIV2,
68};
69
70static struct clk pll0_sysclk3 = {
71 .name = "pll0_sysclk3",
72 .parent = &pll0_clk,
73 .flags = CLK_PLL,
74 .div_reg = PLLDIV3,
75};
76
77static struct clk pll0_sysclk4 = {
78 .name = "pll0_sysclk4",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV4,
82};
83
84static struct clk pll0_sysclk5 = {
85 .name = "pll0_sysclk5",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV5,
89};
90
91static struct clk pll0_sysclk6 = {
92 .name = "pll0_sysclk6",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV6,
96};
97
98static struct clk pll0_sysclk7 = {
99 .name = "pll0_sysclk7",
100 .parent = &pll0_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV7,
103};
104
105static struct pll_data pll1_data = {
106 .num = 2,
107 .phys_base = DA850_PLL1_BASE,
108 .flags = PLL_HAS_POSTDIV,
109};
110
111static struct clk pll1_clk = {
112 .name = "pll1",
113 .parent = &ref_clk,
114 .pll_data = &pll1_data,
115 .flags = CLK_PLL,
116};
117
118static struct clk pll1_aux_clk = {
119 .name = "pll1_aux_clk",
120 .parent = &pll1_clk,
121 .flags = CLK_PLL | PRE_PLL,
122};
123
124static struct clk pll1_sysclk2 = {
125 .name = "pll1_sysclk2",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV2,
129};
130
131static struct clk pll1_sysclk3 = {
132 .name = "pll1_sysclk3",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL,
135 .div_reg = PLLDIV3,
136};
137
138static struct clk pll1_sysclk4 = {
139 .name = "pll1_sysclk4",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL,
142 .div_reg = PLLDIV4,
143};
144
145static struct clk pll1_sysclk5 = {
146 .name = "pll1_sysclk5",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL,
149 .div_reg = PLLDIV5,
150};
151
152static struct clk pll1_sysclk6 = {
153 .name = "pll0_sysclk6",
154 .parent = &pll0_clk,
155 .flags = CLK_PLL,
156 .div_reg = PLLDIV6,
157};
158
159static struct clk pll1_sysclk7 = {
160 .name = "pll1_sysclk7",
161 .parent = &pll1_clk,
162 .flags = CLK_PLL,
163 .div_reg = PLLDIV7,
164};
165
166static struct clk i2c0_clk = {
167 .name = "i2c0",
168 .parent = &pll0_aux_clk,
169};
170
171static struct clk timerp64_0_clk = {
172 .name = "timer0",
173 .parent = &pll0_aux_clk,
174};
175
176static struct clk timerp64_1_clk = {
177 .name = "timer1",
178 .parent = &pll0_aux_clk,
179};
180
181static struct clk arm_rom_clk = {
182 .name = "arm_rom",
183 .parent = &pll0_sysclk2,
184 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
185 .flags = ALWAYS_ENABLED,
186};
187
188static struct clk tpcc0_clk = {
189 .name = "tpcc0",
190 .parent = &pll0_sysclk2,
191 .lpsc = DA8XX_LPSC0_TPCC,
192 .flags = ALWAYS_ENABLED | CLK_PSC,
193};
194
195static struct clk tptc0_clk = {
196 .name = "tptc0",
197 .parent = &pll0_sysclk2,
198 .lpsc = DA8XX_LPSC0_TPTC0,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk tptc1_clk = {
203 .name = "tptc1",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_TPTC1,
206 .flags = ALWAYS_ENABLED,
207};
208
209static struct clk tpcc1_clk = {
210 .name = "tpcc1",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA850_LPSC1_TPCC1,
213 .flags = CLK_PSC | ALWAYS_ENABLED,
214 .psc_ctlr = 1,
215};
216
217static struct clk tptc2_clk = {
218 .name = "tptc2",
219 .parent = &pll0_sysclk2,
220 .lpsc = DA850_LPSC1_TPTC2,
221 .flags = ALWAYS_ENABLED,
222 .psc_ctlr = 1,
223};
224
225static struct clk uart0_clk = {
226 .name = "uart0",
227 .parent = &pll0_sysclk2,
228 .lpsc = DA8XX_LPSC0_UART0,
229};
230
231static struct clk uart1_clk = {
232 .name = "uart1",
233 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1,
235 .psc_ctlr = 1,
236};
237
238static struct clk uart2_clk = {
239 .name = "uart2",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2,
242 .psc_ctlr = 1,
243};
244
245static struct clk aintc_clk = {
246 .name = "aintc",
247 .parent = &pll0_sysclk4,
248 .lpsc = DA8XX_LPSC0_AINTC,
249 .flags = ALWAYS_ENABLED,
250};
251
252static struct clk gpio_clk = {
253 .name = "gpio",
254 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC1_GPIO,
256 .psc_ctlr = 1,
257};
258
259static struct clk i2c1_clk = {
260 .name = "i2c1",
261 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_I2C,
263 .psc_ctlr = 1,
264};
265
266static struct clk emif3_clk = {
267 .name = "emif3",
268 .parent = &pll0_sysclk5,
269 .lpsc = DA8XX_LPSC1_EMIF3C,
270 .flags = ALWAYS_ENABLED,
271 .psc_ctlr = 1,
272};
273
274static struct clk arm_clk = {
275 .name = "arm",
276 .parent = &pll0_sysclk6,
277 .lpsc = DA8XX_LPSC0_ARM,
278 .flags = ALWAYS_ENABLED,
279};
280
281static struct clk rmii_clk = {
282 .name = "rmii",
283 .parent = &pll0_sysclk7,
284};
285
286static struct davinci_clk da850_clks[] = {
287 CLK(NULL, "ref", &ref_clk),
288 CLK(NULL, "pll0", &pll0_clk),
289 CLK(NULL, "pll0_aux", &pll0_aux_clk),
290 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
291 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
292 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
293 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
294 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
295 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
296 CLK(NULL, "pll1", &pll1_clk),
297 CLK(NULL, "pll1_aux", &pll1_aux_clk),
298 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
299 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
300 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
301 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
302 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
303 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
304 CLK("i2c_davinci.1", NULL, &i2c0_clk),
305 CLK(NULL, "timer0", &timerp64_0_clk),
306 CLK("watchdog", NULL, &timerp64_1_clk),
307 CLK(NULL, "arm_rom", &arm_rom_clk),
308 CLK(NULL, "tpcc0", &tpcc0_clk),
309 CLK(NULL, "tptc0", &tptc0_clk),
310 CLK(NULL, "tptc1", &tptc1_clk),
311 CLK(NULL, "tpcc1", &tpcc1_clk),
312 CLK(NULL, "tptc2", &tptc2_clk),
313 CLK(NULL, "uart0", &uart0_clk),
314 CLK(NULL, "uart1", &uart1_clk),
315 CLK(NULL, "uart2", &uart2_clk),
316 CLK(NULL, "aintc", &aintc_clk),
317 CLK(NULL, "gpio", &gpio_clk),
318 CLK("i2c_davinci.2", NULL, &i2c1_clk),
319 CLK(NULL, "emif3", &emif3_clk),
320 CLK(NULL, "arm", &arm_clk),
321 CLK(NULL, "rmii", &rmii_clk),
322 CLK(NULL, NULL, NULL),
323};
324
325/*
326 * Device specific mux setup
327 *
328 * soc description mux mode mode mux dbg
329 * reg offset mask mode
330 */
331static const struct mux_config da850_pins[] = {
332#ifdef CONFIG_DAVINCI_MUX
333 /* UART0 function */
334 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
335 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
336 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
337 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
338 /* UART1 function */
339 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
340 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
341 /* UART2 function */
342 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
343 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
344 /* I2C1 function */
345 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
346 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
347 /* I2C0 function */
348 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
349 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
350#endif
351};
352
353const short da850_uart0_pins[] __initdata = {
354 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
355 -1
356};
357
358const short da850_uart1_pins[] __initdata = {
359 DA850_UART1_RXD, DA850_UART1_TXD,
360 -1
361};
362
363const short da850_uart2_pins[] __initdata = {
364 DA850_UART2_RXD, DA850_UART2_TXD,
365 -1
366};
367
368const short da850_i2c0_pins[] __initdata = {
369 DA850_I2C0_SDA, DA850_I2C0_SCL,
370 -1
371};
372
373const short da850_i2c1_pins[] __initdata = {
374 DA850_I2C1_SCL, DA850_I2C1_SDA,
375 -1
376};
377
378/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
379static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
380 [IRQ_DA8XX_COMMTX] = 7,
381 [IRQ_DA8XX_COMMRX] = 7,
382 [IRQ_DA8XX_NINT] = 7,
383 [IRQ_DA8XX_EVTOUT0] = 7,
384 [IRQ_DA8XX_EVTOUT1] = 7,
385 [IRQ_DA8XX_EVTOUT2] = 7,
386 [IRQ_DA8XX_EVTOUT3] = 7,
387 [IRQ_DA8XX_EVTOUT4] = 7,
388 [IRQ_DA8XX_EVTOUT5] = 7,
389 [IRQ_DA8XX_EVTOUT6] = 7,
390 [IRQ_DA8XX_EVTOUT6] = 7,
391 [IRQ_DA8XX_EVTOUT7] = 7,
392 [IRQ_DA8XX_CCINT0] = 7,
393 [IRQ_DA8XX_CCERRINT] = 7,
394 [IRQ_DA8XX_TCERRINT0] = 7,
395 [IRQ_DA8XX_AEMIFINT] = 7,
396 [IRQ_DA8XX_I2CINT0] = 7,
397 [IRQ_DA8XX_MMCSDINT0] = 7,
398 [IRQ_DA8XX_MMCSDINT1] = 7,
399 [IRQ_DA8XX_ALLINT0] = 7,
400 [IRQ_DA8XX_RTC] = 7,
401 [IRQ_DA8XX_SPINT0] = 7,
402 [IRQ_DA8XX_TINT12_0] = 7,
403 [IRQ_DA8XX_TINT34_0] = 7,
404 [IRQ_DA8XX_TINT12_1] = 7,
405 [IRQ_DA8XX_TINT34_1] = 7,
406 [IRQ_DA8XX_UARTINT0] = 7,
407 [IRQ_DA8XX_KEYMGRINT] = 7,
408 [IRQ_DA8XX_SECINT] = 7,
409 [IRQ_DA8XX_SECKEYERR] = 7,
410 [IRQ_DA850_MPUADDRERR0] = 7,
411 [IRQ_DA850_MPUPROTERR0] = 7,
412 [IRQ_DA850_IOPUADDRERR0] = 7,
413 [IRQ_DA850_IOPUPROTERR0] = 7,
414 [IRQ_DA850_IOPUADDRERR1] = 7,
415 [IRQ_DA850_IOPUPROTERR1] = 7,
416 [IRQ_DA850_IOPUADDRERR2] = 7,
417 [IRQ_DA850_IOPUPROTERR2] = 7,
418 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
419 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
420 [IRQ_DA850_MPUADDRERR1] = 7,
421 [IRQ_DA850_MPUPROTERR1] = 7,
422 [IRQ_DA850_IOPUADDRERR3] = 7,
423 [IRQ_DA850_IOPUPROTERR3] = 7,
424 [IRQ_DA850_IOPUADDRERR4] = 7,
425 [IRQ_DA850_IOPUPROTERR4] = 7,
426 [IRQ_DA850_IOPUADDRERR5] = 7,
427 [IRQ_DA850_IOPUPROTERR5] = 7,
428 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
429 [IRQ_DA8XX_CHIPINT0] = 7,
430 [IRQ_DA8XX_CHIPINT1] = 7,
431 [IRQ_DA8XX_CHIPINT2] = 7,
432 [IRQ_DA8XX_CHIPINT3] = 7,
433 [IRQ_DA8XX_TCERRINT1] = 7,
434 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
435 [IRQ_DA8XX_C0_RX_PULSE] = 7,
436 [IRQ_DA8XX_C0_TX_PULSE] = 7,
437 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
438 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
439 [IRQ_DA8XX_C1_RX_PULSE] = 7,
440 [IRQ_DA8XX_C1_TX_PULSE] = 7,
441 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
442 [IRQ_DA8XX_MEMERR] = 7,
443 [IRQ_DA8XX_GPIO0] = 7,
444 [IRQ_DA8XX_GPIO1] = 7,
445 [IRQ_DA8XX_GPIO2] = 7,
446 [IRQ_DA8XX_GPIO3] = 7,
447 [IRQ_DA8XX_GPIO4] = 7,
448 [IRQ_DA8XX_GPIO5] = 7,
449 [IRQ_DA8XX_GPIO6] = 7,
450 [IRQ_DA8XX_GPIO7] = 7,
451 [IRQ_DA8XX_GPIO8] = 7,
452 [IRQ_DA8XX_I2CINT1] = 7,
453 [IRQ_DA8XX_LCDINT] = 7,
454 [IRQ_DA8XX_UARTINT1] = 7,
455 [IRQ_DA8XX_MCASPINT] = 7,
456 [IRQ_DA8XX_ALLINT1] = 7,
457 [IRQ_DA8XX_SPINT1] = 7,
458 [IRQ_DA8XX_UHPI_INT1] = 7,
459 [IRQ_DA8XX_USB_INT] = 7,
460 [IRQ_DA8XX_IRQN] = 7,
461 [IRQ_DA8XX_RWAKEUP] = 7,
462 [IRQ_DA8XX_UARTINT2] = 7,
463 [IRQ_DA8XX_DFTSSINT] = 7,
464 [IRQ_DA8XX_EHRPWM0] = 7,
465 [IRQ_DA8XX_EHRPWM0TZ] = 7,
466 [IRQ_DA8XX_EHRPWM1] = 7,
467 [IRQ_DA8XX_EHRPWM1TZ] = 7,
468 [IRQ_DA850_SATAINT] = 7,
469 [IRQ_DA850_TINT12_2] = 7,
470 [IRQ_DA850_TINT34_2] = 7,
471 [IRQ_DA850_TINTALL_2] = 7,
472 [IRQ_DA8XX_ECAP0] = 7,
473 [IRQ_DA8XX_ECAP1] = 7,
474 [IRQ_DA8XX_ECAP2] = 7,
475 [IRQ_DA850_MMCSDINT0_1] = 7,
476 [IRQ_DA850_MMCSDINT1_1] = 7,
477 [IRQ_DA850_T12CMPINT0_2] = 7,
478 [IRQ_DA850_T12CMPINT1_2] = 7,
479 [IRQ_DA850_T12CMPINT2_2] = 7,
480 [IRQ_DA850_T12CMPINT3_2] = 7,
481 [IRQ_DA850_T12CMPINT4_2] = 7,
482 [IRQ_DA850_T12CMPINT5_2] = 7,
483 [IRQ_DA850_T12CMPINT6_2] = 7,
484 [IRQ_DA850_T12CMPINT7_2] = 7,
485 [IRQ_DA850_T12CMPINT0_3] = 7,
486 [IRQ_DA850_T12CMPINT1_3] = 7,
487 [IRQ_DA850_T12CMPINT2_3] = 7,
488 [IRQ_DA850_T12CMPINT3_3] = 7,
489 [IRQ_DA850_T12CMPINT4_3] = 7,
490 [IRQ_DA850_T12CMPINT5_3] = 7,
491 [IRQ_DA850_T12CMPINT6_3] = 7,
492 [IRQ_DA850_T12CMPINT7_3] = 7,
493 [IRQ_DA850_RPIINT] = 7,
494 [IRQ_DA850_VPIFINT] = 7,
495 [IRQ_DA850_CCINT1] = 7,
496 [IRQ_DA850_CCERRINT1] = 7,
497 [IRQ_DA850_TCERRINT2] = 7,
498 [IRQ_DA850_TINT12_3] = 7,
499 [IRQ_DA850_TINT34_3] = 7,
500 [IRQ_DA850_TINTALL_3] = 7,
501 [IRQ_DA850_MCBSP0RINT] = 7,
502 [IRQ_DA850_MCBSP0XINT] = 7,
503 [IRQ_DA850_MCBSP1RINT] = 7,
504 [IRQ_DA850_MCBSP1XINT] = 7,
505 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
506};
507
508static struct map_desc da850_io_desc[] = {
509 {
510 .virtual = IO_VIRT,
511 .pfn = __phys_to_pfn(IO_PHYS),
512 .length = IO_SIZE,
513 .type = MT_DEVICE
514 },
515 {
516 .virtual = DA8XX_CP_INTC_VIRT,
517 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
518 .length = DA8XX_CP_INTC_SIZE,
519 .type = MT_DEVICE
520 },
521};
522
523static void __iomem *da850_psc_bases[] = {
524 IO_ADDRESS(DA8XX_PSC0_BASE),
525 IO_ADDRESS(DA8XX_PSC1_BASE),
526};
527
528/* Contents of JTAG ID register used to identify exact cpu type */
529static struct davinci_id da850_ids[] = {
530 {
531 .variant = 0x0,
532 .part_no = 0xb7d1,
533 .manufacturer = 0x017, /* 0x02f >> 1 */
534 .cpu_id = DAVINCI_CPU_ID_DA850,
535 .name = "da850/omap-l138",
536 },
537};
538
539static struct davinci_timer_instance da850_timer_instance[4] = {
540 {
541 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
542 .bottom_irq = IRQ_DA8XX_TINT12_0,
543 .top_irq = IRQ_DA8XX_TINT34_0,
544 },
545 {
546 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
547 .bottom_irq = IRQ_DA8XX_TINT12_1,
548 .top_irq = IRQ_DA8XX_TINT34_1,
549 },
550 {
551 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
552 .bottom_irq = IRQ_DA850_TINT12_2,
553 .top_irq = IRQ_DA850_TINT34_2,
554 },
555 {
556 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
557 .bottom_irq = IRQ_DA850_TINT12_3,
558 .top_irq = IRQ_DA850_TINT34_3,
559 },
560};
561
562/*
563 * T0_BOT: Timer 0, bottom : Used for clock_event
564 * T0_TOP: Timer 0, top : Used for clocksource
565 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
566 */
567static struct davinci_timer_info da850_timer_info = {
568 .timers = da850_timer_instance,
569 .clockevent_id = T0_BOT,
570 .clocksource_id = T0_TOP,
571};
572
573static struct davinci_soc_info davinci_soc_info_da850 = {
574 .io_desc = da850_io_desc,
575 .io_desc_num = ARRAY_SIZE(da850_io_desc),
576 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
577 .ids = da850_ids,
578 .ids_num = ARRAY_SIZE(da850_ids),
579 .cpu_clks = da850_clks,
580 .psc_bases = da850_psc_bases,
581 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
582 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
583 .pinmux_pins = da850_pins,
584 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
585 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
586 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
587 .intc_irq_prios = da850_default_priorities,
588 .intc_irq_num = DA850_N_CP_INTC_IRQ,
589 .timer_info = &da850_timer_info,
590 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
591 .gpio_num = 128,
592 .gpio_irq = IRQ_DA8XX_GPIO0,
593 .serial_dev = &da8xx_serial_device,
594 .emac_pdata = &da8xx_emac_pdata,
595};
596
597void __init da850_init(void)
598{
599 davinci_common_init(&davinci_soc_info_da850);
600}