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Heiko Stuebnerd63dc052013-06-02 23:09:41 +02001/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
Heiko Stuebner5218c6b2015-03-06 19:04:00 +01005 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
Heiko Stuebnerd63dc052013-06-02 23:09:41 +02009 *
Heiko Stuebner5218c6b2015-03-06 19:04:00 +010010 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020042 */
43
44#include <dt-bindings/gpio/gpio.h>
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020045#include <dt-bindings/pinctrl/rockchip.h>
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +020046#include <dt-bindings/clock/rk3066a-cru.h>
Heiko Stuebnerf75efdd2013-09-29 13:25:08 +020047#include "rk3xxx.dtsi"
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020048
49/ {
50 compatible = "rockchip,rk3066a";
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020051
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
Heiko Stübner26ab69c2014-03-27 01:06:32 +010055 enable-method = "rockchip,rk3066-smp";
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020056
Heiko Stuebnerbe8a77c2014-09-13 00:34:29 +020057 cpu0: cpu@0 {
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020058 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
61 reg = <0x0>;
Heiko Stuebnerbe8a77c2014-09-13 00:34:29 +020062 operating-points = <
63 /* kHz uV */
64 1008000 1075000
65 816000 1025000
66 600000 1025000
67 504000 1000000
68 312000 975000
69 >;
70 clock-latency = <40000>;
71 clocks = <&cru ARMCLK>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020072 };
73 cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a9";
76 next-level-cache = <&L2>;
77 reg = <0x1>;
78 };
79 };
80
Heiko Stuebnerc3030d32014-07-26 18:44:35 +020081 sram: sram@10080000 {
82 compatible = "mmio-sram";
83 reg = <0x10080000 0x10000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges = <0 0x10080000 0x10000>;
87
88 smp-sram@0 {
89 compatible = "rockchip,rk3066-smp-sram";
90 reg = <0x0 0x50>;
91 };
92 };
93
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +020094 i2s0: i2s@10118000 {
95 compatible = "rockchip,rk3066-i2s";
96 reg = <0x10118000 0x2000>;
97 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&i2s0_bus>;
102 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
103 dma-names = "tx", "rx";
104 clock-names = "i2s_hclk", "i2s_clk";
105 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
Sugar Zhange2416572015-11-10 15:32:09 +0800106 rockchip,playback-channels = <8>;
107 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200108 status = "disabled";
109 };
110
111 i2s1: i2s@1011a000 {
112 compatible = "rockchip,rk3066-i2s";
113 reg = <0x1011a000 0x2000>;
114 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&i2s1_bus>;
119 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
120 dma-names = "tx", "rx";
121 clock-names = "i2s_hclk", "i2s_clk";
122 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
Sugar Zhange2416572015-11-10 15:32:09 +0800123 rockchip,playback-channels = <2>;
124 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200125 status = "disabled";
126 };
127
128 i2s2: i2s@1011c000 {
129 compatible = "rockchip,rk3066-i2s";
130 reg = <0x1011c000 0x2000>;
131 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&i2s2_bus>;
136 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
137 dma-names = "tx", "rx";
138 clock-names = "i2s_hclk", "i2s_clk";
139 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
Sugar Zhange2416572015-11-10 15:32:09 +0800140 rockchip,playback-channels = <2>;
141 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200142 status = "disabled";
143 };
144
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200145 cru: clock-controller@20000000 {
146 compatible = "rockchip,rk3066a-cru";
147 reg = <0x20000000 0x1000>;
148 rockchip,grf = <&grf>;
149
150 #clock-cells = <1>;
151 #reset-cells = <1>;
152 };
153
Heiko Stuebnerff84b902014-07-26 23:28:03 +0200154 timer@2000e000 {
155 compatible = "snps,dw-apb-timer-osc";
156 reg = <0x2000e000 0x100>;
157 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
159 clock-names = "timer", "pclk";
160 };
161
162 timer@20038000 {
163 compatible = "snps,dw-apb-timer-osc";
164 reg = <0x20038000 0x100>;
165 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
167 clock-names = "timer", "pclk";
168 };
169
170 timer@2003a000 {
171 compatible = "snps,dw-apb-timer-osc";
172 reg = <0x2003a000 0x100>;
173 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
175 clock-names = "timer", "pclk";
176 };
177
Heiko Stuebner760bb972015-08-01 20:28:36 +0200178 usbphy: phy {
179 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
180 rockchip,grf = <&grf>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 status = "disabled";
184
185 usbphy0: usb-phy0 {
186 #phy-cells = <0>;
187 reg = <0x17c>;
188 clocks = <&cru SCLK_OTGPHY0>;
189 clock-names = "phyclk";
190 };
191
192 usbphy1: usb-phy1 {
193 #phy-cells = <0>;
194 reg = <0x188>;
195 clocks = <&cru SCLK_OTGPHY1>;
196 clock-names = "phyclk";
197 };
198 };
199
Heiko Stuebner6e4b3b42014-07-22 22:56:16 +0200200 pinctrl: pinctrl {
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200201 compatible = "rockchip,rk3066a-pinctrl";
202 rockchip,grf = <&grf>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges;
206
207 gpio0: gpio0@20034000 {
208 compatible = "rockchip,gpio-bank";
209 reg = <0x20034000 0x100>;
210 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&cru PCLK_GPIO0>;
212
213 gpio-controller;
214 #gpio-cells = <2>;
215
216 interrupt-controller;
217 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200218 };
219
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200220 gpio1: gpio1@2003c000 {
221 compatible = "rockchip,gpio-bank";
222 reg = <0x2003c000 0x100>;
223 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru PCLK_GPIO1>;
225
226 gpio-controller;
227 #gpio-cells = <2>;
228
229 interrupt-controller;
230 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200231 };
232
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200233 gpio2: gpio2@2003e000 {
234 compatible = "rockchip,gpio-bank";
235 reg = <0x2003e000 0x100>;
236 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cru PCLK_GPIO2>;
238
239 gpio-controller;
240 #gpio-cells = <2>;
241
242 interrupt-controller;
243 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200244 };
245
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200246 gpio3: gpio3@20080000 {
247 compatible = "rockchip,gpio-bank";
248 reg = <0x20080000 0x100>;
249 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cru PCLK_GPIO3>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200251
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200252 gpio-controller;
253 #gpio-cells = <2>;
254
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 };
258
259 gpio4: gpio4@20084000 {
260 compatible = "rockchip,gpio-bank";
261 reg = <0x20084000 0x100>;
262 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&cru PCLK_GPIO4>;
264
265 gpio-controller;
266 #gpio-cells = <2>;
267
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 };
271
272 gpio6: gpio6@2000a000 {
273 compatible = "rockchip,gpio-bank";
274 reg = <0x2000a000 0x100>;
275 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&cru PCLK_GPIO6>;
277
278 gpio-controller;
279 #gpio-cells = <2>;
280
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
284
285 pcfg_pull_default: pcfg_pull_default {
286 bias-pull-pin-default;
287 };
288
289 pcfg_pull_none: pcfg_pull_none {
290 bias-disable;
291 };
292
Romain Perier89f66872014-11-02 10:20:00 +0000293 emac {
294 emac_xfer: emac-xfer {
295 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
296 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
297 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
298 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
299 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
300 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
301 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
302 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
303 };
304
305 emac_mdio: emac-mdio {
306 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
307 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
308 };
309 };
310
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200311 emmc {
312 emmc_clk: emmc-clk {
313 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
314 };
315
316 emmc_cmd: emmc-cmd {
317 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
318 };
319
320 emmc_rst: emmc-rst {
321 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
322 };
323
324 /*
325 * The data pins are shared between nandc and emmc and
326 * not accessible through pinctrl. Also they should've
327 * been already set correctly by firmware, as
328 * flash/emmc is the boot-device.
329 */
330 };
331
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200332 i2c0 {
333 i2c0_xfer: i2c0-xfer {
334 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
335 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
336 };
337 };
338
339 i2c1 {
340 i2c1_xfer: i2c1-xfer {
341 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
342 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
343 };
344 };
345
346 i2c2 {
347 i2c2_xfer: i2c2-xfer {
348 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
349 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
350 };
351 };
352
353 i2c3 {
354 i2c3_xfer: i2c3-xfer {
355 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
356 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
357 };
358 };
359
360 i2c4 {
361 i2c4_xfer: i2c4-xfer {
362 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
363 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
364 };
365 };
366
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200367 pwm0 {
368 pwm0_out: pwm0-out {
369 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
370 };
371 };
372
373 pwm1 {
374 pwm1_out: pwm1-out {
375 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
376 };
377 };
378
379 pwm2 {
380 pwm2_out: pwm2-out {
381 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
382 };
383 };
384
385 pwm3 {
386 pwm3_out: pwm3-out {
387 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
388 };
389 };
390
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200391 spi0 {
392 spi0_clk: spi0-clk {
393 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
394 };
395 spi0_cs0: spi0-cs0 {
396 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
397 };
398 spi0_tx: spi0-tx {
399 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
400 };
401 spi0_rx: spi0-rx {
402 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
403 };
404 spi0_cs1: spi0-cs1 {
405 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
406 };
407 };
408
409 spi1 {
410 spi1_clk: spi1-clk {
411 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
412 };
413 spi1_cs0: spi1-cs0 {
414 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
415 };
416 spi1_rx: spi1-rx {
417 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
418 };
419 spi1_tx: spi1-tx {
420 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
421 };
422 spi1_cs1: spi1-cs1 {
423 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
424 };
425 };
426
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200427 uart0 {
428 uart0_xfer: uart0-xfer {
429 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
430 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
431 };
432
433 uart0_cts: uart0-cts {
434 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
435 };
436
437 uart0_rts: uart0-rts {
438 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200439 };
440 };
441
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200442 uart1 {
443 uart1_xfer: uart1-xfer {
444 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
445 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
446 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200447
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200448 uart1_cts: uart1-cts {
449 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
450 };
451
452 uart1_rts: uart1-rts {
453 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
454 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200455 };
456
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200457 uart2 {
458 uart2_xfer: uart2-xfer {
459 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
460 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
461 };
462 /* no rts / cts for uart2 */
463 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200464
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200465 uart3 {
466 uart3_xfer: uart3-xfer {
467 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
468 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200469 };
470
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200471 uart3_cts: uart3-cts {
472 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200473 };
474
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200475 uart3_rts: uart3-rts {
476 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
477 };
478 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200479
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200480 sd0 {
481 sd0_clk: sd0-clk {
482 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200483 };
484
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200485 sd0_cmd: sd0-cmd {
486 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200487 };
488
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200489 sd0_cd: sd0-cd {
490 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200491 };
492
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200493 sd0_wp: sd0-wp {
494 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200495 };
496
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200497 sd0_bus1: sd0-bus-width1 {
498 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200499 };
500
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200501 sd0_bus4: sd0-bus-width4 {
502 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
503 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
504 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
505 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
506 };
507 };
508
509 sd1 {
510 sd1_clk: sd1-clk {
511 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200512 };
513
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200514 sd1_cmd: sd1-cmd {
515 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200516 };
517
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200518 sd1_cd: sd1-cd {
519 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200520 };
521
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200522 sd1_wp: sd1-wp {
523 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200524 };
525
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200526 sd1_bus1: sd1-bus-width1 {
527 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200528 };
529
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200530 sd1_bus4: sd1-bus-width4 {
531 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
532 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
533 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
534 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200535 };
536 };
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200537
538 i2s0 {
539 i2s0_bus: i2s0-bus {
540 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
541 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
542 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
543 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
544 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
545 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
546 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
547 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
548 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
549 };
550 };
551
552 i2s1 {
553 i2s1_bus: i2s1-bus {
554 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
555 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
556 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
557 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
558 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
559 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
560 };
561 };
562
563 i2s2 {
564 i2s2_bus: i2s2-bus {
565 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
566 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
567 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
568 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
569 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
570 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
571 };
572 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200573 };
574};
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200575
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200576&i2c0 {
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c0_xfer>;
579};
580
581&i2c1 {
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2c1_xfer>;
584};
585
586&i2c2 {
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c2_xfer>;
589};
590
591&i2c3 {
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c3_xfer>;
594};
595
596&i2c4 {
597 pinctrl-names = "default";
598 pinctrl-0 = <&i2c4_xfer>;
599};
600
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200601&mmc0 {
602 pinctrl-names = "default";
603 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
604};
605
606&mmc1 {
607 pinctrl-names = "default";
608 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
609};
610
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200611&pwm0 {
612 pinctrl-names = "default";
613 pinctrl-0 = <&pwm0_out>;
614};
615
616&pwm1 {
617 pinctrl-names = "default";
618 pinctrl-0 = <&pwm1_out>;
619};
620
621&pwm2 {
622 pinctrl-names = "default";
623 pinctrl-0 = <&pwm2_out>;
624};
625
626&pwm3 {
627 pinctrl-names = "default";
628 pinctrl-0 = <&pwm3_out>;
629};
630
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200631&spi0 {
632 pinctrl-names = "default";
633 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
634};
635
636&spi1 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
639};
640
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200641&uart0 {
642 pinctrl-names = "default";
643 pinctrl-0 = <&uart0_xfer>;
644};
645
646&uart1 {
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart1_xfer>;
649};
650
651&uart2 {
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart2_xfer>;
654};
655
656&uart3 {
657 pinctrl-names = "default";
658 pinctrl-0 = <&uart3_xfer>;
659};
Heiko Stuebnereb2b9d42014-07-30 10:16:17 +0200660
661&wdt {
662 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
663};
Romain Perier89f66872014-11-02 10:20:00 +0000664
665&emac {
666 compatible = "rockchip,rk3066-emac";
667};