| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-ks8695/include/mach/regs-sys.h |
| 3 | * |
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> |
| 5 | * Copyright (C) 2006 Simtec Electronics |
| 6 | * |
| 7 | * KS8695 - System control registers and bit definitions |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifndef KS8695_SYS_H |
| 15 | #define KS8695_SYS_H |
| 16 | |
| 17 | #define KS8695_SYS_OFFSET (0xF0000 + 0x0000) |
| 18 | #define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) |
| 19 | #define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) |
| 20 | |
| 21 | |
| 22 | #define KS8695_SYSCFG (0x00) /* System Configuration Register */ |
| 23 | #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ |
| 24 | |
| 25 | |
| 26 | /* System Configuration Register */ |
| 27 | #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ |
| 28 | |
| 29 | /* System Clock and Bus Control Register */ |
| 30 | #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ |
| 31 | #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ |
| 32 | |
| 33 | |
| 34 | #endif |