blob: ae01555d24cf8bf637580be4405b9fe35a77f762 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: lmc_media.c,v 1.13 2000/04/11 05:25:26 asj Exp $ */
2
Linus Torvalds1da177e2005-04-16 15:20:36 -07003#include <linux/kernel.h>
4#include <linux/string.h>
5#include <linux/timer.h>
6#include <linux/ptrace.h>
7#include <linux/errno.h>
8#include <linux/ioport.h>
9#include <linux/slab.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/in.h>
13#include <linux/if_arp.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/skbuff.h>
17#include <linux/inet.h>
18#include <linux/bitops.h>
19
20#include <net/syncppp.h>
21
22#include <asm/processor.h> /* Processor type for cache alignment. */
23#include <asm/io.h>
24#include <asm/dma.h>
25
26#include <asm/uaccess.h>
27
28#include "lmc.h"
29#include "lmc_var.h"
30#include "lmc_ioctl.h"
31#include "lmc_debug.h"
32
33#define CONFIG_LMC_IGNORE_HARDWARE_HANDSHAKE 1
34
35 /*
36 * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
37 * All rights reserved. www.lanmedia.com
38 *
39 * This code is written by:
40 * Andrew Stanley-Jones (asj@cban.com)
41 * Rob Braun (bbraun@vix.com),
42 * Michael Graff (explorer@vix.com) and
43 * Matt Thomas (matt@3am-software.com).
44 *
45 * This software may be used and distributed according to the terms
46 * of the GNU General Public License version 2, incorporated herein by reference.
47 */
48
49/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 * protocol independent method.
51 */
52static void lmc_set_protocol (lmc_softc_t * const, lmc_ctl_t *);
53
54/*
55 * media independent methods to check on media status, link, light LEDs,
56 * etc.
57 */
58static void lmc_ds3_init (lmc_softc_t * const);
59static void lmc_ds3_default (lmc_softc_t * const);
60static void lmc_ds3_set_status (lmc_softc_t * const, lmc_ctl_t *);
61static void lmc_ds3_set_100ft (lmc_softc_t * const, int);
62static int lmc_ds3_get_link_status (lmc_softc_t * const);
63static void lmc_ds3_set_crc_length (lmc_softc_t * const, int);
64static void lmc_ds3_set_scram (lmc_softc_t * const, int);
65static void lmc_ds3_watchdog (lmc_softc_t * const);
66
67static void lmc_hssi_init (lmc_softc_t * const);
68static void lmc_hssi_default (lmc_softc_t * const);
69static void lmc_hssi_set_status (lmc_softc_t * const, lmc_ctl_t *);
70static void lmc_hssi_set_clock (lmc_softc_t * const, int);
71static int lmc_hssi_get_link_status (lmc_softc_t * const);
72static void lmc_hssi_set_link_status (lmc_softc_t * const, int);
73static void lmc_hssi_set_crc_length (lmc_softc_t * const, int);
74static void lmc_hssi_watchdog (lmc_softc_t * const);
75
76static void lmc_ssi_init (lmc_softc_t * const);
77static void lmc_ssi_default (lmc_softc_t * const);
78static void lmc_ssi_set_status (lmc_softc_t * const, lmc_ctl_t *);
79static void lmc_ssi_set_clock (lmc_softc_t * const, int);
80static void lmc_ssi_set_speed (lmc_softc_t * const, lmc_ctl_t *);
81static int lmc_ssi_get_link_status (lmc_softc_t * const);
82static void lmc_ssi_set_link_status (lmc_softc_t * const, int);
83static void lmc_ssi_set_crc_length (lmc_softc_t * const, int);
84static void lmc_ssi_watchdog (lmc_softc_t * const);
85
86static void lmc_t1_init (lmc_softc_t * const);
87static void lmc_t1_default (lmc_softc_t * const);
88static void lmc_t1_set_status (lmc_softc_t * const, lmc_ctl_t *);
89static int lmc_t1_get_link_status (lmc_softc_t * const);
90static void lmc_t1_set_circuit_type (lmc_softc_t * const, int);
91static void lmc_t1_set_crc_length (lmc_softc_t * const, int);
92static void lmc_t1_set_clock (lmc_softc_t * const, int);
93static void lmc_t1_watchdog (lmc_softc_t * const);
94
95static void lmc_dummy_set_1 (lmc_softc_t * const, int);
96static void lmc_dummy_set2_1 (lmc_softc_t * const, lmc_ctl_t *);
97
98static inline void write_av9110_bit (lmc_softc_t *, int);
99static void write_av9110 (lmc_softc_t *, u_int32_t, u_int32_t, u_int32_t,
100 u_int32_t, u_int32_t);
101
102lmc_media_t lmc_ds3_media = {
103 lmc_ds3_init, /* special media init stuff */
104 lmc_ds3_default, /* reset to default state */
105 lmc_ds3_set_status, /* reset status to state provided */
106 lmc_dummy_set_1, /* set clock source */
107 lmc_dummy_set2_1, /* set line speed */
108 lmc_ds3_set_100ft, /* set cable length */
109 lmc_ds3_set_scram, /* set scrambler */
110 lmc_ds3_get_link_status, /* get link status */
111 lmc_dummy_set_1, /* set link status */
112 lmc_ds3_set_crc_length, /* set CRC length */
113 lmc_dummy_set_1, /* set T1 or E1 circuit type */
114 lmc_ds3_watchdog
115};
116
117lmc_media_t lmc_hssi_media = {
118 lmc_hssi_init, /* special media init stuff */
119 lmc_hssi_default, /* reset to default state */
120 lmc_hssi_set_status, /* reset status to state provided */
121 lmc_hssi_set_clock, /* set clock source */
122 lmc_dummy_set2_1, /* set line speed */
123 lmc_dummy_set_1, /* set cable length */
124 lmc_dummy_set_1, /* set scrambler */
125 lmc_hssi_get_link_status, /* get link status */
126 lmc_hssi_set_link_status, /* set link status */
127 lmc_hssi_set_crc_length, /* set CRC length */
128 lmc_dummy_set_1, /* set T1 or E1 circuit type */
129 lmc_hssi_watchdog
130};
131
132lmc_media_t lmc_ssi_media = { lmc_ssi_init, /* special media init stuff */
133 lmc_ssi_default, /* reset to default state */
134 lmc_ssi_set_status, /* reset status to state provided */
135 lmc_ssi_set_clock, /* set clock source */
136 lmc_ssi_set_speed, /* set line speed */
137 lmc_dummy_set_1, /* set cable length */
138 lmc_dummy_set_1, /* set scrambler */
139 lmc_ssi_get_link_status, /* get link status */
140 lmc_ssi_set_link_status, /* set link status */
141 lmc_ssi_set_crc_length, /* set CRC length */
142 lmc_dummy_set_1, /* set T1 or E1 circuit type */
143 lmc_ssi_watchdog
144};
145
146lmc_media_t lmc_t1_media = {
147 lmc_t1_init, /* special media init stuff */
148 lmc_t1_default, /* reset to default state */
149 lmc_t1_set_status, /* reset status to state provided */
150 lmc_t1_set_clock, /* set clock source */
151 lmc_dummy_set2_1, /* set line speed */
152 lmc_dummy_set_1, /* set cable length */
153 lmc_dummy_set_1, /* set scrambler */
154 lmc_t1_get_link_status, /* get link status */
155 lmc_dummy_set_1, /* set link status */
156 lmc_t1_set_crc_length, /* set CRC length */
157 lmc_t1_set_circuit_type, /* set T1 or E1 circuit type */
158 lmc_t1_watchdog
159};
160
161static void
162lmc_dummy_set_1 (lmc_softc_t * const sc, int a)
163{
164}
165
166static void
167lmc_dummy_set2_1 (lmc_softc_t * const sc, lmc_ctl_t * a)
168{
169}
170
171/*
172 * HSSI methods
173 */
174
175static void
176lmc_hssi_init (lmc_softc_t * const sc)
177{
178 sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5200;
179
180 lmc_gpio_mkoutput (sc, LMC_GEP_HSSI_CLOCK);
181}
182
183static void
184lmc_hssi_default (lmc_softc_t * const sc)
185{
186 sc->lmc_miireg16 = LMC_MII16_LED_ALL;
187
188 sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
189 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
190 sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
191}
192
193/*
194 * Given a user provided state, set ourselves up to match it. This will
195 * always reset the card if needed.
196 */
197static void
198lmc_hssi_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
199{
200 if (ctl == NULL)
201 {
202 sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
203 lmc_set_protocol (sc, NULL);
204
205 return;
206 }
207
208 /*
209 * check for change in clock source
210 */
211 if (ctl->clock_source && !sc->ictl.clock_source)
212 {
213 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_INT);
214 sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT;
215 }
216 else if (!ctl->clock_source && sc->ictl.clock_source)
217 {
218 sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
219 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
220 }
221
222 lmc_set_protocol (sc, ctl);
223}
224
225/*
226 * 1 == internal, 0 == external
227 */
228static void
229lmc_hssi_set_clock (lmc_softc_t * const sc, int ie)
230{
231 int old;
232 old = sc->ictl.clock_source;
233 if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
234 {
235 sc->lmc_gpio |= LMC_GEP_HSSI_CLOCK;
236 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
237 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
238 if(old != ie)
239 printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
240 }
241 else
242 {
243 sc->lmc_gpio &= ~(LMC_GEP_HSSI_CLOCK);
244 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
245 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
246 if(old != ie)
247 printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
248 }
249}
250
251/*
252 * return hardware link status.
253 * 0 == link is down, 1 == link is up.
254 */
255static int
256lmc_hssi_get_link_status (lmc_softc_t * const sc)
257{
258 /*
259 * We're using the same code as SSI since
260 * they're practically the same
261 */
262 return lmc_ssi_get_link_status(sc);
263}
264
265static void
266lmc_hssi_set_link_status (lmc_softc_t * const sc, int state)
267{
268 if (state == LMC_LINK_UP)
269 sc->lmc_miireg16 |= LMC_MII16_HSSI_TA;
270 else
271 sc->lmc_miireg16 &= ~LMC_MII16_HSSI_TA;
272
273 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
274}
275
276/*
277 * 0 == 16bit, 1 == 32bit
278 */
279static void
280lmc_hssi_set_crc_length (lmc_softc_t * const sc, int state)
281{
282 if (state == LMC_CTL_CRC_LENGTH_32)
283 {
284 /* 32 bit */
285 sc->lmc_miireg16 |= LMC_MII16_HSSI_CRC;
286 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
287 }
288 else
289 {
290 /* 16 bit */
291 sc->lmc_miireg16 &= ~LMC_MII16_HSSI_CRC;
292 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
293 }
294
295 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
296}
297
298static void
299lmc_hssi_watchdog (lmc_softc_t * const sc)
300{
301 /* HSSI is blank */
302}
303
304/*
305 * DS3 methods
306 */
307
308/*
309 * Set cable length
310 */
311static void
312lmc_ds3_set_100ft (lmc_softc_t * const sc, int ie)
313{
314 if (ie == LMC_CTL_CABLE_LENGTH_GT_100FT)
315 {
316 sc->lmc_miireg16 &= ~LMC_MII16_DS3_ZERO;
317 sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_GT_100FT;
318 }
319 else if (ie == LMC_CTL_CABLE_LENGTH_LT_100FT)
320 {
321 sc->lmc_miireg16 |= LMC_MII16_DS3_ZERO;
322 sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_LT_100FT;
323 }
324 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
325}
326
327static void
328lmc_ds3_default (lmc_softc_t * const sc)
329{
330 sc->lmc_miireg16 = LMC_MII16_LED_ALL;
331
332 sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
333 sc->lmc_media->set_cable_length (sc, LMC_CTL_CABLE_LENGTH_LT_100FT);
334 sc->lmc_media->set_scrambler (sc, LMC_CTL_OFF);
335 sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
336}
337
338/*
339 * Given a user provided state, set ourselves up to match it. This will
340 * always reset the card if needed.
341 */
342static void
343lmc_ds3_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
344{
345 if (ctl == NULL)
346 {
347 sc->lmc_media->set_cable_length (sc, sc->ictl.cable_length);
348 sc->lmc_media->set_scrambler (sc, sc->ictl.scrambler_onoff);
349 lmc_set_protocol (sc, NULL);
350
351 return;
352 }
353
354 /*
355 * check for change in cable length setting
356 */
357 if (ctl->cable_length && !sc->ictl.cable_length)
358 lmc_ds3_set_100ft (sc, LMC_CTL_CABLE_LENGTH_GT_100FT);
359 else if (!ctl->cable_length && sc->ictl.cable_length)
360 lmc_ds3_set_100ft (sc, LMC_CTL_CABLE_LENGTH_LT_100FT);
361
362 /*
363 * Check for change in scrambler setting (requires reset)
364 */
365 if (ctl->scrambler_onoff && !sc->ictl.scrambler_onoff)
366 lmc_ds3_set_scram (sc, LMC_CTL_ON);
367 else if (!ctl->scrambler_onoff && sc->ictl.scrambler_onoff)
368 lmc_ds3_set_scram (sc, LMC_CTL_OFF);
369
370 lmc_set_protocol (sc, ctl);
371}
372
373static void
374lmc_ds3_init (lmc_softc_t * const sc)
375{
376 int i;
377
378 sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5245;
379
380 /* writes zeros everywhere */
381 for (i = 0; i < 21; i++)
382 {
383 lmc_mii_writereg (sc, 0, 17, i);
384 lmc_mii_writereg (sc, 0, 18, 0);
385 }
386
387 /* set some essential bits */
388 lmc_mii_writereg (sc, 0, 17, 1);
389 lmc_mii_writereg (sc, 0, 18, 0x25); /* ser, xtx */
390
391 lmc_mii_writereg (sc, 0, 17, 5);
392 lmc_mii_writereg (sc, 0, 18, 0x80); /* emode */
393
394 lmc_mii_writereg (sc, 0, 17, 14);
395 lmc_mii_writereg (sc, 0, 18, 0x30); /* rcgen, tcgen */
396
397 /* clear counters and latched bits */
398 for (i = 0; i < 21; i++)
399 {
400 lmc_mii_writereg (sc, 0, 17, i);
401 lmc_mii_readreg (sc, 0, 18);
402 }
403}
404
405/*
406 * 1 == DS3 payload scrambled, 0 == not scrambled
407 */
408static void
409lmc_ds3_set_scram (lmc_softc_t * const sc, int ie)
410{
411 if (ie == LMC_CTL_ON)
412 {
413 sc->lmc_miireg16 |= LMC_MII16_DS3_SCRAM;
414 sc->ictl.scrambler_onoff = LMC_CTL_ON;
415 }
416 else
417 {
418 sc->lmc_miireg16 &= ~LMC_MII16_DS3_SCRAM;
419 sc->ictl.scrambler_onoff = LMC_CTL_OFF;
420 }
421 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
422}
423
424/*
425 * return hardware link status.
426 * 0 == link is down, 1 == link is up.
427 */
428static int
429lmc_ds3_get_link_status (lmc_softc_t * const sc)
430{
431 u_int16_t link_status, link_status_11;
432 int ret = 1;
433
434 lmc_mii_writereg (sc, 0, 17, 7);
435 link_status = lmc_mii_readreg (sc, 0, 18);
436
437 /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions
438 * led0 yellow = far-end adapter is in Red alarm condition
439 * led1 blue = received an Alarm Indication signal
440 * (upstream failure)
441 * led2 Green = power to adapter, Gate Array loaded & driver
442 * attached
443 * led3 red = Loss of Signal (LOS) or out of frame (OOF)
444 * conditions detected on T3 receive signal
445 */
446
447 lmc_led_on(sc, LMC_DS3_LED2);
448
449 if ((link_status & LMC_FRAMER_REG0_DLOS) ||
450 (link_status & LMC_FRAMER_REG0_OOFS)){
451 ret = 0;
452 if(sc->last_led_err[3] != 1){
453 u16 r1;
454 lmc_mii_writereg (sc, 0, 17, 01); /* Turn on Xbit error as our cisco does */
455 r1 = lmc_mii_readreg (sc, 0, 18);
456 r1 &= 0xfe;
457 lmc_mii_writereg(sc, 0, 18, r1);
458 printk(KERN_WARNING "%s: Red Alarm - Loss of Signal or Loss of Framing\n", sc->name);
459 }
460 lmc_led_on(sc, LMC_DS3_LED3); /* turn on red LED */
461 sc->last_led_err[3] = 1;
462 }
463 else {
464 lmc_led_off(sc, LMC_DS3_LED3); /* turn on red LED */
465 if(sc->last_led_err[3] == 1){
466 u16 r1;
467 lmc_mii_writereg (sc, 0, 17, 01); /* Turn off Xbit error */
468 r1 = lmc_mii_readreg (sc, 0, 18);
469 r1 |= 0x01;
470 lmc_mii_writereg(sc, 0, 18, r1);
471 }
472 sc->last_led_err[3] = 0;
473 }
474
475 lmc_mii_writereg(sc, 0, 17, 0x10);
476 link_status_11 = lmc_mii_readreg(sc, 0, 18);
477 if((link_status & LMC_FRAMER_REG0_AIS) ||
478 (link_status_11 & LMC_FRAMER_REG10_XBIT)) {
479 ret = 0;
480 if(sc->last_led_err[0] != 1){
481 printk(KERN_WARNING "%s: AIS Alarm or XBit Error\n", sc->name);
482 printk(KERN_WARNING "%s: Remote end has loss of signal or framing\n", sc->name);
483 }
484 lmc_led_on(sc, LMC_DS3_LED0);
485 sc->last_led_err[0] = 1;
486 }
487 else {
488 lmc_led_off(sc, LMC_DS3_LED0);
489 sc->last_led_err[0] = 0;
490 }
491
492 lmc_mii_writereg (sc, 0, 17, 9);
493 link_status = lmc_mii_readreg (sc, 0, 18);
494
495 if(link_status & LMC_FRAMER_REG9_RBLUE){
496 ret = 0;
497 if(sc->last_led_err[1] != 1){
498 printk(KERN_WARNING "%s: Blue Alarm - Receiving all 1's\n", sc->name);
499 }
500 lmc_led_on(sc, LMC_DS3_LED1);
501 sc->last_led_err[1] = 1;
502 }
503 else {
504 lmc_led_off(sc, LMC_DS3_LED1);
505 sc->last_led_err[1] = 0;
506 }
507
508 return ret;
509}
510
511/*
512 * 0 == 16bit, 1 == 32bit
513 */
514static void
515lmc_ds3_set_crc_length (lmc_softc_t * const sc, int state)
516{
517 if (state == LMC_CTL_CRC_LENGTH_32)
518 {
519 /* 32 bit */
520 sc->lmc_miireg16 |= LMC_MII16_DS3_CRC;
521 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
522 }
523 else
524 {
525 /* 16 bit */
526 sc->lmc_miireg16 &= ~LMC_MII16_DS3_CRC;
527 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
528 }
529
530 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
531}
532
533static void
534lmc_ds3_watchdog (lmc_softc_t * const sc)
535{
536
537}
538
539
540/*
541 * SSI methods
542 */
543
544static void
545lmc_ssi_init (lmc_softc_t * const sc)
546{
547 u_int16_t mii17;
548 int cable;
549
550 sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1000;
551
552 mii17 = lmc_mii_readreg (sc, 0, 17);
553
554 cable = (mii17 & LMC_MII17_SSI_CABLE_MASK) >> LMC_MII17_SSI_CABLE_SHIFT;
555 sc->ictl.cable_type = cable;
556
557 lmc_gpio_mkoutput (sc, LMC_GEP_SSI_TXCLOCK);
558}
559
560static void
561lmc_ssi_default (lmc_softc_t * const sc)
562{
563 sc->lmc_miireg16 = LMC_MII16_LED_ALL;
564
565 /*
566 * make TXCLOCK always be an output
567 */
568 lmc_gpio_mkoutput (sc, LMC_GEP_SSI_TXCLOCK);
569
570 sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
571 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
572 sc->lmc_media->set_speed (sc, NULL);
573 sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
574}
575
576/*
577 * Given a user provided state, set ourselves up to match it. This will
578 * always reset the card if needed.
579 */
580static void
581lmc_ssi_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
582{
583 if (ctl == NULL)
584 {
585 sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
586 sc->lmc_media->set_speed (sc, &sc->ictl);
587 lmc_set_protocol (sc, NULL);
588
589 return;
590 }
591
592 /*
593 * check for change in clock source
594 */
595 if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_INT
596 && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_EXT)
597 {
598 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_INT);
599 sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT;
600 }
601 else if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_EXT
602 && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_INT)
603 {
604 sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
605 sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
606 }
607
608 if (ctl->clock_rate != sc->ictl.clock_rate)
609 sc->lmc_media->set_speed (sc, ctl);
610
611 lmc_set_protocol (sc, ctl);
612}
613
614/*
615 * 1 == internal, 0 == external
616 */
617static void
618lmc_ssi_set_clock (lmc_softc_t * const sc, int ie)
619{
620 int old;
621 old = ie;
622 if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
623 {
624 sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK);
625 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
626 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
627 if(ie != old)
628 printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
629 }
630 else
631 {
632 sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK;
633 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
634 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
635 if(ie != old)
636 printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
637 }
638}
639
640static void
641lmc_ssi_set_speed (lmc_softc_t * const sc, lmc_ctl_t * ctl)
642{
643 lmc_ctl_t *ictl = &sc->ictl;
644 lmc_av9110_t *av;
645
646 /* original settings for clock rate of:
647 * 100 Khz (8,25,0,0,2) were incorrect
648 * they should have been 80,125,1,3,3
649 * There are 17 param combinations to produce this freq.
650 * For 1.5 Mhz use 120,100,1,1,2 (226 param. combinations)
651 */
652 if (ctl == NULL)
653 {
654 av = &ictl->cardspec.ssi;
655 ictl->clock_rate = 1500000;
656 av->f = ictl->clock_rate;
657 av->n = 120;
658 av->m = 100;
659 av->v = 1;
660 av->x = 1;
661 av->r = 2;
662
663 write_av9110 (sc, av->n, av->m, av->v, av->x, av->r);
664 return;
665 }
666
667 av = &ctl->cardspec.ssi;
668
669 if (av->f == 0)
670 return;
671
672 ictl->clock_rate = av->f; /* really, this is the rate we are */
673 ictl->cardspec.ssi = *av;
674
675 write_av9110 (sc, av->n, av->m, av->v, av->x, av->r);
676}
677
678/*
679 * return hardware link status.
680 * 0 == link is down, 1 == link is up.
681 */
682static int
683lmc_ssi_get_link_status (lmc_softc_t * const sc)
684{
685 u_int16_t link_status;
686 u_int32_t ticks;
687 int ret = 1;
688 int hw_hdsk = 1;
689
690 /*
691 * missing CTS? Hmm. If we require CTS on, we may never get the
692 * link to come up, so omit it in this test.
693 *
694 * Also, it seems that with a loopback cable, DCD isn't asserted,
695 * so just check for things like this:
696 * DSR _must_ be asserted.
697 * One of DCD or CTS must be asserted.
698 */
699
700 /* LMC 1000 (SSI) LED definitions
701 * led0 Green = power to adapter, Gate Array loaded &
702 * driver attached
703 * led1 Green = DSR and DTR and RTS and CTS are set
704 * led2 Green = Cable detected
705 * led3 red = No timing is available from the
706 * cable or the on-board frequency
707 * generator.
708 */
709
710 link_status = lmc_mii_readreg (sc, 0, 16);
711
712 /* Is the transmit clock still available */
713 ticks = LMC_CSR_READ (sc, csr_gp_timer);
714 ticks = 0x0000ffff - (ticks & 0x0000ffff);
715
716 lmc_led_on (sc, LMC_MII16_LED0);
717
718 /* ====== transmit clock determination ===== */
719 if (sc->lmc_timing == LMC_CTL_CLOCK_SOURCE_INT) {
720 lmc_led_off(sc, LMC_MII16_LED3);
721 }
722 else if (ticks == 0 ) { /* no clock found ? */
723 ret = 0;
724 if(sc->last_led_err[3] != 1){
725 sc->stats.tx_lossOfClockCnt++;
726 printk(KERN_WARNING "%s: Lost Clock, Link Down\n", sc->name);
727 }
728 sc->last_led_err[3] = 1;
729 lmc_led_on (sc, LMC_MII16_LED3); /* turn ON red LED */
730 }
731 else {
732 if(sc->last_led_err[3] == 1)
733 printk(KERN_WARNING "%s: Clock Returned\n", sc->name);
734 sc->last_led_err[3] = 0;
735 lmc_led_off (sc, LMC_MII16_LED3); /* turn OFF red LED */
736 }
737
738 if ((link_status & LMC_MII16_SSI_DSR) == 0) { /* Also HSSI CA */
739 ret = 0;
740 hw_hdsk = 0;
741 }
742
743#ifdef CONFIG_LMC_IGNORE_HARDWARE_HANDSHAKE
744 if ((link_status & (LMC_MII16_SSI_CTS | LMC_MII16_SSI_DCD)) == 0){
745 ret = 0;
746 hw_hdsk = 0;
747 }
748#endif
749
750 if(hw_hdsk == 0){
751 if(sc->last_led_err[1] != 1)
752 printk(KERN_WARNING "%s: DSR not asserted\n", sc->name);
753 sc->last_led_err[1] = 1;
754 lmc_led_off(sc, LMC_MII16_LED1);
755 }
756 else {
757 if(sc->last_led_err[1] != 0)
758 printk(KERN_WARNING "%s: DSR now asserted\n", sc->name);
759 sc->last_led_err[1] = 0;
760 lmc_led_on(sc, LMC_MII16_LED1);
761 }
762
763 if(ret == 1) {
764 lmc_led_on(sc, LMC_MII16_LED2); /* Over all good status? */
765 }
766
767 return ret;
768}
769
770static void
771lmc_ssi_set_link_status (lmc_softc_t * const sc, int state)
772{
773 if (state == LMC_LINK_UP)
774 {
775 sc->lmc_miireg16 |= (LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
776 printk (LMC_PRINTF_FMT ": asserting DTR and RTS\n", LMC_PRINTF_ARGS);
777 }
778 else
779 {
780 sc->lmc_miireg16 &= ~(LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
781 printk (LMC_PRINTF_FMT ": deasserting DTR and RTS\n", LMC_PRINTF_ARGS);
782 }
783
784 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
785
786}
787
788/*
789 * 0 == 16bit, 1 == 32bit
790 */
791static void
792lmc_ssi_set_crc_length (lmc_softc_t * const sc, int state)
793{
794 if (state == LMC_CTL_CRC_LENGTH_32)
795 {
796 /* 32 bit */
797 sc->lmc_miireg16 |= LMC_MII16_SSI_CRC;
798 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
799 sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4;
800
801 }
802 else
803 {
804 /* 16 bit */
805 sc->lmc_miireg16 &= ~LMC_MII16_SSI_CRC;
806 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
807 sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2;
808 }
809
810 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
811}
812
813/*
814 * These are bits to program the ssi frequency generator
815 */
816static inline void
817write_av9110_bit (lmc_softc_t * sc, int c)
818{
819 /*
820 * set the data bit as we need it.
821 */
822 sc->lmc_gpio &= ~(LMC_GEP_CLK);
823 if (c & 0x01)
824 sc->lmc_gpio |= LMC_GEP_DATA;
825 else
826 sc->lmc_gpio &= ~(LMC_GEP_DATA);
827 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
828
829 /*
830 * set the clock to high
831 */
832 sc->lmc_gpio |= LMC_GEP_CLK;
833 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
834
835 /*
836 * set the clock to low again.
837 */
838 sc->lmc_gpio &= ~(LMC_GEP_CLK);
839 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
840}
841
842static void
843write_av9110 (lmc_softc_t * sc, u_int32_t n, u_int32_t m, u_int32_t v,
844 u_int32_t x, u_int32_t r)
845{
846 int i;
847
848#if 0
849 printk (LMC_PRINTF_FMT ": speed %u, %d %d %d %d %d\n",
850 LMC_PRINTF_ARGS, sc->ictl.clock_rate, n, m, v, x, r);
851#endif
852
853 sc->lmc_gpio |= LMC_GEP_SSI_GENERATOR;
854 sc->lmc_gpio &= ~(LMC_GEP_DATA | LMC_GEP_CLK);
855 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
856
857 /*
858 * Set the TXCLOCK, GENERATOR, SERIAL, and SERIALCLK
859 * as outputs.
860 */
861 lmc_gpio_mkoutput (sc, (LMC_GEP_DATA | LMC_GEP_CLK
862 | LMC_GEP_SSI_GENERATOR));
863
864 sc->lmc_gpio &= ~(LMC_GEP_SSI_GENERATOR);
865 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
866
867 /*
868 * a shifting we will go...
869 */
870 for (i = 0; i < 7; i++)
871 write_av9110_bit (sc, n >> i);
872 for (i = 0; i < 7; i++)
873 write_av9110_bit (sc, m >> i);
874 for (i = 0; i < 1; i++)
875 write_av9110_bit (sc, v >> i);
876 for (i = 0; i < 2; i++)
877 write_av9110_bit (sc, x >> i);
878 for (i = 0; i < 2; i++)
879 write_av9110_bit (sc, r >> i);
880 for (i = 0; i < 5; i++)
881 write_av9110_bit (sc, 0x17 >> i);
882
883 /*
884 * stop driving serial-related signals
885 */
886 lmc_gpio_mkinput (sc,
887 (LMC_GEP_DATA | LMC_GEP_CLK
888 | LMC_GEP_SSI_GENERATOR));
889}
890
891static void
892lmc_ssi_watchdog (lmc_softc_t * const sc)
893{
894 u_int16_t mii17;
895 struct ssicsr2
896 {
897 unsigned short dtr:1, dsr:1, rts:1, cable:3, crc:1, led0:1, led1:1,
898 led2:1, led3:1, fifo:1, ll:1, rl:1, tm:1, loop:1;
899 };
900 struct ssicsr2 *ssicsr;
901 mii17 = lmc_mii_readreg (sc, 0, 17);
902 ssicsr = (struct ssicsr2 *) &mii17;
903 if (ssicsr->cable == 7)
904 {
905 lmc_led_off (sc, LMC_MII16_LED2);
906 }
907 else
908 {
909 lmc_led_on (sc, LMC_MII16_LED2);
910 }
911
912}
913
914/*
915 * T1 methods
916 */
917
918/*
919 * The framer regs are multiplexed through MII regs 17 & 18
920 * write the register address to MII reg 17 and the * data to MII reg 18. */
921static void
922lmc_t1_write (lmc_softc_t * const sc, int a, int d)
923{
924 lmc_mii_writereg (sc, 0, 17, a);
925 lmc_mii_writereg (sc, 0, 18, d);
926}
927
928/* Save a warning
929static int
930lmc_t1_read (lmc_softc_t * const sc, int a)
931{
932 lmc_mii_writereg (sc, 0, 17, a);
933 return lmc_mii_readreg (sc, 0, 18);
934}
935*/
936
937
938static void
939lmc_t1_init (lmc_softc_t * const sc)
940{
941 u_int16_t mii16;
942 int i;
943
944 sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200;
945 mii16 = lmc_mii_readreg (sc, 0, 16);
946
947 /* reset 8370 */
948 mii16 &= ~LMC_MII16_T1_RST;
949 lmc_mii_writereg (sc, 0, 16, mii16 | LMC_MII16_T1_RST);
950 lmc_mii_writereg (sc, 0, 16, mii16);
951
952 /* set T1 or E1 line. Uses sc->lmcmii16 reg in function so update it */
953 sc->lmc_miireg16 = mii16;
954 lmc_t1_set_circuit_type(sc, LMC_CTL_CIRCUIT_TYPE_T1);
955 mii16 = sc->lmc_miireg16;
956
957 lmc_t1_write (sc, 0x01, 0x1B); /* CR0 - primary control */
958 lmc_t1_write (sc, 0x02, 0x42); /* JAT_CR - jitter atten config */
959 lmc_t1_write (sc, 0x14, 0x00); /* LOOP - loopback config */
960 lmc_t1_write (sc, 0x15, 0x00); /* DL3_TS - external data link timeslot */
961 lmc_t1_write (sc, 0x18, 0xFF); /* PIO - programmable I/O */
962 lmc_t1_write (sc, 0x19, 0x30); /* POE - programmable OE */
963 lmc_t1_write (sc, 0x1A, 0x0F); /* CMUX - clock input mux */
964 lmc_t1_write (sc, 0x20, 0x41); /* LIU_CR - RX LIU config */
965 lmc_t1_write (sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */
966 lmc_t1_write (sc, 0x40, 0x03); /* RCR0 - RX config */
967 lmc_t1_write (sc, 0x45, 0x00); /* RALM - RX alarm config */
968 lmc_t1_write (sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */
969 lmc_t1_write (sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */
970 lmc_t1_write (sc, 0x70, 0x0D); /* TCR0 - TX framer config */
971 lmc_t1_write (sc, 0x71, 0x05); /* TCR1 - TX config */
972 lmc_t1_write (sc, 0x72, 0x0B); /* TFRM - TX frame format */
973 lmc_t1_write (sc, 0x73, 0x00); /* TERROR - TX error insert */
974 lmc_t1_write (sc, 0x74, 0x00); /* TMAN - TX manual Sa/FEBE config */
975 lmc_t1_write (sc, 0x75, 0x00); /* TALM - TX alarm signal config */
976 lmc_t1_write (sc, 0x76, 0x00); /* TPATT - TX test pattern config */
977 lmc_t1_write (sc, 0x77, 0x00); /* TLB - TX inband loopback config */
978 lmc_t1_write (sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter config */
979 lmc_t1_write (sc, 0x91, 0x05); /* CSEL - clad freq sel */
980 lmc_t1_write (sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */
981 lmc_t1_write (sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */
982 lmc_t1_write (sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */
983 lmc_t1_write (sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */
984 lmc_t1_write (sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */
985 for (i = 0; i < 32; i++)
986 {
987 lmc_t1_write (sc, 0x0E0 + i, 0x00); /* SBCn - sys bus per-channel ctl */
988 lmc_t1_write (sc, 0x100 + i, 0x00); /* TPCn - TX per-channel ctl */
989 lmc_t1_write (sc, 0x180 + i, 0x00); /* RPCn - RX per-channel ctl */
990 }
991 for (i = 1; i < 25; i++)
992 {
993 lmc_t1_write (sc, 0x0E0 + i, 0x0D); /* SBCn - sys bus per-channel ctl */
994 }
995
996 mii16 |= LMC_MII16_T1_XOE;
997 lmc_mii_writereg (sc, 0, 16, mii16);
998 sc->lmc_miireg16 = mii16;
999}
1000
1001static void
1002lmc_t1_default (lmc_softc_t * const sc)
1003{
1004 sc->lmc_miireg16 = LMC_MII16_LED_ALL;
1005 sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
1006 sc->lmc_media->set_circuit_type (sc, LMC_CTL_CIRCUIT_TYPE_T1);
1007 sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
1008 /* Right now we can only clock from out internal source */
1009 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
1010}
1011/* * Given a user provided state, set ourselves up to match it. This will * always reset the card if needed.
1012 */
1013static void
1014lmc_t1_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
1015{
1016 if (ctl == NULL)
1017 {
1018 sc->lmc_media->set_circuit_type (sc, sc->ictl.circuit_type);
1019 lmc_set_protocol (sc, NULL);
1020
1021 return;
1022 }
1023 /*
1024 * check for change in circuit type */
1025 if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_T1
1026 && sc->ictl.circuit_type ==
1027 LMC_CTL_CIRCUIT_TYPE_E1) sc->lmc_media->set_circuit_type (sc,
1028 LMC_CTL_CIRCUIT_TYPE_E1);
1029 else if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_E1
1030 && sc->ictl.circuit_type == LMC_CTL_CIRCUIT_TYPE_T1)
1031 sc->lmc_media->set_circuit_type (sc, LMC_CTL_CIRCUIT_TYPE_T1);
1032 lmc_set_protocol (sc, ctl);
1033}
1034/*
1035 * return hardware link status.
1036 * 0 == link is down, 1 == link is up.
1037 */ static int
1038lmc_t1_get_link_status (lmc_softc_t * const sc)
1039{
1040 u_int16_t link_status;
1041 int ret = 1;
1042
1043 /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions
1044 * led0 yellow = far-end adapter is in Red alarm condition
1045 * led1 blue = received an Alarm Indication signal
1046 * (upstream failure)
1047 * led2 Green = power to adapter, Gate Array loaded & driver
1048 * attached
1049 * led3 red = Loss of Signal (LOS) or out of frame (OOF)
1050 * conditions detected on T3 receive signal
1051 */
1052 lmc_trace(sc->lmc_device, "lmc_t1_get_link_status in");
1053 lmc_led_on(sc, LMC_DS3_LED2);
1054
1055 lmc_mii_writereg (sc, 0, 17, T1FRAMER_ALARM1_STATUS);
1056 link_status = lmc_mii_readreg (sc, 0, 18);
1057
1058
1059 if (link_status & T1F_RAIS) { /* turn on blue LED */
1060 ret = 0;
1061 if(sc->last_led_err[1] != 1){
1062 printk(KERN_WARNING "%s: Receive AIS/Blue Alarm. Far end in RED alarm\n", sc->name);
1063 }
1064 lmc_led_on(sc, LMC_DS3_LED1);
1065 sc->last_led_err[1] = 1;
1066 }
1067 else {
1068 if(sc->last_led_err[1] != 0){
1069 printk(KERN_WARNING "%s: End AIS/Blue Alarm\n", sc->name);
1070 }
1071 lmc_led_off (sc, LMC_DS3_LED1);
1072 sc->last_led_err[1] = 0;
1073 }
1074
1075 /*
1076 * Yellow Alarm is nasty evil stuff, looks at data patterns
1077 * inside the channel and confuses it with HDLC framing
1078 * ignore all yellow alarms.
1079 *
1080 * Do listen to MultiFrame Yellow alarm which while implemented
1081 * different ways isn't in the channel and hence somewhat
1082 * more reliable
1083 */
1084
1085 if (link_status & T1F_RMYEL) {
1086 ret = 0;
1087 if(sc->last_led_err[0] != 1){
1088 printk(KERN_WARNING "%s: Receive Yellow AIS Alarm\n", sc->name);
1089 }
1090 lmc_led_on(sc, LMC_DS3_LED0);
1091 sc->last_led_err[0] = 1;
1092 }
1093 else {
1094 if(sc->last_led_err[0] != 0){
1095 printk(KERN_WARNING "%s: End of Yellow AIS Alarm\n", sc->name);
1096 }
1097 lmc_led_off(sc, LMC_DS3_LED0);
1098 sc->last_led_err[0] = 0;
1099 }
1100
1101 /*
1102 * Loss of signal and los of frame
1103 * Use the green bit to identify which one lit the led
1104 */
1105 if(link_status & T1F_RLOF){
1106 ret = 0;
1107 if(sc->last_led_err[3] != 1){
1108 printk(KERN_WARNING "%s: Local Red Alarm: Loss of Framing\n", sc->name);
1109 }
1110 lmc_led_on(sc, LMC_DS3_LED3);
1111 sc->last_led_err[3] = 1;
1112
1113 }
1114 else {
1115 if(sc->last_led_err[3] != 0){
1116 printk(KERN_WARNING "%s: End Red Alarm (LOF)\n", sc->name);
1117 }
1118 if( ! (link_status & T1F_RLOS))
1119 lmc_led_off(sc, LMC_DS3_LED3);
1120 sc->last_led_err[3] = 0;
1121 }
1122
1123 if(link_status & T1F_RLOS){
1124 ret = 0;
1125 if(sc->last_led_err[2] != 1){
1126 printk(KERN_WARNING "%s: Local Red Alarm: Loss of Signal\n", sc->name);
1127 }
1128 lmc_led_on(sc, LMC_DS3_LED3);
1129 sc->last_led_err[2] = 1;
1130
1131 }
1132 else {
1133 if(sc->last_led_err[2] != 0){
1134 printk(KERN_WARNING "%s: End Red Alarm (LOS)\n", sc->name);
1135 }
1136 if( ! (link_status & T1F_RLOF))
1137 lmc_led_off(sc, LMC_DS3_LED3);
1138 sc->last_led_err[2] = 0;
1139 }
1140
1141 sc->lmc_xinfo.t1_alarm1_status = link_status;
1142
1143 lmc_mii_writereg (sc, 0, 17, T1FRAMER_ALARM2_STATUS);
1144 sc->lmc_xinfo.t1_alarm2_status = lmc_mii_readreg (sc, 0, 18);
1145
1146
1147 lmc_trace(sc->lmc_device, "lmc_t1_get_link_status out");
1148
1149 return ret;
1150}
1151
1152/*
1153 * 1 == T1 Circuit Type , 0 == E1 Circuit Type
1154 */
1155static void
1156lmc_t1_set_circuit_type (lmc_softc_t * const sc, int ie)
1157{
1158 if (ie == LMC_CTL_CIRCUIT_TYPE_T1) {
1159 sc->lmc_miireg16 |= LMC_MII16_T1_Z;
1160 sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_T1;
1161 printk(KERN_INFO "%s: In T1 Mode\n", sc->name);
1162 }
1163 else {
1164 sc->lmc_miireg16 &= ~LMC_MII16_T1_Z;
1165 sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_E1;
1166 printk(KERN_INFO "%s: In E1 Mode\n", sc->name);
1167 }
1168
1169 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
1170
1171}
1172
1173/*
1174 * 0 == 16bit, 1 == 32bit */
1175static void
1176lmc_t1_set_crc_length (lmc_softc_t * const sc, int state)
1177{
1178 if (state == LMC_CTL_CRC_LENGTH_32)
1179 {
1180 /* 32 bit */
1181 sc->lmc_miireg16 |= LMC_MII16_T1_CRC;
1182 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
1183 sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4;
1184
1185 }
1186 else
1187 {
1188 /* 16 bit */ sc->lmc_miireg16 &= ~LMC_MII16_T1_CRC;
1189 sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
1190 sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2;
1191
1192 }
1193
1194 lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
1195}
1196
1197/*
1198 * 1 == internal, 0 == external
1199 */
1200static void
1201lmc_t1_set_clock (lmc_softc_t * const sc, int ie)
1202{
1203 int old;
1204 old = ie;
1205 if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
1206 {
1207 sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK);
1208 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
1209 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
1210 if(old != ie)
1211 printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
1212 }
1213 else
1214 {
1215 sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK;
1216 LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
1217 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
1218 if(old != ie)
1219 printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
1220 }
1221}
1222
1223static void
1224lmc_t1_watchdog (lmc_softc_t * const sc)
1225{
1226}
1227
1228static void
1229lmc_set_protocol (lmc_softc_t * const sc, lmc_ctl_t * ctl)
1230{
1231 if (ctl == 0)
1232 {
1233 sc->ictl.keepalive_onoff = LMC_CTL_ON;
1234
1235 return;
1236 }
1237}