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Murali Karicheri0c4ffcf2014-09-02 17:26:19 -06001/*
2 * Designware application register space functions for Keystone PCI controller
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_pci.h>
20#include <linux/pci.h>
21#include <linux/platform_device.h>
22
23#include "pcie-designware.h"
24#include "pci-keystone.h"
25
26/* Application register defines */
27#define LTSSM_EN_VAL 1
28#define LTSSM_STATE_MASK 0x1f
29#define LTSSM_STATE_L0 0x11
30#define DBI_CS2_EN_VAL 0x20
31#define OB_XLAT_EN_VAL 2
32
33/* Application registers */
34#define CMD_STATUS 0x004
35#define CFG_SETUP 0x008
36#define OB_SIZE 0x030
37#define CFG_PCIM_WIN_SZ_IDX 3
38#define CFG_PCIM_WIN_CNT 32
39#define SPACE0_REMOTE_CFG_OFFSET 0x1000
40#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
41#define OB_OFFSET_HI(n) (0x204 + (8 * n))
42
43/* IRQ register defines */
44#define IRQ_EOI 0x050
45#define IRQ_STATUS 0x184
46#define IRQ_ENABLE_SET 0x188
47#define IRQ_ENABLE_CLR 0x18c
48
49#define MSI_IRQ 0x054
50#define MSI0_IRQ_STATUS 0x104
51#define MSI0_IRQ_ENABLE_SET 0x108
52#define MSI0_IRQ_ENABLE_CLR 0x10c
53#define IRQ_STATUS 0x184
54#define MSI_IRQ_OFFSET 4
55
56/* Config space registers */
57#define DEBUG0 0x728
58
59#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
60
61static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
62{
63 return sys->private_data;
64}
65
66static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
67 u32 *bit_pos)
68{
69 *reg_offset = offset % 8;
70 *bit_pos = offset >> 3;
71}
72
Bjorn Helgaas11045282014-09-29 13:24:24 -060073u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060074{
75 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
76
77 return ks_pcie->app.start + MSI_IRQ;
78}
79
80void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
81{
82 struct pcie_port *pp = &ks_pcie->pp;
83 u32 pending, vector;
84 int src, virq;
85
86 pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
87
88 /*
89 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
90 * shows 1, 9, 17, 25 and so forth
91 */
92 for (src = 0; src < 4; src++) {
93 if (BIT(src) & pending) {
94 vector = offset + (src << 3);
95 virq = irq_linear_revmap(pp->irq_domain, vector);
96 dev_dbg(pp->dev, "irq: bit %d, vector %d, virq %d\n",
97 src, vector, virq);
98 generic_handle_irq(virq);
99 }
100 }
101}
102
103static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
104{
105 u32 offset, reg_offset, bit_pos;
106 struct keystone_pcie *ks_pcie;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600107 struct msi_desc *msi;
108 struct pcie_port *pp;
109
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800110 msi = irq_data_get_msi_desc(d);
Jiang Liue39758e2015-07-09 16:00:43 +0800111 pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600112 ks_pcie = to_keystone_pcie(pp);
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800113 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600114 update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
115
116 writel(BIT(bit_pos),
117 ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
118 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
119}
120
121void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
122{
123 u32 reg_offset, bit_pos;
124 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
125
126 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
127 writel(BIT(bit_pos),
128 ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
129}
130
131void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
132{
133 u32 reg_offset, bit_pos;
134 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
135
136 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
137 writel(BIT(bit_pos),
138 ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
139}
140
141static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
142{
143 struct keystone_pcie *ks_pcie;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600144 struct msi_desc *msi;
145 struct pcie_port *pp;
146 u32 offset;
147
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800148 msi = irq_data_get_msi_desc(d);
Jiang Liue39758e2015-07-09 16:00:43 +0800149 pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600150 ks_pcie = to_keystone_pcie(pp);
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800151 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600152
153 /* Mask the end point if PVM implemented */
154 if (IS_ENABLED(CONFIG_PCI_MSI)) {
155 if (msi->msi_attrib.maskbit)
Thomas Gleixner280510f2014-11-23 12:23:20 +0100156 pci_msi_mask_irq(d);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600157 }
158
159 ks_dw_pcie_msi_clear_irq(pp, offset);
160}
161
162static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
163{
164 struct keystone_pcie *ks_pcie;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600165 struct msi_desc *msi;
166 struct pcie_port *pp;
167 u32 offset;
168
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800169 msi = irq_data_get_msi_desc(d);
Jiang Liue39758e2015-07-09 16:00:43 +0800170 pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600171 ks_pcie = to_keystone_pcie(pp);
Jiang Liu40b6d3f2015-06-04 12:13:23 +0800172 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600173
174 /* Mask the end point if PVM implemented */
175 if (IS_ENABLED(CONFIG_PCI_MSI)) {
176 if (msi->msi_attrib.maskbit)
Thomas Gleixner280510f2014-11-23 12:23:20 +0100177 pci_msi_unmask_irq(d);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600178 }
179
180 ks_dw_pcie_msi_set_irq(pp, offset);
181}
182
183static struct irq_chip ks_dw_pcie_msi_irq_chip = {
184 .name = "Keystone-PCIe-MSI-IRQ",
185 .irq_ack = ks_dw_pcie_msi_irq_ack,
186 .irq_mask = ks_dw_pcie_msi_irq_mask,
187 .irq_unmask = ks_dw_pcie_msi_irq_unmask,
188};
189
190static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
191 irq_hw_number_t hwirq)
192{
193 irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
194 handle_level_irq);
195 irq_set_chip_data(irq, domain->host_data);
196 set_irq_flags(irq, IRQF_VALID);
197
198 return 0;
199}
200
Jingoo Han5ba83682014-10-23 11:10:16 +0900201static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600202 .map = ks_dw_pcie_msi_map,
203};
204
Yijing Wangc2791b82014-11-11 17:45:45 -0700205int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600206{
207 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
208 int i;
209
210 pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
211 MAX_MSI_IRQS,
212 &ks_dw_pcie_msi_domain_ops,
213 chip);
214 if (!pp->irq_domain) {
215 dev_err(pp->dev, "irq domain init failed\n");
216 return -ENXIO;
217 }
218
219 for (i = 0; i < MAX_MSI_IRQS; i++)
220 irq_create_mapping(pp->irq_domain, i);
221
222 return 0;
223}
224
225void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
226{
227 int i;
228
229 for (i = 0; i < MAX_LEGACY_IRQS; i++)
230 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
231}
232
233void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
234{
235 struct pcie_port *pp = &ks_pcie->pp;
236 u32 pending;
237 int virq;
238
239 pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
240
241 if (BIT(0) & pending) {
242 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
243 dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
244 virq);
245 generic_handle_irq(virq);
246 }
247
248 /* EOI the INTx interrupt */
249 writel(offset, ks_pcie->va_app_base + IRQ_EOI);
250}
251
252static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
253{
254}
255
256static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
257{
258}
259
260static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
261{
262}
263
264static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
265 .name = "Keystone-PCI-Legacy-IRQ",
266 .irq_ack = ks_dw_pcie_ack_legacy_irq,
267 .irq_mask = ks_dw_pcie_mask_legacy_irq,
268 .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
269};
270
271static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
272 unsigned int irq, irq_hw_number_t hw_irq)
273{
274 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
275 handle_level_irq);
276 irq_set_chip_data(irq, d->host_data);
277 set_irq_flags(irq, IRQF_VALID);
278
279 return 0;
280}
281
282static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
283 .map = ks_dw_pcie_init_legacy_irq_map,
284 .xlate = irq_domain_xlate_onetwocell,
285};
286
287/**
288 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
289 * registers
290 *
291 * Since modification of dbi_cs2 involves different clock domain, read the
292 * status back to ensure the transition is complete.
293 */
294static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
295{
296 u32 val;
297
298 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS),
299 reg_virt + CMD_STATUS);
300
301 do {
302 val = readl(reg_virt + CMD_STATUS);
303 } while (!(val & DBI_CS2_EN_VAL));
304}
305
306/**
307 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
308 *
309 * Since modification of dbi_cs2 involves different clock domain, read the
310 * status back to ensure the transition is complete.
311 */
312static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
313{
314 u32 val;
315
316 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
317 reg_virt + CMD_STATUS);
318
319 do {
320 val = readl(reg_virt + CMD_STATUS);
321 } while (val & DBI_CS2_EN_VAL);
322}
323
324void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
325{
326 struct pcie_port *pp = &ks_pcie->pp;
327 u32 start = pp->mem.start, end = pp->mem.end;
328 int i, tr_size;
329
330 /* Disable BARs for inbound access */
331 ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
332 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
333 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
334 ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
335
336 /* Set outbound translation size per window division */
337 writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
338
339 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
340
341 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
342 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
343 writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
344 writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
345 start += tr_size;
346 }
347
348 /* Enable OB translation */
349 writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
350 ks_pcie->va_app_base + CMD_STATUS);
351}
352
353/**
354 * ks_pcie_cfg_setup() - Set up configuration space address for a device
355 *
356 * @ks_pcie: ptr to keystone_pcie structure
357 * @bus: Bus number the device is residing on
358 * @devfn: device, function number info
359 *
360 * Forms and returns the address of configuration space mapped in PCIESS
361 * address space 0. Also configures CFG_SETUP for remote configuration space
362 * access.
363 *
364 * The address space has two regions to access configuration - local and remote.
365 * We access local region for bus 0 (as RC is attached on bus 0) and remote
366 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
367 * we will do TYPE 0 access as it will be on our secondary bus (logical).
368 * CFG_SETUP is needed only for remote configuration access.
369 */
370static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
371 unsigned int devfn)
372{
373 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
374 struct pcie_port *pp = &ks_pcie->pp;
375 u32 regval;
376
377 if (bus == 0)
378 return pp->dbi_base;
379
380 regval = (bus << 16) | (device << 8) | function;
381
382 /*
383 * Since Bus#1 will be a virtual bus, we need to have TYPE0
384 * access only.
385 * TYPE 1
386 */
387 if (bus != 1)
388 regval |= BIT(24);
389
390 writel(regval, ks_pcie->va_app_base + CFG_SETUP);
391 return pp->va_cfg0_base;
392}
393
394int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
395 unsigned int devfn, int where, int size, u32 *val)
396{
397 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
398 u8 bus_num = bus->number;
399 void __iomem *addr;
400
401 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
402
403 return dw_pcie_cfg_read(addr + (where & ~0x3), where, size, val);
404}
405
406int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
407 unsigned int devfn, int where, int size, u32 val)
408{
409 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
410 u8 bus_num = bus->number;
411 void __iomem *addr;
412
413 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
414
415 return dw_pcie_cfg_write(addr + (where & ~0x3), where, size, val);
416}
417
418/**
419 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
420 *
421 * This sets BAR0 to enable inbound access for MSI_IRQ register
422 */
423void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
424{
425 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
426
427 /* Configure and set up BAR0 */
428 ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
429
430 /* Enable BAR0 */
431 writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
432 writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
433
434 ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
435
436 /*
437 * For BAR0, just setting bus address for inbound writes (MSI) should
438 * be sufficient. Use physical address to avoid any conflicts.
439 */
440 writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
441}
442
443/**
444 * ks_dw_pcie_link_up() - Check if link up
445 */
446int ks_dw_pcie_link_up(struct pcie_port *pp)
447{
448 u32 val = readl(pp->dbi_base + DEBUG0);
449
450 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
451}
452
453void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
454{
455 u32 val;
456
457 /* Disable Link training */
458 val = readl(ks_pcie->va_app_base + CMD_STATUS);
459 val &= ~LTSSM_EN_VAL;
460 writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
461
462 /* Initiate Link Training */
463 val = readl(ks_pcie->va_app_base + CMD_STATUS);
464 writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS);
465}
466
467/**
468 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
469 *
470 * Ioremap the register resources, initialize legacy irq domain
471 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
472 * PCI host controller.
473 */
474int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
475 struct device_node *msi_intc_np)
476{
477 struct pcie_port *pp = &ks_pcie->pp;
478 struct platform_device *pdev = to_platform_device(pp->dev);
479 struct resource *res;
480
481 /* Index 0 is the config reg. space address */
482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
483 pp->dbi_base = devm_ioremap_resource(pp->dev, res);
484 if (IS_ERR(pp->dbi_base))
485 return PTR_ERR(pp->dbi_base);
486
487 /*
488 * We set these same and is used in pcie rd/wr_other_conf
489 * functions
490 */
491 pp->va_cfg0_base = pp->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
492 pp->va_cfg1_base = pp->va_cfg0_base;
493
494 /* Index 1 is the application reg. space address */
495 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600496 ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
497 if (IS_ERR(ks_pcie->va_app_base))
498 return PTR_ERR(ks_pcie->va_app_base);
499
Bjorn Helgaasf76ea572015-04-09 14:34:10 -0500500 ks_pcie->app = *res;
501
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -0600502 /* Create legacy IRQ domain */
503 ks_pcie->legacy_irq_domain =
504 irq_domain_add_linear(ks_pcie->legacy_intc_np,
505 MAX_LEGACY_IRQS,
506 &ks_dw_pcie_legacy_irq_domain_ops,
507 NULL);
508 if (!ks_pcie->legacy_irq_domain) {
509 dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
510 return -EINVAL;
511 }
512
513 return dw_pcie_host_init(pp);
514}