Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* sun3lance.c: Ethernet driver for SUN3 Lance chip */ |
| 2 | /* |
| 3 | |
| 4 | Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net). |
| 5 | This driver is a part of the linux kernel, and is thus distributed |
| 6 | under the GNU General Public License. |
| 7 | |
| 8 | The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically |
| 9 | true for the correct IRQ and address of the lance registers. They |
| 10 | have not been widely tested, however. What we probably need is a |
| 11 | "proper" way to search for a device in the sun3's prom, but, alas, |
| 12 | linux has no such thing. |
| 13 | |
| 14 | This driver is largely based on atarilance.c, by Roman Hodek. Other |
| 15 | sources of inspiration were the NetBSD sun3 am7990 driver, and the |
| 16 | linux sparc lance driver (sunlance.c). |
| 17 | |
| 18 | There are more assumptions made throughout this driver, it almost |
| 19 | certainly still needs work, but it does work at least for RARP/BOOTP and |
| 20 | mounting the root NFS filesystem. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | static char *version = "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n"; |
| 25 | |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/stddef.h> |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/string.h> |
| 30 | #include <linux/errno.h> |
| 31 | #include <linux/slab.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/init.h> |
| 34 | #include <linux/ioport.h> |
| 35 | #include <linux/delay.h> |
| 36 | #include <linux/netdevice.h> |
| 37 | #include <linux/etherdevice.h> |
| 38 | #include <linux/skbuff.h> |
| 39 | #include <linux/bitops.h> |
| 40 | |
| 41 | #include <asm/setup.h> |
| 42 | #include <asm/irq.h> |
| 43 | #include <asm/io.h> |
| 44 | #include <asm/pgtable.h> |
| 45 | #include <asm/dvma.h> |
| 46 | #include <asm/idprom.h> |
| 47 | #include <asm/machines.h> |
| 48 | |
| 49 | #ifdef CONFIG_SUN3 |
| 50 | #include <asm/sun3mmu.h> |
| 51 | #else |
| 52 | #include <asm/sun3xprom.h> |
| 53 | #endif |
| 54 | |
| 55 | /* sun3/60 addr/irq for the lance chip. If your sun is different, |
| 56 | change this. */ |
| 57 | #define LANCE_OBIO 0x120000 |
| 58 | #define LANCE_IRQ IRQ3 |
| 59 | |
| 60 | /* Debug level: |
| 61 | * 0 = silent, print only serious errors |
| 62 | * 1 = normal, print error messages |
| 63 | * 2 = debug, print debug infos |
| 64 | * 3 = debug, print even more debug infos (packet data) |
| 65 | */ |
| 66 | |
| 67 | #define LANCE_DEBUG 0 |
| 68 | |
| 69 | #ifdef LANCE_DEBUG |
| 70 | static int lance_debug = LANCE_DEBUG; |
| 71 | #else |
| 72 | static int lance_debug = 1; |
| 73 | #endif |
| 74 | MODULE_PARM(lance_debug, "i"); |
| 75 | MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)"); |
| 76 | MODULE_LICENSE("GPL"); |
| 77 | |
| 78 | #define DPRINTK(n,a) \ |
| 79 | do { \ |
| 80 | if (lance_debug >= n) \ |
| 81 | printk a; \ |
| 82 | } while( 0 ) |
| 83 | |
| 84 | |
| 85 | /* we're only using 32k of memory, so we use 4 TX |
| 86 | buffers and 16 RX buffers. These values are expressed as log2. */ |
| 87 | |
| 88 | #define TX_LOG_RING_SIZE 3 |
| 89 | #define RX_LOG_RING_SIZE 5 |
| 90 | |
| 91 | /* These are the derived values */ |
| 92 | |
| 93 | #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE) |
| 94 | #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5) |
| 95 | #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
| 96 | |
| 97 | #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE) |
| 98 | #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5) |
| 99 | #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
| 100 | |
| 101 | /* Definitions for packet buffer access: */ |
| 102 | #define PKT_BUF_SZ 1544 |
| 103 | |
| 104 | /* Get the address of a packet buffer corresponding to a given buffer head */ |
| 105 | #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base) |
| 106 | |
| 107 | |
| 108 | /* The LANCE Rx and Tx ring descriptors. */ |
| 109 | struct lance_rx_head { |
| 110 | unsigned short base; /* Low word of base addr */ |
| 111 | volatile unsigned char flag; |
| 112 | unsigned char base_hi; /* High word of base addr (unused) */ |
| 113 | short buf_length; /* This length is 2s complement! */ |
| 114 | volatile short msg_length; /* This length is "normal". */ |
| 115 | }; |
| 116 | |
| 117 | struct lance_tx_head { |
| 118 | unsigned short base; /* Low word of base addr */ |
| 119 | volatile unsigned char flag; |
| 120 | unsigned char base_hi; /* High word of base addr (unused) */ |
| 121 | short length; /* Length is 2s complement! */ |
| 122 | volatile short misc; |
| 123 | }; |
| 124 | |
| 125 | /* The LANCE initialization block, described in databook. */ |
| 126 | struct lance_init_block { |
| 127 | unsigned short mode; /* Pre-set mode */ |
| 128 | unsigned char hwaddr[6]; /* Physical ethernet address */ |
| 129 | unsigned int filter[2]; /* Multicast filter (unused). */ |
| 130 | /* Receive and transmit ring base, along with length bits. */ |
| 131 | unsigned short rdra; |
| 132 | unsigned short rlen; |
| 133 | unsigned short tdra; |
| 134 | unsigned short tlen; |
| 135 | unsigned short pad[4]; /* is thie needed? */ |
| 136 | }; |
| 137 | |
| 138 | /* The whole layout of the Lance shared memory */ |
| 139 | struct lance_memory { |
| 140 | struct lance_init_block init; |
| 141 | struct lance_tx_head tx_head[TX_RING_SIZE]; |
| 142 | struct lance_rx_head rx_head[RX_RING_SIZE]; |
| 143 | char rx_data[RX_RING_SIZE][PKT_BUF_SZ]; |
| 144 | char tx_data[TX_RING_SIZE][PKT_BUF_SZ]; |
| 145 | }; |
| 146 | |
| 147 | /* The driver's private device structure */ |
| 148 | |
| 149 | struct lance_private { |
| 150 | volatile unsigned short *iobase; |
| 151 | struct lance_memory *mem; |
| 152 | int new_rx, new_tx; /* The next free ring entry */ |
| 153 | int old_tx, old_rx; /* ring entry to be processed */ |
| 154 | struct net_device_stats stats; |
| 155 | /* These two must be longs for set_bit() */ |
| 156 | long tx_full; |
| 157 | long lock; |
| 158 | }; |
| 159 | |
| 160 | /* I/O register access macros */ |
| 161 | |
| 162 | #define MEM lp->mem |
| 163 | #define DREG lp->iobase[0] |
| 164 | #define AREG lp->iobase[1] |
| 165 | #define REGA(a) ( AREG = (a), DREG ) |
| 166 | |
| 167 | /* Definitions for the Lance */ |
| 168 | |
| 169 | /* tx_head flags */ |
| 170 | #define TMD1_ENP 0x01 /* end of packet */ |
| 171 | #define TMD1_STP 0x02 /* start of packet */ |
| 172 | #define TMD1_DEF 0x04 /* deferred */ |
| 173 | #define TMD1_ONE 0x08 /* one retry needed */ |
| 174 | #define TMD1_MORE 0x10 /* more than one retry needed */ |
| 175 | #define TMD1_ERR 0x40 /* error summary */ |
| 176 | #define TMD1_OWN 0x80 /* ownership (set: chip owns) */ |
| 177 | |
| 178 | #define TMD1_OWN_CHIP TMD1_OWN |
| 179 | #define TMD1_OWN_HOST 0 |
| 180 | |
| 181 | /* tx_head misc field */ |
| 182 | #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */ |
| 183 | #define TMD3_RTRY 0x0400 /* failed after 16 retries */ |
| 184 | #define TMD3_LCAR 0x0800 /* carrier lost */ |
| 185 | #define TMD3_LCOL 0x1000 /* late collision */ |
| 186 | #define TMD3_UFLO 0x4000 /* underflow (late memory) */ |
| 187 | #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */ |
| 188 | |
| 189 | /* rx_head flags */ |
| 190 | #define RMD1_ENP 0x01 /* end of packet */ |
| 191 | #define RMD1_STP 0x02 /* start of packet */ |
| 192 | #define RMD1_BUFF 0x04 /* buffer error */ |
| 193 | #define RMD1_CRC 0x08 /* CRC error */ |
| 194 | #define RMD1_OFLO 0x10 /* overflow */ |
| 195 | #define RMD1_FRAM 0x20 /* framing error */ |
| 196 | #define RMD1_ERR 0x40 /* error summary */ |
| 197 | #define RMD1_OWN 0x80 /* ownership (set: ship owns) */ |
| 198 | |
| 199 | #define RMD1_OWN_CHIP RMD1_OWN |
| 200 | #define RMD1_OWN_HOST 0 |
| 201 | |
| 202 | /* register names */ |
| 203 | #define CSR0 0 /* mode/status */ |
| 204 | #define CSR1 1 /* init block addr (low) */ |
| 205 | #define CSR2 2 /* init block addr (high) */ |
| 206 | #define CSR3 3 /* misc */ |
| 207 | #define CSR8 8 /* address filter */ |
| 208 | #define CSR15 15 /* promiscuous mode */ |
| 209 | |
| 210 | /* CSR0 */ |
| 211 | /* (R=readable, W=writeable, S=set on write, C=clear on write) */ |
| 212 | #define CSR0_INIT 0x0001 /* initialize (RS) */ |
| 213 | #define CSR0_STRT 0x0002 /* start (RS) */ |
| 214 | #define CSR0_STOP 0x0004 /* stop (RS) */ |
| 215 | #define CSR0_TDMD 0x0008 /* transmit demand (RS) */ |
| 216 | #define CSR0_TXON 0x0010 /* transmitter on (R) */ |
| 217 | #define CSR0_RXON 0x0020 /* receiver on (R) */ |
| 218 | #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ |
| 219 | #define CSR0_INTR 0x0080 /* interrupt active (R) */ |
| 220 | #define CSR0_IDON 0x0100 /* initialization done (RC) */ |
| 221 | #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ |
| 222 | #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */ |
| 223 | #define CSR0_MERR 0x0800 /* memory error (RC) */ |
| 224 | #define CSR0_MISS 0x1000 /* missed frame (RC) */ |
| 225 | #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */ |
| 226 | #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */ |
| 227 | #define CSR0_ERR 0x8000 /* error (RC) */ |
| 228 | |
| 229 | /* CSR3 */ |
| 230 | #define CSR3_BCON 0x0001 /* byte control */ |
| 231 | #define CSR3_ACON 0x0002 /* ALE control */ |
| 232 | #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */ |
| 233 | |
| 234 | /***************************** Prototypes *****************************/ |
| 235 | |
| 236 | static int lance_probe( struct net_device *dev); |
| 237 | static int lance_open( struct net_device *dev ); |
| 238 | static void lance_init_ring( struct net_device *dev ); |
| 239 | static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev ); |
| 240 | static irqreturn_t lance_interrupt( int irq, void *dev_id, struct pt_regs *fp ); |
| 241 | static int lance_rx( struct net_device *dev ); |
| 242 | static int lance_close( struct net_device *dev ); |
| 243 | static struct net_device_stats *lance_get_stats( struct net_device *dev ); |
| 244 | static void set_multicast_list( struct net_device *dev ); |
| 245 | |
| 246 | /************************* End of Prototypes **************************/ |
| 247 | |
| 248 | struct net_device * __init sun3lance_probe(int unit) |
| 249 | { |
| 250 | struct net_device *dev; |
| 251 | static int found; |
| 252 | int err = -ENODEV; |
| 253 | |
| 254 | /* check that this machine has an onboard lance */ |
| 255 | switch(idprom->id_machtype) { |
| 256 | case SM_SUN3|SM_3_50: |
| 257 | case SM_SUN3|SM_3_60: |
| 258 | case SM_SUN3X|SM_3_80: |
| 259 | /* these machines have lance */ |
| 260 | break; |
| 261 | |
| 262 | default: |
| 263 | return ERR_PTR(-ENODEV); |
| 264 | } |
| 265 | |
| 266 | if (found) |
| 267 | return ERR_PTR(-ENODEV); |
| 268 | |
| 269 | dev = alloc_etherdev(sizeof(struct lance_private)); |
| 270 | if (!dev) |
| 271 | return ERR_PTR(-ENOMEM); |
| 272 | if (unit >= 0) { |
| 273 | sprintf(dev->name, "eth%d", unit); |
| 274 | netdev_boot_setup_check(dev); |
| 275 | } |
| 276 | SET_MODULE_OWNER(dev); |
| 277 | |
| 278 | if (!lance_probe(dev)) |
| 279 | goto out; |
| 280 | |
| 281 | err = register_netdev(dev); |
| 282 | if (err) |
| 283 | goto out1; |
| 284 | found = 1; |
| 285 | return dev; |
| 286 | |
| 287 | out1: |
| 288 | #ifdef CONFIG_SUN3 |
| 289 | iounmap((void *)dev->base_addr); |
| 290 | #endif |
| 291 | out: |
| 292 | free_netdev(dev); |
| 293 | return ERR_PTR(err); |
| 294 | } |
| 295 | |
| 296 | static int __init lance_probe( struct net_device *dev) |
| 297 | { |
| 298 | unsigned long ioaddr; |
| 299 | |
| 300 | struct lance_private *lp; |
| 301 | int i; |
| 302 | static int did_version; |
| 303 | volatile unsigned short *ioaddr_probe; |
| 304 | unsigned short tmp1, tmp2; |
| 305 | |
| 306 | #ifdef CONFIG_SUN3 |
| 307 | ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE); |
| 308 | if (!ioaddr) |
| 309 | return 0; |
| 310 | #else |
| 311 | ioaddr = SUN3X_LANCE; |
| 312 | #endif |
| 313 | |
| 314 | /* test to see if there's really a lance here */ |
| 315 | /* (CSRO_INIT shouldn't be readable) */ |
| 316 | |
| 317 | ioaddr_probe = (volatile unsigned short *)ioaddr; |
| 318 | tmp1 = ioaddr_probe[0]; |
| 319 | tmp2 = ioaddr_probe[1]; |
| 320 | |
| 321 | ioaddr_probe[1] = CSR0; |
| 322 | ioaddr_probe[0] = CSR0_INIT | CSR0_STOP; |
| 323 | |
| 324 | if(ioaddr_probe[0] != CSR0_STOP) { |
| 325 | ioaddr_probe[0] = tmp1; |
| 326 | ioaddr_probe[1] = tmp2; |
| 327 | |
| 328 | #ifdef CONFIG_SUN3 |
| 329 | iounmap((void *)ioaddr); |
| 330 | #endif |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | lp = netdev_priv(dev); |
| 335 | |
| 336 | /* XXX - leak? */ |
| 337 | MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000); |
| 338 | |
| 339 | lp->iobase = (volatile unsigned short *)ioaddr; |
| 340 | dev->base_addr = (unsigned long)ioaddr; /* informational only */ |
| 341 | |
| 342 | REGA(CSR0) = CSR0_STOP; |
| 343 | |
| 344 | request_irq(LANCE_IRQ, lance_interrupt, SA_INTERRUPT, "SUN3 Lance", dev); |
| 345 | dev->irq = (unsigned short)LANCE_IRQ; |
| 346 | |
| 347 | |
| 348 | printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ", |
| 349 | dev->name, |
| 350 | (unsigned long)ioaddr, |
| 351 | (unsigned long)MEM, |
| 352 | dev->irq); |
| 353 | |
| 354 | /* copy in the ethernet address from the prom */ |
| 355 | for(i = 0; i < 6 ; i++) |
| 356 | dev->dev_addr[i] = idprom->id_ethaddr[i]; |
| 357 | |
| 358 | /* tell the card it's ether address, bytes swapped */ |
| 359 | MEM->init.hwaddr[0] = dev->dev_addr[1]; |
| 360 | MEM->init.hwaddr[1] = dev->dev_addr[0]; |
| 361 | MEM->init.hwaddr[2] = dev->dev_addr[3]; |
| 362 | MEM->init.hwaddr[3] = dev->dev_addr[2]; |
| 363 | MEM->init.hwaddr[4] = dev->dev_addr[5]; |
| 364 | MEM->init.hwaddr[5] = dev->dev_addr[4]; |
| 365 | |
| 366 | for( i = 0; i < 6; ++i ) |
| 367 | printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" ); |
| 368 | |
| 369 | MEM->init.mode = 0x0000; |
| 370 | MEM->init.filter[0] = 0x00000000; |
| 371 | MEM->init.filter[1] = 0x00000000; |
| 372 | MEM->init.rdra = dvma_vtob(MEM->rx_head); |
| 373 | MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | |
| 374 | (dvma_vtob(MEM->rx_head) >> 16); |
| 375 | MEM->init.tdra = dvma_vtob(MEM->tx_head); |
| 376 | MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | |
| 377 | (dvma_vtob(MEM->tx_head) >> 16); |
| 378 | |
| 379 | DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n", |
| 380 | dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head), |
| 381 | (dvma_vtob(MEM->tx_head)))); |
| 382 | |
| 383 | if (did_version++ == 0) |
| 384 | printk( version ); |
| 385 | |
| 386 | /* The LANCE-specific entries in the device structure. */ |
| 387 | dev->open = &lance_open; |
| 388 | dev->hard_start_xmit = &lance_start_xmit; |
| 389 | dev->stop = &lance_close; |
| 390 | dev->get_stats = &lance_get_stats; |
| 391 | dev->set_multicast_list = &set_multicast_list; |
| 392 | dev->set_mac_address = 0; |
| 393 | // KLUDGE -- REMOVE ME |
| 394 | set_bit(__LINK_STATE_PRESENT, &dev->state); |
| 395 | |
| 396 | |
| 397 | memset( &lp->stats, 0, sizeof(lp->stats) ); |
| 398 | |
| 399 | return 1; |
| 400 | } |
| 401 | |
| 402 | static int lance_open( struct net_device *dev ) |
| 403 | { |
| 404 | struct lance_private *lp = netdev_priv(dev); |
| 405 | int i; |
| 406 | |
| 407 | DPRINTK( 2, ( "%s: lance_open()\n", dev->name )); |
| 408 | |
| 409 | REGA(CSR0) = CSR0_STOP; |
| 410 | |
| 411 | lance_init_ring(dev); |
| 412 | |
| 413 | /* From now on, AREG is kept to point to CSR0 */ |
| 414 | REGA(CSR0) = CSR0_INIT; |
| 415 | |
| 416 | i = 1000000; |
| 417 | while (--i > 0) |
| 418 | if (DREG & CSR0_IDON) |
| 419 | break; |
| 420 | if (i < 0 || (DREG & CSR0_ERR)) { |
| 421 | DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n", |
| 422 | dev->name, i, DREG )); |
| 423 | DREG = CSR0_STOP; |
| 424 | return( -EIO ); |
| 425 | } |
| 426 | |
| 427 | DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; |
| 428 | |
| 429 | netif_start_queue(dev); |
| 430 | |
| 431 | DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG )); |
| 432 | |
| 433 | return( 0 ); |
| 434 | } |
| 435 | |
| 436 | |
| 437 | /* Initialize the LANCE Rx and Tx rings. */ |
| 438 | |
| 439 | static void lance_init_ring( struct net_device *dev ) |
| 440 | { |
| 441 | struct lance_private *lp = netdev_priv(dev); |
| 442 | int i; |
| 443 | |
| 444 | lp->lock = 0; |
| 445 | lp->tx_full = 0; |
| 446 | lp->new_rx = lp->new_tx = 0; |
| 447 | lp->old_rx = lp->old_tx = 0; |
| 448 | |
| 449 | for( i = 0; i < TX_RING_SIZE; i++ ) { |
| 450 | MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]); |
| 451 | MEM->tx_head[i].flag = 0; |
| 452 | MEM->tx_head[i].base_hi = |
| 453 | (dvma_vtob(MEM->tx_data[i])) >>16; |
| 454 | MEM->tx_head[i].length = 0; |
| 455 | MEM->tx_head[i].misc = 0; |
| 456 | } |
| 457 | |
| 458 | for( i = 0; i < RX_RING_SIZE; i++ ) { |
| 459 | MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]); |
| 460 | MEM->rx_head[i].flag = RMD1_OWN_CHIP; |
| 461 | MEM->rx_head[i].base_hi = |
| 462 | (dvma_vtob(MEM->rx_data[i])) >> 16; |
| 463 | MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000; |
| 464 | MEM->rx_head[i].msg_length = 0; |
| 465 | } |
| 466 | |
| 467 | /* tell the card it's ether address, bytes swapped */ |
| 468 | MEM->init.hwaddr[0] = dev->dev_addr[1]; |
| 469 | MEM->init.hwaddr[1] = dev->dev_addr[0]; |
| 470 | MEM->init.hwaddr[2] = dev->dev_addr[3]; |
| 471 | MEM->init.hwaddr[3] = dev->dev_addr[2]; |
| 472 | MEM->init.hwaddr[4] = dev->dev_addr[5]; |
| 473 | MEM->init.hwaddr[5] = dev->dev_addr[4]; |
| 474 | |
| 475 | MEM->init.mode = 0x0000; |
| 476 | MEM->init.filter[0] = 0x00000000; |
| 477 | MEM->init.filter[1] = 0x00000000; |
| 478 | MEM->init.rdra = dvma_vtob(MEM->rx_head); |
| 479 | MEM->init.rlen = (RX_LOG_RING_SIZE << 13) | |
| 480 | (dvma_vtob(MEM->rx_head) >> 16); |
| 481 | MEM->init.tdra = dvma_vtob(MEM->tx_head); |
| 482 | MEM->init.tlen = (TX_LOG_RING_SIZE << 13) | |
| 483 | (dvma_vtob(MEM->tx_head) >> 16); |
| 484 | |
| 485 | |
| 486 | /* tell the lance the address of its init block */ |
| 487 | REGA(CSR1) = dvma_vtob(&(MEM->init)); |
| 488 | REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16; |
| 489 | |
| 490 | #ifdef CONFIG_SUN3X |
| 491 | REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; |
| 492 | #else |
| 493 | REGA(CSR3) = CSR3_BSWP; |
| 494 | #endif |
| 495 | |
| 496 | } |
| 497 | |
| 498 | |
| 499 | static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev ) |
| 500 | { |
| 501 | struct lance_private *lp = netdev_priv(dev); |
| 502 | int entry, len; |
| 503 | struct lance_tx_head *head; |
| 504 | unsigned long flags; |
| 505 | |
| 506 | DPRINTK( 1, ( "%s: transmit start.\n", |
| 507 | dev->name)); |
| 508 | |
| 509 | /* Transmitter timeout, serious problems. */ |
| 510 | if (netif_queue_stopped(dev)) { |
| 511 | int tickssofar = jiffies - dev->trans_start; |
| 512 | if (tickssofar < 20) |
| 513 | return( 1 ); |
| 514 | |
| 515 | DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n", |
| 516 | dev->name, DREG )); |
| 517 | DREG = CSR0_STOP; |
| 518 | /* |
| 519 | * Always set BSWP after a STOP as STOP puts it back into |
| 520 | * little endian mode. |
| 521 | */ |
| 522 | REGA(CSR3) = CSR3_BSWP; |
| 523 | lp->stats.tx_errors++; |
| 524 | |
| 525 | if(lance_debug >= 2) { |
| 526 | int i; |
| 527 | printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n", |
| 528 | lp->old_tx, lp->new_tx, |
| 529 | lp->tx_full ? " (full)" : "", |
| 530 | lp->new_rx ); |
| 531 | for( i = 0 ; i < RX_RING_SIZE; i++ ) |
| 532 | printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n", |
| 533 | i, MEM->rx_head[i].base, |
| 534 | -MEM->rx_head[i].buf_length, |
| 535 | MEM->rx_head[i].msg_length); |
| 536 | for( i = 0 ; i < TX_RING_SIZE; i++ ) |
| 537 | printk("tx #%d: base=%04x len=%04x misc=%04x\n", |
| 538 | i, MEM->tx_head[i].base, |
| 539 | -MEM->tx_head[i].length, |
| 540 | MEM->tx_head[i].misc ); |
| 541 | } |
| 542 | |
| 543 | lance_init_ring(dev); |
| 544 | REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; |
| 545 | |
| 546 | netif_start_queue(dev); |
| 547 | dev->trans_start = jiffies; |
| 548 | |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | |
| 553 | /* Block a timer-based transmit from overlapping. This could better be |
| 554 | done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */ |
| 555 | |
| 556 | /* Block a timer-based transmit from overlapping with us by |
| 557 | stopping the queue for a bit... */ |
| 558 | |
| 559 | netif_stop_queue(dev); |
| 560 | |
| 561 | if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) { |
| 562 | printk( "%s: tx queue lock!.\n", dev->name); |
| 563 | /* don't clear dev->tbusy flag. */ |
| 564 | return 1; |
| 565 | } |
| 566 | |
| 567 | AREG = CSR0; |
| 568 | DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n", |
| 569 | dev->name, DREG )); |
| 570 | |
| 571 | #ifdef CONFIG_SUN3X |
| 572 | /* this weirdness doesn't appear on sun3... */ |
| 573 | if(!(DREG & CSR0_INIT)) { |
| 574 | DPRINTK( 1, ("INIT not set, reinitializing...\n")); |
| 575 | REGA( CSR0 ) = CSR0_STOP; |
| 576 | lance_init_ring(dev); |
| 577 | REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; |
| 578 | } |
| 579 | #endif |
| 580 | |
| 581 | /* Fill in a Tx ring entry */ |
| 582 | #if 0 |
| 583 | if (lance_debug >= 2) { |
| 584 | u_char *p; |
| 585 | int i; |
| 586 | printk( "%s: TX pkt %d type 0x%04x from ", dev->name, |
| 587 | lp->new_tx, ((u_short *)skb->data)[6]); |
| 588 | for( p = &((u_char *)skb->data)[6], i = 0; i < 6; i++ ) |
| 589 | printk("%02x%s", *p++, i != 5 ? ":" : "" ); |
| 590 | printk(" to "); |
| 591 | for( p = (u_char *)skb->data, i = 0; i < 6; i++ ) |
| 592 | printk("%02x%s", *p++, i != 5 ? ":" : "" ); |
| 593 | printk(" data at 0x%08x len %d\n", (int)skb->data, |
| 594 | (int)skb->len ); |
| 595 | } |
| 596 | #endif |
| 597 | /* We're not prepared for the int until the last flags are set/reset. |
| 598 | * And the int may happen already after setting the OWN_CHIP... */ |
| 599 | local_irq_save(flags); |
| 600 | |
| 601 | /* Mask to ring buffer boundary. */ |
| 602 | entry = lp->new_tx; |
| 603 | head = &(MEM->tx_head[entry]); |
| 604 | |
| 605 | /* Caution: the write order is important here, set the "ownership" bits |
| 606 | * last. |
| 607 | */ |
| 608 | |
| 609 | /* the sun3's lance needs it's buffer padded to the minimum |
| 610 | size */ |
| 611 | len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN; |
| 612 | |
| 613 | // head->length = -len; |
| 614 | head->length = (-len) | 0xf000; |
| 615 | head->misc = 0; |
| 616 | |
| 617 | memcpy( PKTBUF_ADDR(head), (void *)skb->data, skb->len ); |
| 618 | if (len != skb->len) |
| 619 | memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len); |
| 620 | |
| 621 | head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP; |
| 622 | lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK; |
| 623 | lp->stats.tx_bytes += skb->len; |
| 624 | |
| 625 | /* Trigger an immediate send poll. */ |
| 626 | REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; |
| 627 | AREG = CSR0; |
| 628 | DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n", |
| 629 | dev->name, DREG )); |
| 630 | dev->trans_start = jiffies; |
| 631 | dev_kfree_skb( skb ); |
| 632 | |
| 633 | lp->lock = 0; |
| 634 | if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) == |
| 635 | TMD1_OWN_HOST) |
| 636 | netif_start_queue(dev); |
| 637 | |
| 638 | local_irq_restore(flags); |
| 639 | |
| 640 | return 0; |
| 641 | } |
| 642 | |
| 643 | /* The LANCE interrupt handler. */ |
| 644 | |
| 645 | static irqreturn_t lance_interrupt( int irq, void *dev_id, struct pt_regs *fp) |
| 646 | { |
| 647 | struct net_device *dev = dev_id; |
| 648 | struct lance_private *lp = netdev_priv(dev); |
| 649 | int csr0; |
| 650 | static int in_interrupt; |
| 651 | |
| 652 | if (dev == NULL) { |
| 653 | DPRINTK( 1, ( "lance_interrupt(): invalid dev_id\n" )); |
| 654 | return IRQ_NONE; |
| 655 | } |
| 656 | |
| 657 | if (in_interrupt) |
| 658 | DPRINTK( 2, ( "%s: Re-entering the interrupt handler.\n", dev->name )); |
| 659 | in_interrupt = 1; |
| 660 | |
| 661 | still_more: |
| 662 | flush_cache_all(); |
| 663 | |
| 664 | AREG = CSR0; |
| 665 | csr0 = DREG; |
| 666 | |
| 667 | /* ack interrupts */ |
| 668 | DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); |
| 669 | |
| 670 | /* clear errors */ |
| 671 | if(csr0 & CSR0_ERR) |
| 672 | DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS; |
| 673 | |
| 674 | |
| 675 | DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n", |
| 676 | dev->name, csr0, DREG )); |
| 677 | |
| 678 | if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ |
| 679 | int old_tx = lp->old_tx; |
| 680 | |
| 681 | // if(lance_debug >= 3) { |
| 682 | // int i; |
| 683 | // |
| 684 | // printk("%s: tx int\n", dev->name); |
| 685 | // |
| 686 | // for(i = 0; i < TX_RING_SIZE; i++) |
| 687 | // printk("ring %d flag=%04x\n", i, |
| 688 | // MEM->tx_head[i].flag); |
| 689 | // } |
| 690 | |
| 691 | while( old_tx != lp->new_tx) { |
| 692 | struct lance_tx_head *head = &(MEM->tx_head[old_tx]); |
| 693 | |
| 694 | DPRINTK(3, ("on tx_ring %d\n", old_tx)); |
| 695 | |
| 696 | if (head->flag & TMD1_OWN_CHIP) |
| 697 | break; /* It still hasn't been Txed */ |
| 698 | |
| 699 | if (head->flag & TMD1_ERR) { |
| 700 | int status = head->misc; |
| 701 | lp->stats.tx_errors++; |
| 702 | if (status & TMD3_RTRY) lp->stats.tx_aborted_errors++; |
| 703 | if (status & TMD3_LCAR) lp->stats.tx_carrier_errors++; |
| 704 | if (status & TMD3_LCOL) lp->stats.tx_window_errors++; |
| 705 | if (status & (TMD3_UFLO | TMD3_BUFF)) { |
| 706 | lp->stats.tx_fifo_errors++; |
| 707 | printk("%s: Tx FIFO error\n", |
| 708 | dev->name); |
| 709 | REGA(CSR0) = CSR0_STOP; |
| 710 | REGA(CSR3) = CSR3_BSWP; |
| 711 | lance_init_ring(dev); |
| 712 | REGA(CSR0) = CSR0_STRT | CSR0_INEA; |
| 713 | return IRQ_HANDLED; |
| 714 | } |
| 715 | } else if(head->flag & (TMD1_ENP | TMD1_STP)) { |
| 716 | |
| 717 | head->flag &= ~(TMD1_ENP | TMD1_STP); |
| 718 | if(head->flag & (TMD1_ONE | TMD1_MORE)) |
| 719 | lp->stats.collisions++; |
| 720 | |
| 721 | lp->stats.tx_packets++; |
| 722 | DPRINTK(3, ("cleared tx ring %d\n", old_tx)); |
| 723 | } |
| 724 | old_tx = (old_tx +1) & TX_RING_MOD_MASK; |
| 725 | } |
| 726 | |
| 727 | lp->old_tx = old_tx; |
| 728 | } |
| 729 | |
| 730 | |
| 731 | if (netif_queue_stopped(dev)) { |
| 732 | /* The ring is no longer full, clear tbusy. */ |
| 733 | netif_start_queue(dev); |
| 734 | netif_wake_queue(dev); |
| 735 | } |
| 736 | |
| 737 | if (csr0 & CSR0_RINT) /* Rx interrupt */ |
| 738 | lance_rx( dev ); |
| 739 | |
| 740 | /* Log misc errors. */ |
| 741 | if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */ |
| 742 | if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */ |
| 743 | if (csr0 & CSR0_MERR) { |
| 744 | DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), " |
| 745 | "status %04x.\n", dev->name, csr0 )); |
| 746 | /* Restart the chip. */ |
| 747 | REGA(CSR0) = CSR0_STOP; |
| 748 | REGA(CSR3) = CSR3_BSWP; |
| 749 | lance_init_ring(dev); |
| 750 | REGA(CSR0) = CSR0_STRT | CSR0_INEA; |
| 751 | } |
| 752 | |
| 753 | |
| 754 | /* Clear any other interrupt, and set interrupt enable. */ |
| 755 | // DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR | |
| 756 | // CSR0_IDON | CSR0_INEA; |
| 757 | |
| 758 | REGA(CSR0) = CSR0_INEA; |
| 759 | |
| 760 | if(DREG & (CSR0_RINT | CSR0_TINT)) { |
| 761 | DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG)); |
| 762 | goto still_more; |
| 763 | } |
| 764 | |
| 765 | DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n", |
| 766 | dev->name, DREG )); |
| 767 | in_interrupt = 0; |
| 768 | return IRQ_HANDLED; |
| 769 | } |
| 770 | |
| 771 | /* get packet, toss into skbuff */ |
| 772 | static int lance_rx( struct net_device *dev ) |
| 773 | { |
| 774 | struct lance_private *lp = netdev_priv(dev); |
| 775 | int entry = lp->new_rx; |
| 776 | |
| 777 | /* If we own the next entry, it's a new packet. Send it up. */ |
| 778 | while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) { |
| 779 | struct lance_rx_head *head = &(MEM->rx_head[entry]); |
| 780 | int status = head->flag; |
| 781 | |
| 782 | if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */ |
| 783 | /* There is a tricky error noted by John Murphy, |
| 784 | <murf@perftech.com> to Russ Nelson: Even with |
| 785 | full-sized buffers it's possible for a jabber packet to use two |
| 786 | buffers, with only the last correctly noting the error. */ |
| 787 | if (status & RMD1_ENP) /* Only count a general error at the */ |
| 788 | lp->stats.rx_errors++; /* end of a packet.*/ |
| 789 | if (status & RMD1_FRAM) lp->stats.rx_frame_errors++; |
| 790 | if (status & RMD1_OFLO) lp->stats.rx_over_errors++; |
| 791 | if (status & RMD1_CRC) lp->stats.rx_crc_errors++; |
| 792 | if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++; |
| 793 | head->flag &= (RMD1_ENP|RMD1_STP); |
| 794 | } else { |
| 795 | /* Malloc up new buffer, compatible with net-3. */ |
| 796 | // short pkt_len = head->msg_length;// & 0xfff; |
| 797 | short pkt_len = (head->msg_length & 0xfff) - 4; |
| 798 | struct sk_buff *skb; |
| 799 | |
| 800 | if (pkt_len < 60) { |
| 801 | printk( "%s: Runt packet!\n", dev->name ); |
| 802 | lp->stats.rx_errors++; |
| 803 | } |
| 804 | else { |
| 805 | skb = dev_alloc_skb( pkt_len+2 ); |
| 806 | if (skb == NULL) { |
| 807 | DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n", |
| 808 | dev->name )); |
| 809 | |
| 810 | lp->stats.rx_dropped++; |
| 811 | head->msg_length = 0; |
| 812 | head->flag |= RMD1_OWN_CHIP; |
| 813 | lp->new_rx = (lp->new_rx+1) & |
| 814 | RX_RING_MOD_MASK; |
| 815 | } |
| 816 | |
| 817 | #if 0 |
| 818 | if (lance_debug >= 3) { |
| 819 | u_char *data = PKTBUF_ADDR(head), *p; |
| 820 | printk( "%s: RX pkt %d type 0x%04x from ", dev->name, entry, ((u_short *)data)[6]); |
| 821 | for( p = &data[6], i = 0; i < 6; i++ ) |
| 822 | printk("%02x%s", *p++, i != 5 ? ":" : "" ); |
| 823 | printk(" to "); |
| 824 | for( p = data, i = 0; i < 6; i++ ) |
| 825 | printk("%02x%s", *p++, i != 5 ? ":" : "" ); |
| 826 | printk(" data %02x %02x %02x %02x %02x %02x %02x %02x " |
| 827 | "len %d at %08x\n", |
| 828 | data[15], data[16], data[17], data[18], |
| 829 | data[19], data[20], data[21], data[22], |
| 830 | pkt_len, data); |
| 831 | } |
| 832 | #endif |
| 833 | if (lance_debug >= 3) { |
| 834 | u_char *data = PKTBUF_ADDR(head); |
| 835 | printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len); |
| 836 | } |
| 837 | |
| 838 | |
| 839 | skb->dev = dev; |
| 840 | skb_reserve( skb, 2 ); /* 16 byte align */ |
| 841 | skb_put( skb, pkt_len ); /* Make room */ |
| 842 | // memcpy( skb->data, PKTBUF_ADDR(head), pkt_len ); |
| 843 | eth_copy_and_sum(skb, |
| 844 | PKTBUF_ADDR(head), |
| 845 | pkt_len, 0); |
| 846 | |
| 847 | skb->protocol = eth_type_trans( skb, dev ); |
| 848 | netif_rx( skb ); |
| 849 | dev->last_rx = jiffies; |
| 850 | lp->stats.rx_packets++; |
| 851 | lp->stats.rx_bytes += pkt_len; |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | // head->buf_length = -PKT_BUF_SZ | 0xf000; |
| 856 | head->msg_length = 0; |
| 857 | head->flag = RMD1_OWN_CHIP; |
| 858 | |
| 859 | entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK; |
| 860 | } |
| 861 | |
| 862 | /* From lance.c (Donald Becker): */ |
| 863 | /* We should check that at least two ring entries are free. |
| 864 | If not, we should free one and mark stats->rx_dropped++. */ |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | |
| 870 | static int lance_close( struct net_device *dev ) |
| 871 | { |
| 872 | struct lance_private *lp = netdev_priv(dev); |
| 873 | |
| 874 | netif_stop_queue(dev); |
| 875 | |
| 876 | AREG = CSR0; |
| 877 | |
| 878 | DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n", |
| 879 | dev->name, DREG )); |
| 880 | |
| 881 | /* We stop the LANCE here -- it occasionally polls |
| 882 | memory if we don't. */ |
| 883 | DREG = CSR0_STOP; |
| 884 | return 0; |
| 885 | } |
| 886 | |
| 887 | |
| 888 | static struct net_device_stats *lance_get_stats( struct net_device *dev ) |
| 889 | { |
| 890 | struct lance_private *lp = netdev_priv(dev); |
| 891 | |
| 892 | return &lp->stats; |
| 893 | } |
| 894 | |
| 895 | |
| 896 | /* Set or clear the multicast filter for this adaptor. |
| 897 | num_addrs == -1 Promiscuous mode, receive all packets |
| 898 | num_addrs == 0 Normal mode, clear multicast list |
| 899 | num_addrs > 0 Multicast mode, receive normal and MC packets, and do |
| 900 | best-effort filtering. |
| 901 | */ |
| 902 | |
| 903 | /* completely untested on a sun3 */ |
| 904 | static void set_multicast_list( struct net_device *dev ) |
| 905 | { |
| 906 | struct lance_private *lp = netdev_priv(dev); |
| 907 | |
| 908 | if(netif_queue_stopped(dev)) |
| 909 | /* Only possible if board is already started */ |
| 910 | return; |
| 911 | |
| 912 | /* We take the simple way out and always enable promiscuous mode. */ |
| 913 | DREG = CSR0_STOP; /* Temporarily stop the lance. */ |
| 914 | |
| 915 | if (dev->flags & IFF_PROMISC) { |
| 916 | /* Log any net taps. */ |
| 917 | DPRINTK( 1, ( "%s: Promiscuous mode enabled.\n", dev->name )); |
| 918 | REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */ |
| 919 | } else { |
| 920 | short multicast_table[4]; |
| 921 | int num_addrs = dev->mc_count; |
| 922 | int i; |
| 923 | /* We don't use the multicast table, but rely on upper-layer |
| 924 | * filtering. */ |
| 925 | memset( multicast_table, (num_addrs == 0) ? 0 : -1, |
| 926 | sizeof(multicast_table) ); |
| 927 | for( i = 0; i < 4; i++ ) |
| 928 | REGA( CSR8+i ) = multicast_table[i]; |
| 929 | REGA( CSR15 ) = 0; /* Unset promiscuous mode */ |
| 930 | } |
| 931 | |
| 932 | /* |
| 933 | * Always set BSWP after a STOP as STOP puts it back into |
| 934 | * little endian mode. |
| 935 | */ |
| 936 | REGA( CSR3 ) = CSR3_BSWP; |
| 937 | |
| 938 | /* Resume normal operation and reset AREG to CSR0 */ |
| 939 | REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; |
| 940 | } |
| 941 | |
| 942 | |
| 943 | #ifdef MODULE |
| 944 | |
| 945 | static struct net_device *sun3lance_dev; |
| 946 | |
| 947 | int init_module(void) |
| 948 | { |
| 949 | sun3lance_dev = sun3lance_probe(-1); |
| 950 | if (IS_ERR(sun3lance_dev)) |
| 951 | return PTR_ERR(sun3lance_dev); |
| 952 | return 0; |
| 953 | } |
| 954 | |
| 955 | void cleanup_module(void) |
| 956 | { |
| 957 | unregister_netdev(sun3lance_dev); |
| 958 | #ifdef CONFIG_SUN3 |
| 959 | iounmap((void *)sun3lance_dev->base_addr); |
| 960 | #endif |
| 961 | free_netdev(sun3lance_dev); |
| 962 | } |
| 963 | |
| 964 | #endif /* MODULE */ |
| 965 | |