blob: 6dc08ed950c87dd8f4d7c3d7a9bf31cf84ec651d [file] [log] [blame]
Huang Shijiee46ecda2014-02-24 18:37:42 +08001/*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/errno.h>
15#include <linux/platform_device.h>
16#include <linux/sched.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/timer.h>
24#include <linux/jiffies.h>
25#include <linux/completion.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/spi-nor.h>
29
30/* The registers */
31#define QUADSPI_MCR 0x00
32#define QUADSPI_MCR_RESERVED_SHIFT 16
33#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
34#define QUADSPI_MCR_MDIS_SHIFT 14
35#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
36#define QUADSPI_MCR_CLR_TXF_SHIFT 11
37#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
38#define QUADSPI_MCR_CLR_RXF_SHIFT 10
39#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
40#define QUADSPI_MCR_DDR_EN_SHIFT 7
41#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
42#define QUADSPI_MCR_END_CFG_SHIFT 2
43#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
44#define QUADSPI_MCR_SWRSTHD_SHIFT 1
45#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
46#define QUADSPI_MCR_SWRSTSD_SHIFT 0
47#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
48
49#define QUADSPI_IPCR 0x08
50#define QUADSPI_IPCR_SEQID_SHIFT 24
51#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
52
53#define QUADSPI_BUF0CR 0x10
54#define QUADSPI_BUF1CR 0x14
55#define QUADSPI_BUF2CR 0x18
56#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
57
58#define QUADSPI_BUF3CR 0x1c
59#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
60#define QUADSPI_BUF3CR_ALLMST (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
61
62#define QUADSPI_BFGENCR 0x20
63#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
64#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
65#define QUADSPI_BFGENCR_SEQID_SHIFT 12
66#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
67
68#define QUADSPI_BUF0IND 0x30
69#define QUADSPI_BUF1IND 0x34
70#define QUADSPI_BUF2IND 0x38
71#define QUADSPI_SFAR 0x100
72
73#define QUADSPI_SMPR 0x108
74#define QUADSPI_SMPR_DDRSMP_SHIFT 16
75#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
76#define QUADSPI_SMPR_FSDLY_SHIFT 6
77#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
78#define QUADSPI_SMPR_FSPHS_SHIFT 5
79#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
80#define QUADSPI_SMPR_HSENA_SHIFT 0
81#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
82
83#define QUADSPI_RBSR 0x10c
84#define QUADSPI_RBSR_RDBFL_SHIFT 8
85#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
86
87#define QUADSPI_RBCT 0x110
88#define QUADSPI_RBCT_WMRK_MASK 0x1F
89#define QUADSPI_RBCT_RXBRD_SHIFT 8
90#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
91
92#define QUADSPI_TBSR 0x150
93#define QUADSPI_TBDR 0x154
94#define QUADSPI_SR 0x15c
95#define QUADSPI_SR_IP_ACC_SHIFT 1
96#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
97#define QUADSPI_SR_AHB_ACC_SHIFT 2
98#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
99
100#define QUADSPI_FR 0x160
101#define QUADSPI_FR_TFF_MASK 0x1
102
103#define QUADSPI_SFA1AD 0x180
104#define QUADSPI_SFA2AD 0x184
105#define QUADSPI_SFB1AD 0x188
106#define QUADSPI_SFB2AD 0x18c
107#define QUADSPI_RBDR 0x200
108
109#define QUADSPI_LUTKEY 0x300
110#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
111
112#define QUADSPI_LCKCR 0x304
113#define QUADSPI_LCKER_LOCK 0x1
114#define QUADSPI_LCKER_UNLOCK 0x2
115
116#define QUADSPI_RSER 0x164
117#define QUADSPI_RSER_TFIE (0x1 << 0)
118
119#define QUADSPI_LUT_BASE 0x310
120
121/*
122 * The definition of the LUT register shows below:
123 *
124 * ---------------------------------------------------
125 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
126 * ---------------------------------------------------
127 */
128#define OPRND0_SHIFT 0
129#define PAD0_SHIFT 8
130#define INSTR0_SHIFT 10
131#define OPRND1_SHIFT 16
132
133/* Instruction set for the LUT register. */
134#define LUT_STOP 0
135#define LUT_CMD 1
136#define LUT_ADDR 2
137#define LUT_DUMMY 3
138#define LUT_MODE 4
139#define LUT_MODE2 5
140#define LUT_MODE4 6
141#define LUT_READ 7
142#define LUT_WRITE 8
143#define LUT_JMP_ON_CS 9
144#define LUT_ADDR_DDR 10
145#define LUT_MODE_DDR 11
146#define LUT_MODE2_DDR 12
147#define LUT_MODE4_DDR 13
148#define LUT_READ_DDR 14
149#define LUT_WRITE_DDR 15
150#define LUT_DATA_LEARN 16
151
152/*
153 * The PAD definitions for LUT register.
154 *
155 * The pad stands for the lines number of IO[0:3].
156 * For example, the Quad read need four IO lines, so you should
157 * set LUT_PAD4 which means we use four IO lines.
158 */
159#define LUT_PAD1 0
160#define LUT_PAD2 1
161#define LUT_PAD4 2
162
163/* Oprands for the LUT register. */
164#define ADDR24BIT 0x18
165#define ADDR32BIT 0x20
166
167/* Macros for constructing the LUT register. */
168#define LUT0(ins, pad, opr) \
169 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
170 ((LUT_##ins) << INSTR0_SHIFT))
171
172#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
173
174/* other macros for LUT register. */
175#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
176#define QUADSPI_LUT_NUM 64
177
178/* SEQID -- we can have 16 seqids at most. */
179#define SEQID_QUAD_READ 0
180#define SEQID_WREN 1
181#define SEQID_WRDI 2
182#define SEQID_RDSR 3
183#define SEQID_SE 4
184#define SEQID_CHIP_ERASE 5
185#define SEQID_PP 6
186#define SEQID_RDID 7
187#define SEQID_WRSR 8
188#define SEQID_RDCR 9
189#define SEQID_EN4B 10
190#define SEQID_BRWR 11
191
192enum fsl_qspi_devtype {
193 FSL_QUADSPI_VYBRID,
194 FSL_QUADSPI_IMX6SX,
195};
196
197struct fsl_qspi_devtype_data {
198 enum fsl_qspi_devtype devtype;
199 int rxfifo;
200 int txfifo;
201};
202
203static struct fsl_qspi_devtype_data vybrid_data = {
204 .devtype = FSL_QUADSPI_VYBRID,
205 .rxfifo = 128,
206 .txfifo = 64
207};
208
209static struct fsl_qspi_devtype_data imx6sx_data = {
210 .devtype = FSL_QUADSPI_IMX6SX,
211 .rxfifo = 128,
212 .txfifo = 512
213};
214
215#define FSL_QSPI_MAX_CHIP 4
216struct fsl_qspi {
217 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
218 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
219 void __iomem *iobase;
220 void __iomem *ahb_base; /* Used when read from AHB bus */
221 u32 memmap_phy;
222 struct clk *clk, *clk_en;
223 struct device *dev;
224 struct completion c;
225 struct fsl_qspi_devtype_data *devtype_data;
226 u32 nor_size;
227 u32 nor_num;
228 u32 clk_rate;
229 unsigned int chip_base_addr; /* We may support two chips. */
230};
231
232static inline int is_vybrid_qspi(struct fsl_qspi *q)
233{
234 return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
235}
236
237static inline int is_imx6sx_qspi(struct fsl_qspi *q)
238{
239 return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
240}
241
242/*
243 * An IC bug makes us to re-arrange the 32-bit data.
244 * The following chips, such as IMX6SLX, have fixed this bug.
245 */
246static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
247{
248 return is_vybrid_qspi(q) ? __swab32(a) : a;
249}
250
251static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
252{
253 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
254 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
255}
256
257static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
258{
259 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
260 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
261}
262
263static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
264{
265 struct fsl_qspi *q = dev_id;
266 u32 reg;
267
268 /* clear interrupt */
269 reg = readl(q->iobase + QUADSPI_FR);
270 writel(reg, q->iobase + QUADSPI_FR);
271
272 if (reg & QUADSPI_FR_TFF_MASK)
273 complete(&q->c);
274
275 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
276 return IRQ_HANDLED;
277}
278
279static void fsl_qspi_init_lut(struct fsl_qspi *q)
280{
281 void *__iomem base = q->iobase;
282 int rxfifo = q->devtype_data->rxfifo;
283 u32 lut_base;
284 u8 cmd, addrlen, dummy;
285 int i;
286
287 fsl_qspi_unlock_lut(q);
288
289 /* Clear all the LUT table */
290 for (i = 0; i < QUADSPI_LUT_NUM; i++)
291 writel(0, base + QUADSPI_LUT_BASE + i * 4);
292
293 /* Quad Read */
294 lut_base = SEQID_QUAD_READ * 4;
295
296 if (q->nor_size <= SZ_16M) {
297 cmd = OPCODE_QUAD_READ;
298 addrlen = ADDR24BIT;
299 dummy = 8;
300 } else {
301 /* use the 4-byte address */
302 cmd = OPCODE_QUAD_READ;
303 addrlen = ADDR32BIT;
304 dummy = 8;
305 }
306
307 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
308 base + QUADSPI_LUT(lut_base));
309 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
310 base + QUADSPI_LUT(lut_base + 1));
311
312 /* Write enable */
313 lut_base = SEQID_WREN * 4;
314 writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base));
315
316 /* Page Program */
317 lut_base = SEQID_PP * 4;
318
319 if (q->nor_size <= SZ_16M) {
320 cmd = OPCODE_PP;
321 addrlen = ADDR24BIT;
322 } else {
323 /* use the 4-byte address */
324 cmd = OPCODE_PP;
325 addrlen = ADDR32BIT;
326 }
327
328 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
329 base + QUADSPI_LUT(lut_base));
330 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
331
332 /* Read Status */
333 lut_base = SEQID_RDSR * 4;
334 writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1),
335 base + QUADSPI_LUT(lut_base));
336
337 /* Erase a sector */
338 lut_base = SEQID_SE * 4;
339
340 if (q->nor_size <= SZ_16M) {
341 cmd = OPCODE_SE;
342 addrlen = ADDR24BIT;
343 } else {
344 /* use the 4-byte address */
345 cmd = OPCODE_SE;
346 addrlen = ADDR32BIT;
347 }
348
349 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
350 base + QUADSPI_LUT(lut_base));
351
352 /* Erase the whole chip */
353 lut_base = SEQID_CHIP_ERASE * 4;
354 writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE),
355 base + QUADSPI_LUT(lut_base));
356
357 /* READ ID */
358 lut_base = SEQID_RDID * 4;
359 writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8),
360 base + QUADSPI_LUT(lut_base));
361
362 /* Write Register */
363 lut_base = SEQID_WRSR * 4;
364 writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2),
365 base + QUADSPI_LUT(lut_base));
366
367 /* Read Configuration Register */
368 lut_base = SEQID_RDCR * 4;
369 writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1),
370 base + QUADSPI_LUT(lut_base));
371
372 /* Write disable */
373 lut_base = SEQID_WRDI * 4;
374 writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base));
375
376 /* Enter 4 Byte Mode (Micron) */
377 lut_base = SEQID_EN4B * 4;
378 writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base));
379
380 /* Enter 4 Byte Mode (Spansion) */
381 lut_base = SEQID_BRWR * 4;
382 writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base));
383
384 fsl_qspi_lock_lut(q);
385}
386
387/* Get the SEQID for the command */
388static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
389{
390 switch (cmd) {
391 case OPCODE_QUAD_READ:
392 return SEQID_QUAD_READ;
393 case OPCODE_WREN:
394 return SEQID_WREN;
395 case OPCODE_WRDI:
396 return SEQID_WRDI;
397 case OPCODE_RDSR:
398 return SEQID_RDSR;
399 case OPCODE_SE:
400 return SEQID_SE;
401 case OPCODE_CHIP_ERASE:
402 return SEQID_CHIP_ERASE;
403 case OPCODE_PP:
404 return SEQID_PP;
405 case OPCODE_RDID:
406 return SEQID_RDID;
407 case OPCODE_WRSR:
408 return SEQID_WRSR;
409 case OPCODE_RDCR:
410 return SEQID_RDCR;
411 case OPCODE_EN4B:
412 return SEQID_EN4B;
413 case OPCODE_BRWR:
414 return SEQID_BRWR;
415 default:
416 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
417 break;
418 }
419 return -EINVAL;
420}
421
422static int
423fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
424{
425 void *__iomem base = q->iobase;
426 int seqid;
427 u32 reg, reg2;
428 int err;
429
430 init_completion(&q->c);
431 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
432 q->chip_base_addr, addr, len, cmd);
433
434 /* save the reg */
435 reg = readl(base + QUADSPI_MCR);
436
437 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
438 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
439 base + QUADSPI_RBCT);
440 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
441
442 do {
443 reg2 = readl(base + QUADSPI_SR);
444 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
445 udelay(1);
446 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
447 continue;
448 }
449 break;
450 } while (1);
451
452 /* trigger the LUT now */
453 seqid = fsl_qspi_get_seqid(q, cmd);
454 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
455
456 /* Wait for the interrupt. */
457 err = wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000));
458 if (!err) {
459 dev_err(q->dev,
460 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
461 cmd, addr, readl(base + QUADSPI_FR),
462 readl(base + QUADSPI_SR));
463 err = -ETIMEDOUT;
464 } else {
465 err = 0;
466 }
467
468 /* restore the MCR */
469 writel(reg, base + QUADSPI_MCR);
470
471 return err;
472}
473
474/* Read out the data from the QUADSPI_RBDR buffer registers. */
475static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
476{
477 u32 tmp;
478 int i = 0;
479
480 while (len > 0) {
481 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
482 tmp = fsl_qspi_endian_xchg(q, tmp);
483 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
484 q->chip_base_addr, tmp);
485
486 if (len >= 4) {
487 *((u32 *)rxbuf) = tmp;
488 rxbuf += 4;
489 } else {
490 memcpy(rxbuf, &tmp, len);
491 break;
492 }
493
494 len -= 4;
495 i++;
496 }
497}
498
499/*
500 * If we have changed the content of the flash by writing or erasing,
501 * we need to invalidate the AHB buffer. If we do not do so, we may read out
502 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
503 * domain at the same time.
504 */
505static inline void fsl_qspi_invalid(struct fsl_qspi *q)
506{
507 u32 reg;
508
509 reg = readl(q->iobase + QUADSPI_MCR);
510 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
511 writel(reg, q->iobase + QUADSPI_MCR);
512
513 /*
514 * The minimum delay : 1 AHB + 2 SFCK clocks.
515 * Delay 1 us is enough.
516 */
517 udelay(1);
518
519 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
520 writel(reg, q->iobase + QUADSPI_MCR);
521}
522
523static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
524 u8 opcode, unsigned int to, u32 *txbuf,
525 unsigned count, size_t *retlen)
526{
527 int ret, i, j;
528 u32 tmp;
529
530 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
531 q->chip_base_addr, to, count);
532
533 /* clear the TX FIFO. */
534 tmp = readl(q->iobase + QUADSPI_MCR);
535 writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
536
537 /* fill the TX data to the FIFO */
538 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
539 tmp = fsl_qspi_endian_xchg(q, *txbuf);
540 writel(tmp, q->iobase + QUADSPI_TBDR);
541 txbuf++;
542 }
543
544 /* Trigger it */
545 ret = fsl_qspi_runcmd(q, opcode, to, count);
546
547 if (ret == 0 && retlen)
548 *retlen += count;
549
550 return ret;
551}
552
553static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
554{
555 int nor_size = q->nor_size;
556 void __iomem *base = q->iobase;
557
558 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
559 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
560 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
561 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
562}
563
564/*
565 * There are two different ways to read out the data from the flash:
566 * the "IP Command Read" and the "AHB Command Read".
567 *
568 * The IC guy suggests we use the "AHB Command Read" which is faster
569 * then the "IP Command Read". (What's more is that there is a bug in
570 * the "IP Command Read" in the Vybrid.)
571 *
572 * After we set up the registers for the "AHB Command Read", we can use
573 * the memcpy to read the data directly. A "missed" access to the buffer
574 * causes the controller to clear the buffer, and use the sequence pointed
575 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
576 */
577static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
578{
579 void __iomem *base = q->iobase;
580 int seqid;
581
582 /* AHB configuration for access buffer 0/1/2 .*/
583 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
584 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
585 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
586 writel(QUADSPI_BUF3CR_ALLMST, base + QUADSPI_BUF3CR);
587
588 /* We only use the buffer3 */
589 writel(0, base + QUADSPI_BUF0IND);
590 writel(0, base + QUADSPI_BUF1IND);
591 writel(0, base + QUADSPI_BUF2IND);
592
593 /* Set the default lut sequence for AHB Read. */
594 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
595 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
596 q->iobase + QUADSPI_BFGENCR);
597}
598
599/* We use this function to do some basic init for spi_nor_scan(). */
600static int fsl_qspi_nor_setup(struct fsl_qspi *q)
601{
602 void __iomem *base = q->iobase;
603 u32 reg;
604 int ret;
605
606 /* the default frequency, we will change it in the future.*/
607 ret = clk_set_rate(q->clk, 66000000);
608 if (ret)
609 return ret;
610
611 /* Init the LUT table. */
612 fsl_qspi_init_lut(q);
613
614 /* Disable the module */
615 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
616 base + QUADSPI_MCR);
617
618 reg = readl(base + QUADSPI_SMPR);
619 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
620 | QUADSPI_SMPR_FSPHS_MASK
621 | QUADSPI_SMPR_HSENA_MASK
622 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
623
624 /* Enable the module */
625 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
626 base + QUADSPI_MCR);
627
628 /* enable the interrupt */
629 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
630
631 return 0;
632}
633
634static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
635{
636 unsigned long rate = q->clk_rate;
637 int ret;
638
639 if (is_imx6sx_qspi(q))
640 rate *= 4;
641
642 ret = clk_set_rate(q->clk, rate);
643 if (ret)
644 return ret;
645
646 /* Init the LUT table again. */
647 fsl_qspi_init_lut(q);
648
649 /* Init for AHB read */
650 fsl_qspi_init_abh_read(q);
651
652 return 0;
653}
654
655static struct of_device_id fsl_qspi_dt_ids[] = {
656 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
657 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
658 { /* sentinel */ }
659};
660MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
661
662static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
663{
664 q->chip_base_addr = q->nor_size * (nor - q->nor);
665}
666
667static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
668{
669 int ret;
670 struct fsl_qspi *q = nor->priv;
671
672 ret = fsl_qspi_runcmd(q, opcode, 0, len);
673 if (ret)
674 return ret;
675
676 fsl_qspi_read_data(q, len, buf);
677 return 0;
678}
679
680static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
681 int write_enable)
682{
683 struct fsl_qspi *q = nor->priv;
684 int ret;
685
686 if (!buf) {
687 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
688 if (ret)
689 return ret;
690
691 if (opcode == OPCODE_CHIP_ERASE)
692 fsl_qspi_invalid(q);
693
694 } else if (len > 0) {
695 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
696 (u32 *)buf, len, NULL);
697 } else {
698 dev_err(q->dev, "invalid cmd %d\n", opcode);
699 ret = -EINVAL;
700 }
701
702 return ret;
703}
704
705static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
706 size_t len, size_t *retlen, const u_char *buf)
707{
708 struct fsl_qspi *q = nor->priv;
709
710 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
711 (u32 *)buf, len, retlen);
712
713 /* invalid the data in the AHB buffer. */
714 fsl_qspi_invalid(q);
715}
716
717static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
718 size_t len, size_t *retlen, u_char *buf)
719{
720 struct fsl_qspi *q = nor->priv;
721 u8 cmd = nor->read_opcode;
722 int ret;
723
724 dev_dbg(q->dev, "cmd [%x],read from (0x%p, 0x%.8x, 0x%.8x),len:%d\n",
725 cmd, q->ahb_base, q->chip_base_addr, (unsigned int)from, len);
726
727 /* Wait until the previous command is finished. */
728 ret = nor->wait_till_ready(nor);
729 if (ret)
730 return ret;
731
732 /* Read out the data directly from the AHB buffer.*/
733 memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
734
735 *retlen += len;
736 return 0;
737}
738
739static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
740{
741 struct fsl_qspi *q = nor->priv;
742 int ret;
743
744 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
745 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
746
747 /* Wait until finished previous write command. */
748 ret = nor->wait_till_ready(nor);
749 if (ret)
750 return ret;
751
752 /* Send write enable, then erase commands. */
753 ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0);
754 if (ret)
755 return ret;
756
757 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
758 if (ret)
759 return ret;
760
761 fsl_qspi_invalid(q);
762 return 0;
763}
764
765static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
766{
767 struct fsl_qspi *q = nor->priv;
768 int ret;
769
770 ret = clk_enable(q->clk_en);
771 if (ret)
772 return ret;
773
774 ret = clk_enable(q->clk);
775 if (ret) {
776 clk_disable(q->clk_en);
777 return ret;
778 }
779
780 fsl_qspi_set_base_addr(q, nor);
781 return 0;
782}
783
784static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
785{
786 struct fsl_qspi *q = nor->priv;
787
788 clk_disable(q->clk);
789 clk_disable(q->clk_en);
790}
791
792static int fsl_qspi_probe(struct platform_device *pdev)
793{
794 struct device_node *np = pdev->dev.of_node;
795 struct mtd_part_parser_data ppdata;
796 struct device *dev = &pdev->dev;
797 struct fsl_qspi *q;
798 struct resource *res;
799 struct spi_nor *nor;
800 struct mtd_info *mtd;
801 int ret, i = 0;
802 bool has_second_chip = false;
803 const struct of_device_id *of_id =
804 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
805
806 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
807 if (!q)
808 return -ENOMEM;
809
810 q->nor_num = of_get_child_count(dev->of_node);
811 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
812 return -ENODEV;
813
814 /* find the resources */
815 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
816 q->iobase = devm_ioremap_resource(dev, res);
817 if (IS_ERR(q->iobase)) {
818 ret = PTR_ERR(q->iobase);
819 goto map_failed;
820 }
821
822 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
823 "QuadSPI-memory");
824 q->ahb_base = devm_ioremap_resource(dev, res);
825 if (IS_ERR(q->ahb_base)) {
826 ret = PTR_ERR(q->ahb_base);
827 goto map_failed;
828 }
829 q->memmap_phy = res->start;
830
831 /* find the clocks */
832 q->clk_en = devm_clk_get(dev, "qspi_en");
833 if (IS_ERR(q->clk_en)) {
834 ret = PTR_ERR(q->clk_en);
835 goto map_failed;
836 }
837
838 q->clk = devm_clk_get(dev, "qspi");
839 if (IS_ERR(q->clk)) {
840 ret = PTR_ERR(q->clk);
841 goto map_failed;
842 }
843
844 ret = clk_prepare_enable(q->clk_en);
845 if (ret) {
846 dev_err(dev, "can not enable the qspi_en clock\n");
847 goto map_failed;
848 }
849
850 ret = clk_prepare_enable(q->clk);
851 if (ret) {
852 clk_disable_unprepare(q->clk_en);
853 dev_err(dev, "can not enable the qspi clock\n");
854 goto map_failed;
855 }
856
857 /* find the irq */
858 ret = platform_get_irq(pdev, 0);
859 if (ret < 0) {
860 dev_err(dev, "failed to get the irq\n");
861 goto irq_failed;
862 }
863
864 ret = devm_request_irq(dev, ret,
865 fsl_qspi_irq_handler, 0, pdev->name, q);
866 if (ret) {
867 dev_err(dev, "failed to request irq.\n");
868 goto irq_failed;
869 }
870
871 q->dev = dev;
872 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
873 platform_set_drvdata(pdev, q);
874
875 ret = fsl_qspi_nor_setup(q);
876 if (ret)
877 goto irq_failed;
878
879 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
880 has_second_chip = true;
881
882 /* iterate the subnodes. */
883 for_each_available_child_of_node(dev->of_node, np) {
884 const struct spi_device_id *id;
885 char modalias[40];
886
887 /* skip the holes */
888 if (!has_second_chip)
889 i *= 2;
890
891 nor = &q->nor[i];
892 mtd = &q->mtd[i];
893
894 nor->mtd = mtd;
895 nor->dev = dev;
896 nor->priv = q;
897 mtd->priv = nor;
898
899 /* fill the hooks */
900 nor->read_reg = fsl_qspi_read_reg;
901 nor->write_reg = fsl_qspi_write_reg;
902 nor->read = fsl_qspi_read;
903 nor->write = fsl_qspi_write;
904 nor->erase = fsl_qspi_erase;
905
906 nor->prepare = fsl_qspi_prep;
907 nor->unprepare = fsl_qspi_unprep;
908
909 if (of_modalias_node(np, modalias, sizeof(modalias)) < 0)
910 goto map_failed;
911
912 id = spi_nor_match_id(modalias);
913 if (!id)
914 goto map_failed;
915
916 ret = of_property_read_u32(np, "spi-max-frequency",
917 &q->clk_rate);
918 if (ret < 0)
919 goto map_failed;
920
921 /* set the chip address for READID */
922 fsl_qspi_set_base_addr(q, nor);
923
924 ret = spi_nor_scan(nor, id, SPI_NOR_QUAD);
925 if (ret)
926 goto map_failed;
927
928 ppdata.of_node = np;
929 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
930 if (ret)
931 goto map_failed;
932
933 /* Set the correct NOR size now. */
934 if (q->nor_size == 0) {
935 q->nor_size = mtd->size;
936
937 /* Map the SPI NOR to accessiable address */
938 fsl_qspi_set_map_addr(q);
939 }
940
941 /*
942 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
943 * may writes 265 bytes per time. The write is working in the
944 * unit of the TX FIFO, not in the unit of the SPI NOR's page
945 * size.
946 *
947 * So shrink the spi_nor->page_size if it is larger then the
948 * TX FIFO.
949 */
950 if (nor->page_size > q->devtype_data->txfifo)
951 nor->page_size = q->devtype_data->txfifo;
952
953 i++;
954 }
955
956 /* finish the rest init. */
957 ret = fsl_qspi_nor_setup_last(q);
958 if (ret)
959 goto last_init_failed;
960
961 clk_disable(q->clk);
962 clk_disable(q->clk_en);
963 dev_info(dev, "QuadSPI SPI NOR flash driver\n");
964 return 0;
965
966last_init_failed:
967 for (i = 0; i < q->nor_num; i++)
968 mtd_device_unregister(&q->mtd[i]);
969
970irq_failed:
971 clk_disable_unprepare(q->clk);
972 clk_disable_unprepare(q->clk_en);
973map_failed:
974 dev_err(dev, "Freescale QuadSPI probe failed\n");
975 return ret;
976}
977
978static int fsl_qspi_remove(struct platform_device *pdev)
979{
980 struct fsl_qspi *q = platform_get_drvdata(pdev);
981 int i;
982
983 for (i = 0; i < q->nor_num; i++)
984 mtd_device_unregister(&q->mtd[i]);
985
986 /* disable the hardware */
987 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
988 writel(0x0, q->iobase + QUADSPI_RSER);
989
990 clk_unprepare(q->clk);
991 clk_unprepare(q->clk_en);
992 return 0;
993}
994
995static struct platform_driver fsl_qspi_driver = {
996 .driver = {
997 .name = "fsl-quadspi",
998 .bus = &platform_bus_type,
999 .owner = THIS_MODULE,
1000 .of_match_table = fsl_qspi_dt_ids,
1001 },
1002 .probe = fsl_qspi_probe,
1003 .remove = fsl_qspi_remove,
1004};
1005module_platform_driver(fsl_qspi_driver);
1006
1007MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1008MODULE_AUTHOR("Freescale Semiconductor Inc.");
1009MODULE_LICENSE("GPL v2");