blob: 8865e8d9b3c59ed8d774e964f898b9343689f5d2 [file] [log] [blame]
Michael Neuling6f7f0b32015-05-27 16:07:18 +10001/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci.h>
11#include <misc/cxl.h>
12#include "cxl.h"
13
14static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
15{
16 if (dma_mask < DMA_BIT_MASK(64)) {
17 pr_info("%s only 64bit DMA supported on CXL", __func__);
18 return -EIO;
19 }
20
21 *(pdev->dev.dma_mask) = dma_mask;
22 return 0;
23}
24
25static int cxl_pci_probe_mode(struct pci_bus *bus)
26{
27 return PCI_PROBE_NORMAL;
28}
29
30static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
31{
32 return -ENODEV;
33}
34
35static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
36{
37 /*
38 * MSI should never be set but need still need to provide this call
39 * back.
40 */
41}
42
43static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
44{
45 struct pci_controller *phb;
46 struct cxl_afu *afu;
Michael Neuling6f7f0b32015-05-27 16:07:18 +100047
48 phb = pci_bus_to_host(dev->bus);
49 afu = (struct cxl_afu *)phb->private_data;
Andrew Donnellan7d1647d2015-09-07 10:52:58 +100050
Christophe Lombard0d400f72016-03-04 12:26:41 +010051 if (!cxl_ops->link_ok(afu->adapter, afu)) {
Andrew Donnellan7d1647d2015-09-07 10:52:58 +100052 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
53 return false;
54 }
55
Michael Neuling6f7f0b32015-05-27 16:07:18 +100056 set_dma_ops(&dev->dev, &dma_direct_ops);
57 set_dma_offset(&dev->dev, PAGE_OFFSET);
58
Ian Munsiea19bd792016-07-14 07:17:04 +100059 return _cxl_pci_associate_default_context(dev, afu);
Michael Neuling6f7f0b32015-05-27 16:07:18 +100060}
61
62static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
63 unsigned long type)
64{
65 return 1;
66}
67
68static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
69{
70 /* Should we do an AFU reset here ? */
71}
72
73static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
74{
75 return (bus << 8) + devfn;
76}
77
Michael Neuling6f7f0b32015-05-27 16:07:18 +100078static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
Frederic Barratd601ea92016-03-04 12:26:40 +010079 struct cxl_afu **_afu, int *_record)
Michael Neuling6f7f0b32015-05-27 16:07:18 +100080{
81 struct pci_controller *phb;
82 struct cxl_afu *afu;
Frederic Barratd601ea92016-03-04 12:26:40 +010083 int record;
Michael Neuling6f7f0b32015-05-27 16:07:18 +100084
85 phb = pci_bus_to_host(bus);
Michael Neuling6f7f0b32015-05-27 16:07:18 +100086 if (phb == NULL)
87 return PCIBIOS_DEVICE_NOT_FOUND;
Frederic Barratd601ea92016-03-04 12:26:40 +010088
Maninder Singh14f21182015-06-29 16:05:11 +053089 afu = (struct cxl_afu *)phb->private_data;
Frederic Barratd601ea92016-03-04 12:26:40 +010090 record = cxl_pcie_cfg_record(bus->number, devfn);
91 if (record > afu->crs_num)
Michael Neuling6f7f0b32015-05-27 16:07:18 +100092 return PCIBIOS_DEVICE_NOT_FOUND;
Michael Neuling6f7f0b32015-05-27 16:07:18 +100093
Frederic Barratd601ea92016-03-04 12:26:40 +010094 *_afu = afu;
95 *_record = record;
Michael Neuling6f7f0b32015-05-27 16:07:18 +100096 return 0;
97}
98
99static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
100 int offset, int len, u32 *val)
101{
Frederic Barratd601ea92016-03-04 12:26:40 +0100102 int rc, record;
103 struct cxl_afu *afu;
104 u8 val8;
105 u16 val16;
106 u32 val32;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000107
Frederic Barratd601ea92016-03-04 12:26:40 +0100108 rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000109 if (rc)
110 return rc;
111
Frederic Barratd601ea92016-03-04 12:26:40 +0100112 switch (len) {
113 case 1:
114 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
115 *val = val8;
116 break;
117 case 2:
118 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
119 *val = val16;
120 break;
121 case 4:
122 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
123 *val = val32;
124 break;
125 default:
126 WARN_ON(1);
127 }
128
129 if (rc)
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000130 return PCIBIOS_DEVICE_NOT_FOUND;
131
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000132 return PCIBIOS_SUCCESSFUL;
133}
134
135static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
136 int offset, int len, u32 val)
137{
Frederic Barratd601ea92016-03-04 12:26:40 +0100138 int rc, record;
139 struct cxl_afu *afu;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000140
Frederic Barratd601ea92016-03-04 12:26:40 +0100141 rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000142 if (rc)
143 return rc;
144
Frederic Barratd601ea92016-03-04 12:26:40 +0100145 switch (len) {
146 case 1:
147 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
148 break;
149 case 2:
150 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
151 break;
152 case 4:
153 rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
154 break;
155 default:
156 WARN_ON(1);
157 }
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000158
Frederic Barratd601ea92016-03-04 12:26:40 +0100159 if (rc)
160 return PCIBIOS_SET_FAILED;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000161
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000162 return PCIBIOS_SUCCESSFUL;
163}
164
165static struct pci_ops cxl_pcie_pci_ops =
166{
167 .read = cxl_pcie_read_config,
168 .write = cxl_pcie_write_config,
169};
170
171
172static struct pci_controller_ops cxl_pci_controller_ops =
173{
174 .probe_mode = cxl_pci_probe_mode,
175 .enable_device_hook = cxl_pci_enable_device_hook,
Ian Munsiea19bd792016-07-14 07:17:04 +1000176 .disable_device = _cxl_pci_disable_device,
177 .release_device = _cxl_pci_disable_device,
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000178 .window_alignment = cxl_pci_window_alignment,
179 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
180 .setup_msi_irqs = cxl_setup_msi_irqs,
181 .teardown_msi_irqs = cxl_teardown_msi_irqs,
182 .dma_set_mask = cxl_dma_set_mask,
183};
184
185int cxl_pci_vphb_add(struct cxl_afu *afu)
186{
Frederic Barrata4307392016-06-15 16:42:16 +0200187 struct pci_controller *phb;
Frederic Barratd601ea92016-03-04 12:26:40 +0100188 struct device_node *vphb_dn;
189 struct device *parent;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000190
Ian Munsiee4f5fc02016-07-14 07:17:05 +1000191 /*
192 * If there are no AFU configuration records we won't have anything to
193 * expose under the vPHB, so skip creating one, returning success since
194 * this is still a valid case. This will also opt us out of EEH
195 * handling since we won't have anything special to do if there are no
196 * kernel drivers attached to the vPHB, and EEH handling is not yet
197 * supported in the peer model.
198 */
199 if (!afu->crs_num)
200 return 0;
201
Frederic Barrata4307392016-06-15 16:42:16 +0200202 /* The parent device is the adapter. Reuse the device node of
203 * the adapter.
204 * We don't seem to care what device node is used for the vPHB,
205 * but tools such as lsvpd walk up the device parents looking
206 * for a valid location code, so we might as well show devices
207 * attached to the adapter as being located on that adapter.
208 */
209 parent = afu->adapter->dev.parent;
210 vphb_dn = parent->of_node;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000211
212 /* Alloc and setup PHB data structure */
Frederic Barratd601ea92016-03-04 12:26:40 +0100213 phb = pcibios_alloc_controller(vphb_dn);
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000214 if (!phb)
215 return -ENODEV;
216
217 /* Setup parent in sysfs */
Frederic Barratd601ea92016-03-04 12:26:40 +0100218 phb->parent = parent;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000219
220 /* Setup the PHB using arch provided callback */
221 phb->ops = &cxl_pcie_pci_ops;
Frederic Barratd601ea92016-03-04 12:26:40 +0100222 phb->cfg_addr = NULL;
223 phb->cfg_data = 0;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000224 phb->private_data = afu;
225 phb->controller_ops = cxl_pci_controller_ops;
226
227 /* Scan the bus */
228 pcibios_scan_phb(phb);
229 if (phb->bus == NULL)
230 return -ENXIO;
231
232 /* Claim resources. This might need some rework as well depending
233 * whether we are doing probe-only or not, like assigning unassigned
234 * resources etc...
235 */
236 pcibios_claim_one_bus(phb->bus);
237
238 /* Add probed PCI devices to the device model */
239 pci_bus_add_devices(phb->bus);
240
241 afu->phb = phb;
242
243 return 0;
244}
245
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000246void cxl_pci_vphb_remove(struct cxl_afu *afu)
247{
248 struct pci_controller *phb;
249
250 /* If there is no configuration record we won't have one of these */
251 if (!afu || !afu->phb)
252 return;
253
254 phb = afu->phb;
Andrew Donnellan2e1a2552015-10-13 15:09:44 +1100255 afu->phb = NULL;
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000256
257 pci_remove_root_bus(phb->bus);
Andrew Donnellan2e1a2552015-10-13 15:09:44 +1100258 pcibios_free_controller(phb);
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000259}
260
Vaibhav Jain17eb3ee2016-02-29 11:10:53 +0530261bool cxl_pci_is_vphb_device(struct pci_dev *dev)
262{
263 struct pci_controller *phb;
264
265 phb = pci_bus_to_host(dev->bus);
266
267 return (phb->ops == &cxl_pcie_pci_ops);
268}
269
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000270struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
271{
272 struct pci_controller *phb;
273
274 phb = pci_bus_to_host(dev->bus);
275
276 return (struct cxl_afu *)phb->private_data;
277}
278EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
279
280unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
281{
282 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
283}
284EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);