| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-sh/cpu-sh3/timer.h |
| 3 | * |
| 4 | * Copyright (C) 2004 Lineo Solutions, Inc. |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | #ifndef __ASM_CPU_SH3_TIMER_H |
| 11 | #define __ASM_CPU_SH3_TIMER_H |
| 12 | |
| 13 | /* |
| 14 | * --------------------------------------------------------------------------- |
| 15 | * TMU Common definitions for SH3 processors |
| 16 | * SH7706 |
| 17 | * SH7709S |
| 18 | * SH7727 |
| 19 | * SH7729R |
| 20 | * SH7710 |
| 21 | * SH7720 |
| 22 | * SH7300 |
| Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame^] | 23 | * SH7710 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | * --------------------------------------------------------------------------- |
| 25 | */ |
| 26 | |
| Paul Mundt | d95fb13 | 2006-09-27 13:30:08 +0900 | [diff] [blame] | 27 | #if !defined(CONFIG_CPU_SUBTYPE_SH7727) |
| 28 | #define TMU_TOCR 0xfffffe90 /* Byte access */ |
| 29 | #endif |
| 30 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) |
| 32 | #define TMU_TSTR 0xa412fe92 /* Byte access */ |
| 33 | |
| 34 | #define TMU0_TCOR 0xa412fe94 /* Long access */ |
| 35 | #define TMU0_TCNT 0xa412fe98 /* Long access */ |
| 36 | #define TMU0_TCR 0xa412fe9c /* Word access */ |
| 37 | |
| 38 | #define TMU1_TCOR 0xa412fea0 /* Long access */ |
| 39 | #define TMU1_TCNT 0xa412fea4 /* Long access */ |
| 40 | #define TMU1_TCR 0xa412fea8 /* Word access */ |
| 41 | |
| 42 | #define TMU2_TCOR 0xa412feac /* Long access */ |
| 43 | #define TMU2_TCNT 0xa412feb0 /* Long access */ |
| 44 | #define TMU2_TCR 0xa412feb4 /* Word access */ |
| 45 | |
| 46 | #else |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #define TMU_TSTR 0xfffffe92 /* Byte access */ |
| 48 | |
| 49 | #define TMU0_TCOR 0xfffffe94 /* Long access */ |
| 50 | #define TMU0_TCNT 0xfffffe98 /* Long access */ |
| 51 | #define TMU0_TCR 0xfffffe9c /* Word access */ |
| 52 | |
| 53 | #define TMU1_TCOR 0xfffffea0 /* Long access */ |
| 54 | #define TMU1_TCNT 0xfffffea4 /* Long access */ |
| 55 | #define TMU1_TCR 0xfffffea8 /* Word access */ |
| 56 | |
| 57 | #define TMU2_TCOR 0xfffffeac /* Long access */ |
| 58 | #define TMU2_TCNT 0xfffffeb0 /* Long access */ |
| 59 | #define TMU2_TCR 0xfffffeb4 /* Word access */ |
| 60 | #if !defined(CONFIG_CPU_SUBTYPE_SH7727) |
| 61 | #define TMU2_TCPR2 0xfffffeb8 /* Long access */ |
| 62 | #endif |
| 63 | #endif |
| 64 | |
| 65 | #endif /* __ASM_CPU_SH3_TIMER_H */ |
| 66 | |