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Valentine Barshakba3eb9f2013-10-29 20:12:51 +04001/*
2 * pci-rcar-gen2: internal PCI bus support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
Valentine Barshakfb178d82013-12-04 20:33:35 +040020#include <linux/pm_runtime.h>
Valentine Barshakba3eb9f2013-10-29 20:12:51 +040021#include <linux/slab.h>
22
23/* AHB-PCI Bridge PCI communication registers */
24#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
25
26#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
27#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
28#define RCAR_PCIAHB_PREFETCH0 0x0
29#define RCAR_PCIAHB_PREFETCH4 0x1
30#define RCAR_PCIAHB_PREFETCH8 0x2
31#define RCAR_PCIAHB_PREFETCH16 0x3
32
33#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
34#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
35#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
36#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
37#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
38#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
39
40#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
41#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
Ben Dooks80a595d2014-02-18 11:11:01 +090042#define RCAR_PCI_INT_SIGTABORT (1 << 0)
43#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
44#define RCAR_PCI_INT_REMABORT (1 << 2)
45#define RCAR_PCI_INT_PERR (1 << 3)
46#define RCAR_PCI_INT_SIGSERR (1 << 4)
47#define RCAR_PCI_INT_RESERR (1 << 5)
48#define RCAR_PCI_INT_WIN1ERR (1 << 12)
49#define RCAR_PCI_INT_WIN2ERR (1 << 13)
Valentine Barshakba3eb9f2013-10-29 20:12:51 +040050#define RCAR_PCI_INT_A (1 << 16)
51#define RCAR_PCI_INT_B (1 << 17)
52#define RCAR_PCI_INT_PME (1 << 19)
Ben Dooks80a595d2014-02-18 11:11:01 +090053#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
54 RCAR_PCI_INT_SIGRETABORT | \
55 RCAR_PCI_INT_SIGRETABORT | \
56 RCAR_PCI_INT_REMABORT | \
57 RCAR_PCI_INT_PERR | \
58 RCAR_PCI_INT_SIGSERR | \
59 RCAR_PCI_INT_RESERR | \
60 RCAR_PCI_INT_WIN1ERR | \
61 RCAR_PCI_INT_WIN2ERR)
Valentine Barshakba3eb9f2013-10-29 20:12:51 +040062
63#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
64#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
65#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
66#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
67#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
68#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
69#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
70 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
71 RCAR_AHB_BUS_MMODE_WR_INCR | \
72 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
73 RCAR_AHB_BUS_SMODE_READYCTR)
74
75#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
76#define RCAR_USBCTR_USBH_RST (1 << 0)
77#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
78#define RCAR_USBCTR_PLL_RST (1 << 2)
79#define RCAR_USBCTR_DIRPD (1 << 8)
80#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
81#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
82#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
83#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
84#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
85#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
86
87#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
88#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
89#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
90#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
91
92#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
93
94/* Number of internal PCI controllers */
95#define RCAR_PCI_NR_CONTROLLERS 3
96
97struct rcar_pci_priv {
Valentine Barshakfb178d82013-12-04 20:33:35 +040098 struct device *dev;
Valentine Barshakba3eb9f2013-10-29 20:12:51 +040099 void __iomem *reg;
100 struct resource io_res;
101 struct resource mem_res;
102 struct resource *cfg_res;
103 int irq;
104};
105
106/* PCI configuration space operations */
107static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
108 int where)
109{
110 struct pci_sys_data *sys = bus->sysdata;
111 struct rcar_pci_priv *priv = sys->private_data;
112 int slot, val;
113
114 if (sys->busnr != bus->number || PCI_FUNC(devfn))
115 return NULL;
116
117 /* Only one EHCI/OHCI device built-in */
118 slot = PCI_SLOT(devfn);
119 if (slot > 2)
120 return NULL;
121
Ben Dookse64a2a92014-02-18 11:11:11 +0900122 /* bridge logic only has registers to 0x40 */
123 if (slot == 0x0 && where >= 0x40)
124 return NULL;
125
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400126 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
127 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
128
129 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
130 return priv->reg + (slot >> 1) * 0x100 + where;
131}
132
133static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
134 int where, int size, u32 *val)
135{
136 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
137
138 if (!reg)
139 return PCIBIOS_DEVICE_NOT_FOUND;
140
141 switch (size) {
142 case 1:
143 *val = ioread8(reg);
144 break;
145 case 2:
146 *val = ioread16(reg);
147 break;
148 default:
149 *val = ioread32(reg);
150 break;
151 }
152
153 return PCIBIOS_SUCCESSFUL;
154}
155
156static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
157 int where, int size, u32 val)
158{
159 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
160
161 if (!reg)
162 return PCIBIOS_DEVICE_NOT_FOUND;
163
164 switch (size) {
165 case 1:
166 iowrite8(val, reg);
167 break;
168 case 2:
169 iowrite16(val, reg);
170 break;
171 default:
172 iowrite32(val, reg);
173 break;
174 }
175
176 return PCIBIOS_SUCCESSFUL;
177}
178
179/* PCI interrupt mapping */
180static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
181{
182 struct pci_sys_data *sys = dev->bus->sysdata;
183 struct rcar_pci_priv *priv = sys->private_data;
184
185 return priv->irq;
186}
187
Ben Dooks80a595d2014-02-18 11:11:01 +0900188#ifdef CONFIG_PCI_DEBUG
189/* if debug enabled, then attach an error handler irq to the bridge */
190
191static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
192{
193 struct rcar_pci_priv *priv = pw;
194 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
195
196 if (status & RCAR_PCI_INT_ALLERRORS) {
197 dev_err(priv->dev, "error irq: status %08x\n", status);
198
199 /* clear the error(s) */
200 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
201 priv->reg + RCAR_PCI_INT_STATUS_REG);
202 return IRQ_HANDLED;
203 }
204
205 return IRQ_NONE;
206}
207
208static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
209{
210 int ret;
211 u32 val;
212
213 ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
214 IRQF_SHARED, "error irq", priv);
215 if (ret) {
216 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
217 return;
218 }
219
220 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
221 val |= RCAR_PCI_INT_ALLERRORS;
222 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
223}
224#else
225static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
226#endif
227
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400228/* PCI host controller setup */
229static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
230{
231 struct rcar_pci_priv *priv = sys->private_data;
232 void __iomem *reg = priv->reg;
233 u32 val;
234
Valentine Barshakfb178d82013-12-04 20:33:35 +0400235 pm_runtime_enable(priv->dev);
236 pm_runtime_get_sync(priv->dev);
237
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400238 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
Valentine Barshakfb178d82013-12-04 20:33:35 +0400239 dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400240
241 /* Disable Direct Power Down State and assert reset */
242 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
243 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
244 iowrite32(val, reg + RCAR_USBCTR_REG);
245 udelay(4);
246
247 /* De-assert reset and set PCIAHB window1 size to 1GB */
248 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
249 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
250 iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
251
252 /* Configure AHB master and slave modes */
253 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
254
255 /* Configure PCI arbiter */
256 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
257 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
258 RCAR_PCI_ARBITER_PCIBP_MODE;
259 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
260
261 /* PCI-AHB mapping: 0x40000000-0x80000000 */
262 iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
263 reg + RCAR_PCIAHB_WIN1_CTR_REG);
264
265 /* AHB-PCI mapping: OHCI/EHCI registers */
266 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
267 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
268
269 /* Enable AHB-PCI bridge PCI configuration access */
270 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
271 reg + RCAR_AHBPCI_WIN1_CTR_REG);
272 /* Set PCI-AHB Window1 address */
273 iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
274 reg + PCI_BASE_ADDRESS_1);
275 /* Set AHB-PCI bridge PCI communication area address */
276 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
277 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
278
279 val = ioread32(reg + PCI_COMMAND);
280 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
281 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
282 iowrite32(val, reg + PCI_COMMAND);
283
284 /* Enable PCI interrupts */
285 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
286 reg + RCAR_PCI_INT_ENABLE_REG);
287
Ben Dooks80a595d2014-02-18 11:11:01 +0900288 if (priv->irq > 0)
289 rcar_pci_setup_errirq(priv);
290
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400291 /* Add PCI resources */
292 pci_add_resource(&sys->resources, &priv->io_res);
293 pci_add_resource(&sys->resources, &priv->mem_res);
294
295 return 1;
296}
297
298static struct pci_ops rcar_pci_ops = {
299 .read = rcar_pci_read_config,
300 .write = rcar_pci_write_config,
301};
302
303static struct hw_pci rcar_hw_pci __initdata = {
304 .map_irq = rcar_pci_map_irq,
305 .ops = &rcar_pci_ops,
306 .setup = rcar_pci_setup,
307};
308
309static int rcar_pci_count __initdata;
310
311static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
312{
313 void **private_data;
314 int count;
315
316 if (rcar_hw_pci.nr_controllers < rcar_pci_count)
317 goto add_priv;
318
319 /* (Re)allocate private data pointer array if needed */
320 count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
321 private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
322 if (!private_data)
323 return -ENOMEM;
324
325 rcar_pci_count = count;
326 if (rcar_hw_pci.private_data) {
327 memcpy(private_data, rcar_hw_pci.private_data,
328 rcar_hw_pci.nr_controllers * sizeof(void *));
329 kfree(rcar_hw_pci.private_data);
330 }
331
332 rcar_hw_pci.private_data = private_data;
333
334add_priv:
335 /* Add private data pointer to the array */
336 rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
337 return 0;
338}
339
340static int __init rcar_pci_probe(struct platform_device *pdev)
341{
342 struct resource *cfg_res, *mem_res;
343 struct rcar_pci_priv *priv;
344 void __iomem *reg;
345
346 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
347 reg = devm_ioremap_resource(&pdev->dev, cfg_res);
Wei Yongjunc176d1c2013-11-19 11:40:28 +0800348 if (IS_ERR(reg))
349 return PTR_ERR(reg);
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400350
351 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
352 if (!mem_res || !mem_res->start)
353 return -ENODEV;
354
355 priv = devm_kzalloc(&pdev->dev,
356 sizeof(struct rcar_pci_priv), GFP_KERNEL);
357 if (!priv)
358 return -ENOMEM;
359
360 priv->mem_res = *mem_res;
361 /*
362 * The controller does not support/use port I/O,
363 * so setup a dummy port I/O region here.
364 */
365 priv->io_res.start = priv->mem_res.start;
366 priv->io_res.end = priv->mem_res.end;
367 priv->io_res.flags = IORESOURCE_IO;
368
369 priv->cfg_res = cfg_res;
370
371 priv->irq = platform_get_irq(pdev, 0);
372 priv->reg = reg;
Valentine Barshakfb178d82013-12-04 20:33:35 +0400373 priv->dev = &pdev->dev;
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400374
Ben Dooksed65b782014-02-18 11:10:51 +0900375 if (priv->irq < 0) {
376 dev_err(&pdev->dev, "no valid irq found\n");
377 return priv->irq;
378 }
379
Valentine Barshakba3eb9f2013-10-29 20:12:51 +0400380 return rcar_pci_add_controller(priv);
381}
382
383static struct platform_driver rcar_pci_driver = {
384 .driver = {
385 .name = "pci-rcar-gen2",
386 },
387};
388
389static int __init rcar_pci_init(void)
390{
391 int retval;
392
393 retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
394 if (!retval)
395 pci_common_init(&rcar_hw_pci);
396
397 /* Private data pointer array is not needed any more */
398 kfree(rcar_hw_pci.private_data);
399 rcar_hw_pci.private_data = NULL;
400
401 return retval;
402}
403
404subsys_initcall(rcar_pci_init);
405
406MODULE_LICENSE("GPL v2");
407MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
408MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");