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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001#ifndef LINUX_BCMA_DRIVER_CC_H_
2#define LINUX_BCMA_DRIVER_CC_H_
3
4/** ChipCommon core registers. **/
5#define BCMA_CC_ID 0x0000
6#define BCMA_CC_ID_ID 0x0000FFFF
7#define BCMA_CC_ID_ID_SHIFT 0
8#define BCMA_CC_ID_REV 0x000F0000
9#define BCMA_CC_ID_REV_SHIFT 16
10#define BCMA_CC_ID_PKG 0x00F00000
11#define BCMA_CC_ID_PKG_SHIFT 20
12#define BCMA_CC_ID_NRCORES 0x0F000000
13#define BCMA_CC_ID_NRCORES_SHIFT 24
14#define BCMA_CC_ID_TYPE 0xF0000000
15#define BCMA_CC_ID_TYPE_SHIFT 28
16#define BCMA_CC_CAP 0x0004 /* Capabilities */
17#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
18#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
19#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
20#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
21#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
22#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
23#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
24#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
25#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
26#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
Rafał Miłecki7eea1a22012-07-16 11:46:52 +020027#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
Rafał Miłecki8369ae32011-05-09 18:56:46 +020028#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
29#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
30#define BCMA_PLLTYPE_NONE 0x00000000
31#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
32#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
33#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
34#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
35#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
36#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
37#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
38#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
39#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
40#define BCMA_CC_CAP_OTPS_SHIFT 19
41#define BCMA_CC_CAP_OTPS_BASE 5
42#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
43#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
44#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
45#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
46#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
47#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
Rafał Miłecki7eea1a22012-07-16 11:46:52 +020048#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
Rafał Miłecki8369ae32011-05-09 18:56:46 +020049#define BCMA_CC_CORECTL 0x0008
50#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
51#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
52#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
53#define BCMA_CC_BIST 0x000C
54#define BCMA_CC_OTPS 0x0010 /* OTP status */
55#define BCMA_CC_OTPS_PROGFAIL 0x80000000
56#define BCMA_CC_OTPS_PROTECT 0x00000007
57#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
58#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
59#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
Arend van Spriel10d84932012-03-06 15:50:48 +010060#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
61#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
62#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
Rafał Miłecki8369ae32011-05-09 18:56:46 +020063#define BCMA_CC_OTPC 0x0014 /* OTP control */
64#define BCMA_CC_OTPC_RECWAIT 0xFF000000
65#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
66#define BCMA_CC_OTPC_PRW_SHIFT 8
67#define BCMA_CC_OTPC_MAXFAIL 0x00000038
68#define BCMA_CC_OTPC_VSEL 0x00000006
69#define BCMA_CC_OTPC_SELVL 0x00000001
70#define BCMA_CC_OTPP 0x0018 /* OTP prog */
71#define BCMA_CC_OTPP_COL 0x000000FF
72#define BCMA_CC_OTPP_ROW 0x0000FF00
73#define BCMA_CC_OTPP_ROW_SHIFT 8
74#define BCMA_CC_OTPP_READERR 0x10000000
75#define BCMA_CC_OTPP_VALUE 0x20000000
76#define BCMA_CC_OTPP_READ 0x40000000
77#define BCMA_CC_OTPP_START 0x80000000
78#define BCMA_CC_OTPP_BUSY 0x80000000
Arend van Spriel10d84932012-03-06 15:50:48 +010079#define BCMA_CC_OTPL 0x001C /* OTP layout */
80#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
Rafał Miłecki8369ae32011-05-09 18:56:46 +020081#define BCMA_CC_IRQSTAT 0x0020
82#define BCMA_CC_IRQMASK 0x0024
83#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
84#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
85#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
86#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
87#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
Arend van Spriel10d84932012-03-06 15:50:48 +010088#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
89#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
90#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
91#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
Rafał Miłeckic263c2c2012-07-23 18:20:12 +020092#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
93#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
94#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
95#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
96#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
97#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
Hauke Mehrtens650cef382012-07-09 22:03:10 +020098#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
99#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
100#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
101#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
102#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
Rafał Miłecki3213e1a2012-08-08 19:10:14 +0200103#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200104#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
105#define BCMA_CC_JCMD_START 0x80000000
106#define BCMA_CC_JCMD_BUSY 0x80000000
107#define BCMA_CC_JCMD_PAUSE 0x40000000
108#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
109#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
110#define BCMA_CC_JCMD0_ACC_DR 0x00001000
111#define BCMA_CC_JCMD0_ACC_IR 0x00002000
112#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
113#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
114#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
115#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
116#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
117#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
118#define BCMA_CC_JCMD_ACC_DR 0x00010000
119#define BCMA_CC_JCMD_ACC_IR 0x00020000
120#define BCMA_CC_JCMD_ACC_RESET 0x00030000
121#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
122#define BCMA_CC_JCMD_ACC_PDR 0x00050000
123#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
124#define BCMA_CC_JCMD_IRW_SHIFT 8
125#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
126#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
127#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
128#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
129#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
130#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
131#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
132#define BCMA_CC_FLASHCTL 0x0040
Rafał Miłecki7eea1a22012-07-16 11:46:52 +0200133/* Start/busy bit in flashcontrol */
134#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
135#define BCMA_CC_FLASHCTL_ACTION 0x00000700
136#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200137#define BCMA_CC_FLASHCTL_START 0x80000000
138#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
Rafał Miłecki7eea1a22012-07-16 11:46:52 +0200139/* Flashcontrol action + opcodes for ST flashes */
140#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
141#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
142#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
143#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
144#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
145#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
146#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
147#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
148#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
149#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
150#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
151#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
152/* Flashcontrol action + opcodes for Atmel flashes */
153#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
154#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
155#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
156#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
157#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
158#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
159#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
160#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
161#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
162#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
163#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
164#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
165#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
166#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
167#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
168#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
169#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
170#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
171#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200172#define BCMA_CC_FLASHADDR 0x0044
173#define BCMA_CC_FLASHDATA 0x0048
Rafał Miłecki7eea1a22012-07-16 11:46:52 +0200174/* Status register bits for ST flashes */
175#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
176#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
177#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
178#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
179#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
180/* Status register bits for Atmel flashes */
181#define BCMA_CC_FLASHDATA_AT_READY 0x80
182#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
183#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
184#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200185#define BCMA_CC_BCAST_ADDR 0x0050
186#define BCMA_CC_BCAST_DATA 0x0054
Rafał Miłecki1073e4e2011-05-11 02:08:09 +0200187#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
188#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200189#define BCMA_CC_GPIOIN 0x0060
190#define BCMA_CC_GPIOOUT 0x0064
191#define BCMA_CC_GPIOOUTEN 0x0068
192#define BCMA_CC_GPIOCTL 0x006C
193#define BCMA_CC_GPIOPOL 0x0070
194#define BCMA_CC_GPIOIRQ 0x0074
195#define BCMA_CC_WATCHDOG 0x0080
196#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
Rafał Miłecki1073e4e2011-05-11 02:08:09 +0200197#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
198#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
199#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200200#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
201#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
202#define BCMA_CC_CLOCK_N 0x0090
203#define BCMA_CC_CLOCK_SB 0x0094
204#define BCMA_CC_CLOCK_PCI 0x0098
205#define BCMA_CC_CLOCK_M2 0x009C
206#define BCMA_CC_CLOCK_MIPS 0x00A0
207#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
208#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
209#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
210#define BCMA_CC_CLKDIV_OTP 0x000F0000
211#define BCMA_CC_CLKDIV_OTP_SHIFT 16
212#define BCMA_CC_CLKDIV_JTAG 0x00000F00
213#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
214#define BCMA_CC_CLKDIV_UART 0x000000FF
215#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
216#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
217#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
218#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
219#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
220#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
221#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
222#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
223#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
224#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
225#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
226#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
227#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
228#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
229#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
230#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
231#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
232#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
233#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
234#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
235#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
236#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
237#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
238#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
239#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
240#define BCMA_CC_EROM 0x00FC
241#define BCMA_CC_PCMCIA_CFG 0x0100
242#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
243#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
244#define BCMA_CC_PCMCIA_IOWAIT 0x010C
245#define BCMA_CC_IDE_CFG 0x0110
246#define BCMA_CC_IDE_MEMWAIT 0x0114
247#define BCMA_CC_IDE_ATTRWAIT 0x0118
248#define BCMA_CC_IDE_IOWAIT 0x011C
249#define BCMA_CC_PROG_CFG 0x0120
250#define BCMA_CC_PROG_WAITCNT 0x0124
251#define BCMA_CC_FLASH_CFG 0x0128
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200252#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200253#define BCMA_CC_FLASH_WAITCNT 0x012C
Hauke Mehrtensd6865dcc2012-01-31 00:03:37 +0100254#define BCMA_CC_SROM_CONTROL 0x0190
255#define BCMA_CC_SROM_CONTROL_START 0x80000000
256#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
257#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
258#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
259#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
260#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
261#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
262#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
263#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
264#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
265#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
266#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
267#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
268#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
269#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
Rafał Miłecki3213e1a2012-08-08 19:10:14 +0200270/* Block 0x140 - 0x190 registers are chipset specific */
271#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
272#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
273#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
274#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
275#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
276#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
277#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
278#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
279#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
280#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
281#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
282#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
283#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
284#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
285/* NAND flash registers for BCM4706 (corerev = 31) */
286#define BCMA_CC_NFLASH_CTL 0x01A0
287#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
288#define BCMA_CC_NFLASH_CONF 0x01A4
289#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
290#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
291#define BCMA_CC_NFLASH_DATA 0x01B0
292#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
Rafał Miłeckibb932ad2011-07-16 18:43:36 +0200293/* 0x1E0 is defined as shared BCMA_CLKCTLST */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200294#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
295#define BCMA_CC_UART0_DATA 0x0300
296#define BCMA_CC_UART0_IMR 0x0304
297#define BCMA_CC_UART0_FCR 0x0308
298#define BCMA_CC_UART0_LCR 0x030C
299#define BCMA_CC_UART0_MCR 0x0310
300#define BCMA_CC_UART0_LSR 0x0314
301#define BCMA_CC_UART0_MSR 0x0318
302#define BCMA_CC_UART0_SCRATCH 0x031C
303#define BCMA_CC_UART1_DATA 0x0400
304#define BCMA_CC_UART1_IMR 0x0404
305#define BCMA_CC_UART1_FCR 0x0408
306#define BCMA_CC_UART1_LCR 0x040C
307#define BCMA_CC_UART1_MCR 0x0410
308#define BCMA_CC_UART1_LSR 0x0414
309#define BCMA_CC_UART1_MSR 0x0418
310#define BCMA_CC_UART1_SCRATCH 0x041C
311/* PMU registers (rev >= 20) */
312#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
313#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
314#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
Rafał Miłeckiaee5ed52011-12-08 18:02:22 +0100315#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200316#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
317#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
318#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
319#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
320#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
321#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
322#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
323#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
324#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
325#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
326#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
327#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
328#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
329#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
330#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
331#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
332#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
333#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
334#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
335#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
336#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
337#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
338#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
339#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
340#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
341#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
342#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
343#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
344#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
345#define BCMA_CC_CHIPCTL_ADDR 0x0650
346#define BCMA_CC_CHIPCTL_DATA 0x0654
347#define BCMA_CC_REGCTL_ADDR 0x0658
348#define BCMA_CC_REGCTL_DATA 0x065C
349#define BCMA_CC_PLLCTL_ADDR 0x0660
350#define BCMA_CC_PLLCTL_DATA 0x0664
Rafał Miłeckieb1577b2011-07-17 11:00:59 +0200351#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
Rafał Miłecki3213e1a2012-08-08 19:10:14 +0200352/* NAND flash MLC controller registers (corerev >= 38) */
353#define BCMA_CC_NAND_REVISION 0x0C00
354#define BCMA_CC_NAND_CMD_START 0x0C04
355#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
356#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
357#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
358#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
359#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
360#define BCMA_CC_NAND_SPARE_RD0 0x0C20
361#define BCMA_CC_NAND_SPARE_RD4 0x0C24
362#define BCMA_CC_NAND_SPARE_RD8 0x0C28
363#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
364#define BCMA_CC_NAND_SPARE_WR0 0x0C30
365#define BCMA_CC_NAND_SPARE_WR4 0x0C34
366#define BCMA_CC_NAND_SPARE_WR8 0x0C38
367#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
368#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
369#define BCMA_CC_NAND_CONFIG 0x0C48
370#define BCMA_CC_NAND_TIMING_1 0x0C50
371#define BCMA_CC_NAND_TIMING_2 0x0C54
372#define BCMA_CC_NAND_SEMAPHORE 0x0C58
373#define BCMA_CC_NAND_DEVID 0x0C60
374#define BCMA_CC_NAND_DEVID_X 0x0C64
375#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
376#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
377#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
378#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
379#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
380#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
381#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
382#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
383#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
384#define BCMA_CC_NAND_READ_ADDR 0x0C94
385#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
386#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
387#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
388#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
389#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
390#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
391#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
392#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
393#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
394#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
395#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
396#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
397#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
398#define BCMA_CC_NAND_SPARE_RD16 0x0D30
399#define BCMA_CC_NAND_SPARE_RD20 0x0D34
400#define BCMA_CC_NAND_SPARE_RD24 0x0D38
401#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
402#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
403#define BCMA_CC_NAND_CACHE_DATA 0x0D44
404#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
405#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200406
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200407/* Divider allocation in 4716/47162/5356 */
408#define BCMA_CC_PMU5_MAINPLL_CPU 1
409#define BCMA_CC_PMU5_MAINPLL_MEM 2
410#define BCMA_CC_PMU5_MAINPLL_SSB 3
411
412/* PLL usage in 4716/47162 */
413#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
414
415/* PLL usage in 5356/5357 */
416#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
417#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
418
419/* 4706 PMU */
420#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
Hauke Mehrtens650cef382012-07-09 22:03:10 +0200421#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
422#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
423#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
424#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
425#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
426#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
427#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
428#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
429#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200430
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200431/* ALP clock on pre-PMU chips */
432#define BCMA_CC_PMU_ALP_CLOCK 20000000
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200433/* HT clock for systems with PMU-enabled chipcommon */
434#define BCMA_CC_PMU_HT_CLOCK 80000000
435
436/* PMU rev 5 (& 6) */
437#define BCMA_CC_PPL_P1P2_OFF 0
438#define BCMA_CC_PPL_P1_MASK 0x0f000000
439#define BCMA_CC_PPL_P1_SHIFT 24
440#define BCMA_CC_PPL_P2_MASK 0x00f00000
441#define BCMA_CC_PPL_P2_SHIFT 20
442#define BCMA_CC_PPL_M14_OFF 1
443#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
444#define BCMA_CC_PPL_MDIV_WIDTH 8
445#define BCMA_CC_PPL_NM5_OFF 2
446#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
447#define BCMA_CC_PPL_NDIV_SHIFT 20
448#define BCMA_CC_PPL_FMAB_OFF 3
449#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
450#define BCMA_CC_PPL_MRAT_SHIFT 28
451#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
452#define BCMA_CC_PPL_ABRAT_SHIFT 27
453#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
454#define BCMA_CC_PPL_PLLCTL_OFF 4
455#define BCMA_CC_PPL_PCHI_OFF 5
456#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200457
Hauke Mehrtensc586e102012-06-30 01:44:44 +0200458#define BCMA_CC_PMU_PLL_CTL0 0
459#define BCMA_CC_PMU_PLL_CTL1 1
460#define BCMA_CC_PMU_PLL_CTL2 2
461#define BCMA_CC_PMU_PLL_CTL3 3
462#define BCMA_CC_PMU_PLL_CTL4 4
463#define BCMA_CC_PMU_PLL_CTL5 5
464
465#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
466#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
467
468#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
469#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
470
Rafał Miłecki984e5be2011-08-11 23:46:44 +0200471/* BCM4331 ChipControl numbers. */
472#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
473#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
474#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
475#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
476#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
477#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
478#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
479#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
480#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
481#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
482#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
483#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
Hauke Mehrtens00eeedc2012-06-30 01:44:37 +0200484#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
Rafał Miłecki984e5be2011-08-11 23:46:44 +0200485#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
486#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
487
Hauke Mehrtensb9562542012-06-30 01:44:41 +0200488/* 43224 chip-specific ChipControl register bits */
489#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
490#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
491#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
492
493/* 4313 Chip specific ChipControl register bits */
494#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
495
Rafał Miłecki3213e1a2012-08-08 19:10:14 +0200496/* BCM5357 ChipControl register bits */
497#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
498#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
499#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
500#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
501#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
502
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200503/* Data for the PMU, if available.
504 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
505 */
506struct bcma_chipcommon_pmu {
507 u8 rev; /* PMU revision */
508 u32 crystalfreq; /* The active crystal frequency (in kHz) */
509};
510
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200511#ifdef CONFIG_BCMA_DRIVER_MIPS
512struct bcma_pflash {
Hauke Mehrtens360dc312012-09-29 20:33:49 +0200513 bool present;
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200514 u8 buswidth;
515 u32 window;
516 u32 window_size;
517};
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200518
Rafał Miłeckid57ef3a2012-08-10 21:23:53 +0200519#ifdef CONFIG_BCMA_SFLASH
520struct bcma_sflash {
521 bool present;
522 u32 window;
523 u32 blocksize;
524 u16 numblocks;
525 u32 size;
Rafał Miłecki5fe42d52012-09-17 11:50:49 +0200526
527 struct mtd_info *mtd;
Rafał Miłeckid57ef3a2012-08-10 21:23:53 +0200528};
529#endif
530
Rafał Miłecki371a0042012-08-12 13:08:05 +0200531#ifdef CONFIG_BCMA_NFLASH
532struct mtd_info;
533
534struct bcma_nflash {
535 bool present;
Hauke Mehrtense661b752012-09-29 20:33:51 +0200536 bool boot; /* This is the flash the SoC boots from */
Rafał Miłecki371a0042012-08-12 13:08:05 +0200537
538 struct mtd_info *mtd;
539};
540#endif
541
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200542struct bcma_serial_port {
543 void *regs;
544 unsigned long clockspeed;
545 unsigned int irq;
546 unsigned int baud_base;
547 unsigned int reg_shift;
548};
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200549#endif /* CONFIG_BCMA_DRIVER_MIPS */
550
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200551struct bcma_drv_cc {
552 struct bcma_device *core;
553 u32 status;
554 u32 capabilities;
555 u32 capabilities_ext;
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200556 u8 setup_done:1;
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200557 u8 early_setup_done:1;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200558 /* Fast Powerup Delay constant */
559 u16 fast_pwrup_delay;
560 struct bcma_chipcommon_pmu pmu;
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200561#ifdef CONFIG_BCMA_DRIVER_MIPS
562 struct bcma_pflash pflash;
Rafał Miłeckid57ef3a2012-08-10 21:23:53 +0200563#ifdef CONFIG_BCMA_SFLASH
564 struct bcma_sflash sflash;
565#endif
Rafał Miłecki371a0042012-08-12 13:08:05 +0200566#ifdef CONFIG_BCMA_NFLASH
567 struct bcma_nflash nflash;
568#endif
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200569
570 int nr_serial_ports;
571 struct bcma_serial_port serial_ports[4];
Hauke Mehrtens21e05342011-07-23 01:20:09 +0200572#endif /* CONFIG_BCMA_DRIVER_MIPS */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200573};
574
575/* Register access */
576#define bcma_cc_read32(cc, offset) \
577 bcma_read32((cc)->core, offset)
578#define bcma_cc_write32(cc, offset, val) \
579 bcma_write32((cc)->core, offset, val)
580
581#define bcma_cc_mask32(cc, offset, mask) \
582 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
583#define bcma_cc_set32(cc, offset, set) \
584 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
585#define bcma_cc_maskset32(cc, offset, mask, set) \
586 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
587
588extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200589extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200590
591extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
592extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
593
Rafał Miłecki984e5be2011-08-11 23:46:44 +0200594void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
595
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200596extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
597 u32 ticks);
598
599void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
600
601u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
602
603/* Chipcommon GPIO pin access. */
604u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
605u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
606u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
607u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
608u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
609u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
610
611/* PMU support */
612extern void bcma_pmu_init(struct bcma_drv_cc *cc);
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200613extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200614
Rafał Miłecki3861b2c2011-09-16 12:33:58 +0200615extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
616 u32 value);
617extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
618 u32 mask, u32 set);
619extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
620 u32 offset, u32 mask, u32 set);
621extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
622 u32 offset, u32 mask, u32 set);
Hauke Mehrtensc586e102012-06-30 01:44:44 +0200623extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
Rafał Miłecki3861b2c2011-09-16 12:33:58 +0200624
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200625#endif /* LINUX_BCMA_DRIVER_CC_H_ */