M R Swami Reddy | dbf7a73 | 2012-03-30 16:03:43 +0530 | [diff] [blame] | 1 | /* |
| 2 | * lm49453.c - LM49453 ALSA Soc Audio driver |
| 3 | * |
| 4 | * Copyright (c) 2012 Texas Instruments, Inc |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * Initially based on sound/soc/codecs/wm8350.c |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/version.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/pm.h> |
| 20 | #include <linux/i2c.h> |
| 21 | #include <linux/regmap.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <sound/core.h> |
| 24 | #include <sound/pcm.h> |
| 25 | #include <sound/pcm_params.h> |
| 26 | #include <sound/soc.h> |
| 27 | #include <sound/soc-dapm.h> |
| 28 | #include <sound/tlv.h> |
| 29 | #include <sound/jack.h> |
| 30 | #include <sound/initval.h> |
| 31 | #include <asm/div64.h> |
| 32 | #include "lm49453.h" |
| 33 | |
| 34 | static struct reg_default lm49453_reg_defs[] = { |
| 35 | { 0, 0x00 }, |
| 36 | { 1, 0x00 }, |
| 37 | { 2, 0x00 }, |
| 38 | { 3, 0x00 }, |
| 39 | { 4, 0x00 }, |
| 40 | { 5, 0x00 }, |
| 41 | { 6, 0x00 }, |
| 42 | { 7, 0x00 }, |
| 43 | { 8, 0x00 }, |
| 44 | { 9, 0x00 }, |
| 45 | { 10, 0x00 }, |
| 46 | { 11, 0x00 }, |
| 47 | { 12, 0x00 }, |
| 48 | { 13, 0x00 }, |
| 49 | { 14, 0x00 }, |
| 50 | { 15, 0x00 }, |
| 51 | { 16, 0x00 }, |
| 52 | { 17, 0x00 }, |
| 53 | { 18, 0x00 }, |
| 54 | { 19, 0x00 }, |
| 55 | { 20, 0x00 }, |
| 56 | { 21, 0x00 }, |
| 57 | { 22, 0x00 }, |
| 58 | { 23, 0x00 }, |
| 59 | { 32, 0x00 }, |
| 60 | { 33, 0x00 }, |
| 61 | { 35, 0x00 }, |
| 62 | { 36, 0x00 }, |
| 63 | { 37, 0x00 }, |
| 64 | { 46, 0x00 }, |
| 65 | { 48, 0x00 }, |
| 66 | { 49, 0x00 }, |
| 67 | { 51, 0x00 }, |
| 68 | { 56, 0x00 }, |
| 69 | { 58, 0x00 }, |
| 70 | { 59, 0x00 }, |
| 71 | { 60, 0x00 }, |
| 72 | { 61, 0x00 }, |
| 73 | { 62, 0x00 }, |
| 74 | { 63, 0x00 }, |
| 75 | { 64, 0x00 }, |
| 76 | { 65, 0x00 }, |
| 77 | { 66, 0x00 }, |
| 78 | { 67, 0x00 }, |
| 79 | { 68, 0x00 }, |
| 80 | { 69, 0x00 }, |
| 81 | { 70, 0x00 }, |
| 82 | { 71, 0x00 }, |
| 83 | { 72, 0x00 }, |
| 84 | { 73, 0x00 }, |
| 85 | { 74, 0x00 }, |
| 86 | { 75, 0x00 }, |
| 87 | { 76, 0x00 }, |
| 88 | { 77, 0x00 }, |
| 89 | { 78, 0x00 }, |
| 90 | { 79, 0x00 }, |
| 91 | { 80, 0x00 }, |
| 92 | { 81, 0x00 }, |
| 93 | { 82, 0x00 }, |
| 94 | { 83, 0x00 }, |
| 95 | { 85, 0x00 }, |
| 96 | { 85, 0x00 }, |
| 97 | { 86, 0x00 }, |
| 98 | { 87, 0x00 }, |
| 99 | { 88, 0x00 }, |
| 100 | { 89, 0x00 }, |
| 101 | { 90, 0x00 }, |
| 102 | { 91, 0x00 }, |
| 103 | { 92, 0x00 }, |
| 104 | { 93, 0x00 }, |
| 105 | { 94, 0x00 }, |
| 106 | { 95, 0x00 }, |
| 107 | { 96, 0x01 }, |
| 108 | { 97, 0x00 }, |
| 109 | { 98, 0x00 }, |
| 110 | { 99, 0x00 }, |
| 111 | { 100, 0x00 }, |
| 112 | { 101, 0x00 }, |
| 113 | { 102, 0x00 }, |
| 114 | { 103, 0x01 }, |
| 115 | { 105, 0x01 }, |
| 116 | { 106, 0x00 }, |
| 117 | { 107, 0x01 }, |
| 118 | { 107, 0x00 }, |
| 119 | { 108, 0x00 }, |
| 120 | { 109, 0x00 }, |
| 121 | { 110, 0x00 }, |
| 122 | { 111, 0x02 }, |
| 123 | { 112, 0x02 }, |
| 124 | { 113, 0x00 }, |
| 125 | { 121, 0x80 }, |
| 126 | { 122, 0xBB }, |
| 127 | { 123, 0x80 }, |
| 128 | { 124, 0xBB }, |
| 129 | { 128, 0x00 }, |
| 130 | { 130, 0x00 }, |
| 131 | { 131, 0x00 }, |
| 132 | { 132, 0x00 }, |
| 133 | { 133, 0x0A }, |
| 134 | { 134, 0x0A }, |
| 135 | { 135, 0x0A }, |
| 136 | { 136, 0x0F }, |
| 137 | { 137, 0x00 }, |
| 138 | { 138, 0x73 }, |
| 139 | { 139, 0x33 }, |
| 140 | { 140, 0x73 }, |
| 141 | { 141, 0x33 }, |
| 142 | { 142, 0x73 }, |
| 143 | { 143, 0x33 }, |
| 144 | { 144, 0x73 }, |
| 145 | { 145, 0x33 }, |
| 146 | { 146, 0x73 }, |
| 147 | { 147, 0x33 }, |
| 148 | { 148, 0x73 }, |
| 149 | { 149, 0x33 }, |
| 150 | { 150, 0x73 }, |
| 151 | { 151, 0x33 }, |
| 152 | { 152, 0x00 }, |
| 153 | { 153, 0x00 }, |
| 154 | { 154, 0x00 }, |
| 155 | { 155, 0x00 }, |
| 156 | { 176, 0x00 }, |
| 157 | { 177, 0x00 }, |
| 158 | { 178, 0x00 }, |
| 159 | { 179, 0x00 }, |
| 160 | { 180, 0x00 }, |
| 161 | { 181, 0x00 }, |
| 162 | { 182, 0x00 }, |
| 163 | { 183, 0x00 }, |
| 164 | { 184, 0x00 }, |
| 165 | { 185, 0x00 }, |
| 166 | { 186, 0x00 }, |
| 167 | { 189, 0x00 }, |
| 168 | { 188, 0x00 }, |
| 169 | { 194, 0x00 }, |
| 170 | { 195, 0x00 }, |
| 171 | { 196, 0x00 }, |
| 172 | { 197, 0x00 }, |
| 173 | { 200, 0x00 }, |
| 174 | { 201, 0x00 }, |
| 175 | { 202, 0x00 }, |
| 176 | { 203, 0x00 }, |
| 177 | { 204, 0x00 }, |
| 178 | { 205, 0x00 }, |
| 179 | { 208, 0x00 }, |
| 180 | { 209, 0x00 }, |
| 181 | { 210, 0x00 }, |
| 182 | { 211, 0x00 }, |
| 183 | { 213, 0x00 }, |
| 184 | { 214, 0x00 }, |
| 185 | { 215, 0x00 }, |
| 186 | { 216, 0x00 }, |
| 187 | { 217, 0x00 }, |
| 188 | { 218, 0x00 }, |
| 189 | { 219, 0x00 }, |
| 190 | { 221, 0x00 }, |
| 191 | { 222, 0x00 }, |
| 192 | { 224, 0x00 }, |
| 193 | { 225, 0x00 }, |
| 194 | { 226, 0x00 }, |
| 195 | { 227, 0x00 }, |
| 196 | { 228, 0x00 }, |
| 197 | { 229, 0x00 }, |
| 198 | { 230, 0x13 }, |
| 199 | { 231, 0x00 }, |
| 200 | { 232, 0x80 }, |
| 201 | { 233, 0x0C }, |
| 202 | { 234, 0xDD }, |
| 203 | { 235, 0x00 }, |
| 204 | { 236, 0x04 }, |
| 205 | { 237, 0x00 }, |
| 206 | { 238, 0x00 }, |
| 207 | { 239, 0x00 }, |
| 208 | { 240, 0x00 }, |
| 209 | { 241, 0x00 }, |
| 210 | { 242, 0x00 }, |
| 211 | { 243, 0x00 }, |
| 212 | { 244, 0x00 }, |
| 213 | { 245, 0x00 }, |
| 214 | { 248, 0x00 }, |
| 215 | { 249, 0x00 }, |
| 216 | { 254, 0x00 }, |
| 217 | { 255, 0x00 }, |
| 218 | }; |
| 219 | |
| 220 | /* codec private data */ |
| 221 | struct lm49453_priv { |
| 222 | struct regmap *regmap; |
| 223 | int fs_rate; |
| 224 | }; |
| 225 | |
| 226 | /* capture path controls */ |
| 227 | |
| 228 | static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"}; |
| 229 | |
| 230 | static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5, |
| 231 | lm49453_mic2mode_text); |
| 232 | |
| 233 | static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"}; |
| 234 | |
| 235 | static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum, |
| 236 | LM49453_P0_DIGITAL_MIC1_CONFIG_REG, |
| 237 | 7, lm49453_dmic_cfg_text); |
| 238 | |
| 239 | static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum, |
| 240 | LM49453_P0_DIGITAL_MIC2_CONFIG_REG, |
| 241 | 7, lm49453_dmic_cfg_text); |
| 242 | |
| 243 | /* MUX Controls */ |
| 244 | static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" }; |
| 245 | |
| 246 | static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" }; |
| 247 | |
| 248 | static const struct soc_enum lm49453_adcl_enum = |
| 249 | SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0, |
| 250 | ARRAY_SIZE(lm49453_adcl_mux_text), |
| 251 | lm49453_adcl_mux_text); |
| 252 | |
| 253 | static const struct soc_enum lm49453_adcr_enum = |
| 254 | SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1, |
| 255 | ARRAY_SIZE(lm49453_adcr_mux_text), |
| 256 | lm49453_adcr_mux_text); |
| 257 | |
| 258 | static const struct snd_kcontrol_new lm49453_adcl_mux_control = |
| 259 | SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum); |
| 260 | |
| 261 | static const struct snd_kcontrol_new lm49453_adcr_mux_control = |
| 262 | SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum); |
| 263 | |
| 264 | static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = { |
| 265 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0), |
| 266 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0), |
| 267 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0), |
| 268 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0), |
| 269 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0), |
| 270 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0), |
| 271 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0), |
| 272 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0), |
| 273 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0), |
| 274 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0), |
| 275 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0), |
| 276 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0), |
| 277 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0), |
| 278 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0), |
| 279 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0), |
| 280 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0), |
| 281 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0), |
| 282 | }; |
| 283 | |
| 284 | static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = { |
| 285 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0), |
| 286 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0), |
| 287 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0), |
| 288 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0), |
| 289 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0), |
| 290 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0), |
| 291 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0), |
| 292 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0), |
| 293 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0), |
| 294 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0), |
| 295 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0), |
| 296 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0), |
| 297 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0), |
| 298 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0), |
| 299 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0), |
| 300 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0), |
| 301 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0), |
| 302 | }; |
| 303 | |
| 304 | static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = { |
| 305 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0), |
| 306 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0), |
| 307 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0), |
| 308 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0), |
| 309 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0), |
| 310 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0), |
| 311 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0), |
| 312 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0), |
| 313 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0), |
| 314 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0), |
| 315 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0), |
| 316 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0), |
| 317 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0), |
| 318 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0), |
| 319 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0), |
| 320 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0), |
| 321 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0), |
| 322 | }; |
| 323 | |
| 324 | static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = { |
| 325 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0), |
| 326 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0), |
| 327 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0), |
| 328 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0), |
| 329 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0), |
| 330 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0), |
| 331 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0), |
| 332 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0), |
| 333 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0), |
| 334 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0), |
| 335 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0), |
| 336 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0), |
| 337 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0), |
| 338 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0), |
| 339 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0), |
| 340 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0), |
| 341 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0), |
| 342 | }; |
| 343 | |
| 344 | static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = { |
| 345 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0), |
| 346 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0), |
| 347 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0), |
| 348 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0), |
| 349 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0), |
| 350 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0), |
| 351 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0), |
| 352 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0), |
| 353 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0), |
| 354 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0), |
| 355 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0), |
| 356 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0), |
| 357 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0), |
| 358 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0), |
| 359 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0), |
| 360 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0), |
| 361 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0), |
| 362 | }; |
| 363 | |
| 364 | static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = { |
| 365 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0), |
| 366 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0), |
| 367 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0), |
| 368 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0), |
| 369 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0), |
| 370 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0), |
| 371 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0), |
| 372 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0), |
| 373 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0), |
| 374 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0), |
| 375 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0), |
| 376 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0), |
| 377 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0), |
| 378 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0), |
| 379 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0), |
| 380 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0), |
| 381 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0), |
| 382 | }; |
| 383 | |
| 384 | static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = { |
| 385 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0), |
| 386 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0), |
| 387 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0), |
| 388 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0), |
| 389 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0), |
| 390 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0), |
| 391 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0), |
| 392 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0), |
| 393 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0), |
| 394 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0), |
| 395 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0), |
| 396 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0), |
| 397 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0), |
| 398 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0), |
| 399 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0), |
| 400 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0), |
| 401 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0), |
| 402 | }; |
| 403 | |
| 404 | static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = { |
| 405 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0), |
| 406 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0), |
| 407 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0), |
| 408 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0), |
| 409 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0), |
| 410 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0), |
| 411 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0), |
| 412 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0), |
| 413 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0), |
| 414 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0), |
| 415 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0), |
| 416 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0), |
| 417 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0), |
| 418 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0), |
| 419 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0), |
| 420 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0), |
| 421 | SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0), |
| 422 | }; |
| 423 | |
| 424 | static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = { |
| 425 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0), |
| 426 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0), |
| 427 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0), |
| 428 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0), |
| 429 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0), |
| 430 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0), |
| 431 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0), |
| 432 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0), |
| 433 | }; |
| 434 | |
| 435 | static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = { |
| 436 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0), |
| 437 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0), |
| 438 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0), |
| 439 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0), |
| 440 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0), |
| 441 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0), |
| 442 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0), |
| 443 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0), |
| 444 | }; |
| 445 | |
| 446 | static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = { |
| 447 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0), |
| 448 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0), |
| 449 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0), |
| 450 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0), |
| 451 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0), |
| 452 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0), |
| 453 | SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0), |
| 454 | }; |
| 455 | |
| 456 | static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = { |
| 457 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0), |
| 458 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0), |
| 459 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0), |
| 460 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0), |
| 461 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0), |
| 462 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0), |
| 463 | SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0), |
| 464 | }; |
| 465 | |
| 466 | static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = { |
| 467 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0), |
| 468 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0), |
| 469 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0), |
| 470 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0), |
| 471 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0), |
| 472 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0), |
| 473 | SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0), |
| 474 | }; |
| 475 | |
| 476 | static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = { |
| 477 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0), |
| 478 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0), |
| 479 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0), |
| 480 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0), |
| 481 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0), |
| 482 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0), |
| 483 | SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0), |
| 484 | }; |
| 485 | |
| 486 | static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = { |
| 487 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0), |
| 488 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0), |
| 489 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0), |
| 490 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0), |
| 491 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0), |
| 492 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0), |
| 493 | SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0), |
| 494 | }; |
| 495 | |
| 496 | static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = { |
| 497 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0), |
| 498 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0), |
| 499 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0), |
| 500 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0), |
| 501 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0), |
| 502 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0), |
| 503 | SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0), |
| 504 | }; |
| 505 | |
| 506 | static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = { |
| 507 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0), |
| 508 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0), |
| 509 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0), |
| 510 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0), |
| 511 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0), |
| 512 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0), |
| 513 | SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0), |
| 514 | SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0), |
| 515 | }; |
| 516 | |
| 517 | static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = { |
| 518 | SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0), |
| 519 | SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0), |
| 520 | SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0), |
| 521 | SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0), |
| 522 | SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0), |
| 523 | SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0), |
| 524 | SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0), |
| 525 | SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0), |
| 526 | }; |
| 527 | |
| 528 | /* TLV Declarations */ |
| 529 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7650, 150, 1); |
| 530 | static const DECLARE_TLV_DB_SCALE(port_tlv, 0, 600, 0); |
| 531 | |
| 532 | static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = { |
| 533 | /* Sidetone supports mono only */ |
| 534 | SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG, |
| 535 | 0, 0x3F, 0, digital_tlv), |
| 536 | SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG, |
| 537 | 0, 0x3F, 0, digital_tlv), |
| 538 | SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG, |
| 539 | 0, 0x3F, 0, digital_tlv), |
| 540 | SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG, |
| 541 | 0, 0x3F, 0, digital_tlv), |
| 542 | SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG, |
| 543 | 0, 0x3F, 0, digital_tlv), |
| 544 | SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG, |
| 545 | 0, 0x3F, 0, digital_tlv), |
| 546 | }; |
| 547 | |
| 548 | static const struct snd_kcontrol_new lm49453_snd_controls[] = { |
| 549 | /* mic1 and mic2 supports mono only */ |
| 550 | SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_ADC_LEVELL_REG, 0, 6, |
| 551 | 0, digital_tlv), |
| 552 | SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_ADC_LEVELR_REG, 0, 6, |
| 553 | 0, digital_tlv), |
| 554 | |
| 555 | SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG, |
| 556 | LM49453_P0_DMIC1_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 557 | SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG, |
| 558 | LM49453_P0_DMIC2_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 559 | |
| 560 | SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum), |
| 561 | SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum), |
| 562 | SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum), |
| 563 | |
| 564 | /* Capture path filter enable */ |
| 565 | SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, |
| 566 | 0, 1, 0), |
| 567 | SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, |
| 568 | 1, 1, 0), |
| 569 | SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG, |
| 570 | 2, 1, 0), |
| 571 | |
| 572 | SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG, |
| 573 | LM49453_P0_DAC_HP_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 574 | SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG, |
| 575 | LM49453_P0_DAC_LO_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 576 | SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG, |
| 577 | LM49453_P0_DAC_LS_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 578 | SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG, |
| 579 | LM49453_P0_DAC_HA_LEVELR_REG, 0, 6, 0, digital_tlv), |
| 580 | |
| 581 | SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG, |
| 582 | 0, 6, 0, digital_tlv), |
| 583 | |
| 584 | SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, |
| 585 | 0, 3, 0, port_tlv), |
| 586 | SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, |
| 587 | 2, 3, 0, port_tlv), |
| 588 | SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, |
| 589 | 4, 3, 0, port_tlv), |
| 590 | SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG, |
| 591 | 6, 3, 0, port_tlv), |
| 592 | SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, |
| 593 | 0, 3, 0, port_tlv), |
| 594 | SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, |
| 595 | 2, 3, 0, port_tlv), |
| 596 | SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, |
| 597 | 4, 3, 0, port_tlv), |
| 598 | SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG, |
| 599 | 6, 3, 0, port_tlv), |
| 600 | |
| 601 | SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG, |
| 602 | 0, 3, 0, port_tlv), |
| 603 | SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG, |
| 604 | 2, 3, 0, port_tlv), |
| 605 | |
| 606 | SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG, |
| 607 | 1, 1, 0), |
| 608 | SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG, |
| 609 | 1, 1, 0), |
| 610 | SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG, |
| 611 | 2, 1, 0), |
| 612 | SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG, |
| 613 | 2, 1, 0) |
| 614 | |
| 615 | }; |
| 616 | |
| 617 | /* DAPM widgets */ |
| 618 | static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = { |
| 619 | |
| 620 | /* All end points HP,EP, LS, Lineout and Haptic */ |
| 621 | SND_SOC_DAPM_OUTPUT("HPOUTL"), |
| 622 | SND_SOC_DAPM_OUTPUT("HPOUTR"), |
| 623 | SND_SOC_DAPM_OUTPUT("EPOUT"), |
| 624 | SND_SOC_DAPM_OUTPUT("LSOUTL"), |
| 625 | SND_SOC_DAPM_OUTPUT("LSOUTR"), |
| 626 | SND_SOC_DAPM_OUTPUT("LOOUTR"), |
| 627 | SND_SOC_DAPM_OUTPUT("LOOUTL"), |
| 628 | SND_SOC_DAPM_OUTPUT("HAOUTL"), |
| 629 | SND_SOC_DAPM_OUTPUT("HAOUTR"), |
| 630 | |
| 631 | SND_SOC_DAPM_INPUT("AMIC1"), |
| 632 | SND_SOC_DAPM_INPUT("AMIC2"), |
| 633 | SND_SOC_DAPM_INPUT("DMIC1DAT"), |
| 634 | SND_SOC_DAPM_INPUT("DMIC2DAT"), |
| 635 | SND_SOC_DAPM_INPUT("AUXL"), |
| 636 | SND_SOC_DAPM_INPUT("AUXR"), |
| 637 | |
| 638 | SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 639 | SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 640 | SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 641 | SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 642 | SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 643 | SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 644 | SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 645 | SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 646 | SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 647 | SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 648 | |
| 649 | SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0), |
| 650 | SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0), |
| 651 | |
| 652 | /* playback path driver enables */ |
| 653 | SND_SOC_DAPM_OUT_DRV("Headset Switch", |
| 654 | LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0), |
| 655 | SND_SOC_DAPM_OUT_DRV("Earpiece Switch", |
| 656 | LM49453_P0_EP_REG, 0, 0, NULL, 0), |
| 657 | SND_SOC_DAPM_OUT_DRV("Speaker Left Switch", |
| 658 | LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0), |
| 659 | SND_SOC_DAPM_OUT_DRV("Speaker Right Switch", |
| 660 | LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0), |
| 661 | SND_SOC_DAPM_OUT_DRV("Haptic Left Switch", |
| 662 | LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0), |
| 663 | SND_SOC_DAPM_OUT_DRV("Haptic Right Switch", |
| 664 | LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0), |
| 665 | |
| 666 | /* DAC */ |
| 667 | SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0), |
| 668 | SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0), |
| 669 | SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0), |
| 670 | SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0), |
| 671 | SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0), |
| 672 | SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0), |
| 673 | SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0), |
| 674 | SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0), |
| 675 | |
| 676 | |
| 677 | SND_SOC_DAPM_PGA("AUXL Input", |
| 678 | LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0), |
| 679 | SND_SOC_DAPM_PGA("AUXR Input", |
| 680 | LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0), |
| 681 | |
| 682 | SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 683 | |
| 684 | /* ADC */ |
| 685 | SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0), |
| 686 | SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0), |
| 687 | SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0), |
| 688 | SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0), |
| 689 | |
| 690 | SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0), |
| 691 | SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0), |
| 692 | |
| 693 | SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0, |
| 694 | &lm49453_adcl_mux_control), |
| 695 | SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, |
| 696 | &lm49453_adcr_mux_control), |
| 697 | |
| 698 | SND_SOC_DAPM_MUX("Mic1 Input", |
| 699 | SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control), |
| 700 | |
| 701 | SND_SOC_DAPM_MUX("Mic2 Input", |
| 702 | SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control), |
| 703 | |
| 704 | /* AIF */ |
| 705 | SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0, |
| 706 | LM49453_P0_PULL_CONFIG1_REG, 2, 0), |
| 707 | SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0, |
| 708 | LM49453_P0_PULL_CONFIG1_REG, 6, 0), |
| 709 | |
| 710 | SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0, |
| 711 | LM49453_P0_PULL_CONFIG1_REG, 3, 0), |
| 712 | SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0, |
| 713 | LM49453_P0_PULL_CONFIG1_REG, 7, 0), |
| 714 | |
| 715 | /* Port1 TX controls */ |
| 716 | SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 717 | SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 718 | SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 719 | SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 720 | SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 721 | SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 722 | SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 723 | SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 724 | |
| 725 | /* Port2 TX controls */ |
| 726 | SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 727 | SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 728 | |
| 729 | /* Sidetone Mixer */ |
| 730 | SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0, |
| 731 | lm49453_sidetone_mixer_controls, |
| 732 | ARRAY_SIZE(lm49453_sidetone_mixer_controls)), |
| 733 | |
| 734 | /* DAC MIXERS */ |
| 735 | SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, |
| 736 | lm49453_headset_left_mixer, |
| 737 | ARRAY_SIZE(lm49453_headset_left_mixer)), |
| 738 | SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, |
| 739 | lm49453_headset_right_mixer, |
| 740 | ARRAY_SIZE(lm49453_headset_right_mixer)), |
| 741 | SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0, |
| 742 | lm49453_lineout_left_mixer, |
| 743 | ARRAY_SIZE(lm49453_lineout_left_mixer)), |
| 744 | SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0, |
| 745 | lm49453_lineout_right_mixer, |
| 746 | ARRAY_SIZE(lm49453_lineout_right_mixer)), |
| 747 | SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0, |
| 748 | lm49453_speaker_left_mixer, |
| 749 | ARRAY_SIZE(lm49453_speaker_left_mixer)), |
| 750 | SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0, |
| 751 | lm49453_speaker_right_mixer, |
| 752 | ARRAY_SIZE(lm49453_speaker_right_mixer)), |
| 753 | SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0, |
| 754 | lm49453_haptic_left_mixer, |
| 755 | ARRAY_SIZE(lm49453_haptic_left_mixer)), |
| 756 | SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0, |
| 757 | lm49453_haptic_right_mixer, |
| 758 | ARRAY_SIZE(lm49453_haptic_right_mixer)), |
| 759 | |
| 760 | /* Capture Mixer */ |
| 761 | SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0, |
| 762 | lm49453_port1_tx1_mixer, |
| 763 | ARRAY_SIZE(lm49453_port1_tx1_mixer)), |
| 764 | SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0, |
| 765 | lm49453_port1_tx2_mixer, |
| 766 | ARRAY_SIZE(lm49453_port1_tx2_mixer)), |
| 767 | SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0, |
| 768 | lm49453_port1_tx3_mixer, |
| 769 | ARRAY_SIZE(lm49453_port1_tx3_mixer)), |
| 770 | SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0, |
| 771 | lm49453_port1_tx4_mixer, |
| 772 | ARRAY_SIZE(lm49453_port1_tx4_mixer)), |
| 773 | SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0, |
| 774 | lm49453_port1_tx5_mixer, |
| 775 | ARRAY_SIZE(lm49453_port1_tx5_mixer)), |
| 776 | SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0, |
| 777 | lm49453_port1_tx6_mixer, |
| 778 | ARRAY_SIZE(lm49453_port1_tx6_mixer)), |
| 779 | SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0, |
| 780 | lm49453_port1_tx7_mixer, |
| 781 | ARRAY_SIZE(lm49453_port1_tx7_mixer)), |
| 782 | SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0, |
| 783 | lm49453_port1_tx8_mixer, |
| 784 | ARRAY_SIZE(lm49453_port1_tx8_mixer)), |
| 785 | |
| 786 | SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0, |
| 787 | lm49453_port2_tx1_mixer, |
| 788 | ARRAY_SIZE(lm49453_port2_tx1_mixer)), |
| 789 | SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0, |
| 790 | lm49453_port2_tx2_mixer, |
| 791 | ARRAY_SIZE(lm49453_port2_tx2_mixer)), |
| 792 | }; |
| 793 | |
| 794 | static const struct snd_soc_dapm_route lm49453_audio_map[] = { |
| 795 | /* Port SDI mapping */ |
| 796 | { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 797 | { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 798 | { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 799 | { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 800 | { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 801 | { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 802 | { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 803 | { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" }, |
| 804 | |
| 805 | { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" }, |
| 806 | { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" }, |
| 807 | |
| 808 | /* HP mapping */ |
| 809 | { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 810 | { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 811 | { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 812 | { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 813 | { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 814 | { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 815 | { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 816 | { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 817 | |
| 818 | { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 819 | { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 820 | |
| 821 | { "HPL Mixer", "ADCL Switch", "ADC Left" }, |
| 822 | { "HPL Mixer", "ADCR Switch", "ADC Right" }, |
| 823 | { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 824 | { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 825 | { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 826 | { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 827 | { "HPL Mixer", "Sidetone Switch", "Sidetone" }, |
| 828 | |
| 829 | { "HPL DAC", NULL, "HPL Mixer" }, |
| 830 | |
| 831 | { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 832 | { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 833 | { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 834 | { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 835 | { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 836 | { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 837 | { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 838 | { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 839 | |
| 840 | /* Port 2 */ |
| 841 | { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 842 | { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 843 | |
| 844 | { "HPR Mixer", "ADCL Switch", "ADC Left" }, |
| 845 | { "HPR Mixer", "ADCR Switch", "ADC Right" }, |
| 846 | { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 847 | { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 848 | { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 849 | { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" }, |
| 850 | { "HPR Mixer", "Sidetone Switch", "Sidetone" }, |
| 851 | |
| 852 | { "HPR DAC", NULL, "HPR Mixer" }, |
| 853 | |
| 854 | { "HPOUTL", "Headset Switch", "HPL DAC"}, |
| 855 | { "HPOUTR", "Headset Switch", "HPR DAC"}, |
| 856 | |
| 857 | /* EP map */ |
| 858 | { "EPOUT", "Earpiece Switch", "HPL DAC" }, |
| 859 | |
| 860 | /* Speaker map */ |
| 861 | { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 862 | { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 863 | { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 864 | { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 865 | { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 866 | { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 867 | { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 868 | { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 869 | |
| 870 | /* Port 2 */ |
| 871 | { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 872 | { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 873 | |
| 874 | { "LSL Mixer", "ADCL Switch", "ADC Left" }, |
| 875 | { "LSL Mixer", "ADCR Switch", "ADC Right" }, |
| 876 | { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 877 | { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 878 | { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 879 | { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 880 | { "LSL Mixer", "Sidetone Switch", "Sidetone" }, |
| 881 | |
| 882 | { "LSL DAC", NULL, "LSL Mixer" }, |
| 883 | |
| 884 | { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 885 | { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 886 | { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 887 | { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 888 | { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 889 | { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 890 | { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 891 | { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 892 | |
| 893 | /* Port 2 */ |
| 894 | { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 895 | { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 896 | |
| 897 | { "LSR Mixer", "ADCL Switch", "ADC Left" }, |
| 898 | { "LSR Mixer", "ADCR Switch", "ADC Right" }, |
| 899 | { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 900 | { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 901 | { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 902 | { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 903 | { "LSR Mixer", "Sidetone Switch", "Sidetone" }, |
| 904 | |
| 905 | { "LSR DAC", NULL, "LSR Mixer" }, |
| 906 | |
| 907 | { "LSOUTL", "Speaker Left Switch", "LSL DAC"}, |
| 908 | { "LSOUTR", "Speaker Left Switch", "LSR DAC"}, |
| 909 | |
| 910 | /* Haptic map */ |
| 911 | { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 912 | { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 913 | { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 914 | { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 915 | { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 916 | { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 917 | { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 918 | { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 919 | |
| 920 | /* Port 2 */ |
| 921 | { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 922 | { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 923 | |
| 924 | { "HAL Mixer", "ADCL Switch", "ADC Left" }, |
| 925 | { "HAL Mixer", "ADCR Switch", "ADC Right" }, |
| 926 | { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 927 | { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 928 | { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 929 | { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 930 | { "HAL Mixer", "Sidetone Switch", "Sidetone" }, |
| 931 | |
| 932 | { "HAL DAC", NULL, "HAL Mixer" }, |
| 933 | |
| 934 | { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 935 | { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 936 | { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 937 | { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 938 | { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 939 | { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 940 | { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 941 | { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 942 | |
| 943 | /* Port 2 */ |
| 944 | { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 945 | { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 946 | |
| 947 | { "HAR Mixer", "ADCL Switch", "ADC Left" }, |
| 948 | { "HAR Mixer", "ADCR Switch", "ADC Right" }, |
| 949 | { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 950 | { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 951 | { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 952 | { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 953 | { "HAR Mixer", "Sideton Switch", "Sidetone" }, |
| 954 | |
| 955 | { "HAR DAC", NULL, "HAR Mixer" }, |
| 956 | |
| 957 | { "HAOUTL", "Haptic Left Switch", "HAL DAC" }, |
| 958 | { "HAOUTR", "Haptic Right Switch", "HAR DAC" }, |
| 959 | |
| 960 | /* Lineout map */ |
| 961 | { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 962 | { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 963 | { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 964 | { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 965 | { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 966 | { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 967 | { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 968 | { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 969 | |
| 970 | /* Port 2 */ |
| 971 | { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 972 | { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 973 | |
| 974 | { "LOL Mixer", "ADCL Switch", "ADC Left" }, |
| 975 | { "LOL Mixer", "ADCR Switch", "ADC Right" }, |
| 976 | { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 977 | { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 978 | { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 979 | { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 980 | { "LOL Mixer", "Sidetone Switch", "Sidetone" }, |
| 981 | |
| 982 | { "LOL DAC", NULL, "LOL Mixer" }, |
| 983 | |
| 984 | { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" }, |
| 985 | { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" }, |
| 986 | { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" }, |
| 987 | { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" }, |
| 988 | { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" }, |
| 989 | { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" }, |
| 990 | { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" }, |
| 991 | { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" }, |
| 992 | |
| 993 | /* Port 2 */ |
| 994 | { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" }, |
| 995 | { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" }, |
| 996 | |
| 997 | { "LOR Mixer", "ADCL Switch", "ADC Left" }, |
| 998 | { "LOR Mixer", "ADCR Switch", "ADC Right" }, |
| 999 | { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1000 | { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1001 | { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1002 | { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1003 | { "LOR Mixer", "Sidetone Switch", "Sidetone" }, |
| 1004 | |
| 1005 | { "LOR DAC", NULL, "LOR Mixer" }, |
| 1006 | |
| 1007 | { "LOOUTL", NULL, "LOL DAC" }, |
| 1008 | { "LOOUTR", NULL, "LOR DAC" }, |
| 1009 | |
| 1010 | /* TX map */ |
| 1011 | /* Port1 mappings */ |
| 1012 | { "Port1_1 Mixer", "ADCL Switch", "ADC Left" }, |
| 1013 | { "Port1_1 Mixer", "ADCR Switch", "ADC Right" }, |
| 1014 | { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1015 | { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1016 | { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1017 | { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1018 | |
| 1019 | { "Port1_2 Mixer", "ADCL Switch", "ADC Left" }, |
| 1020 | { "Port1_2 Mixer", "ADCR Switch", "ADC Right" }, |
| 1021 | { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1022 | { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1023 | { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1024 | { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1025 | |
| 1026 | { "Port1_3 Mixer", "ADCL Switch", "ADC Left" }, |
| 1027 | { "Port1_3 Mixer", "ADCR Switch", "ADC Right" }, |
| 1028 | { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1029 | { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1030 | { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1031 | { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1032 | |
| 1033 | { "Port1_4 Mixer", "ADCL Switch", "ADC Left" }, |
| 1034 | { "Port1_4 Mixer", "ADCR Switch", "ADC Right" }, |
| 1035 | { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1036 | { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1037 | { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1038 | { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1039 | |
| 1040 | { "Port1_5 Mixer", "ADCL Switch", "ADC Left" }, |
| 1041 | { "Port1_5 Mixer", "ADCR Switch", "ADC Right" }, |
| 1042 | { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1043 | { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1044 | { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1045 | { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1046 | |
| 1047 | { "Port1_6 Mixer", "ADCL Switch", "ADC Left" }, |
| 1048 | { "Port1_6 Mixer", "ADCR Switch", "ADC Right" }, |
| 1049 | { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1050 | { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1051 | { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1052 | { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1053 | |
| 1054 | { "Port1_7 Mixer", "ADCL Switch", "ADC Left" }, |
| 1055 | { "Port1_7 Mixer", "ADCR Switch", "ADC Right" }, |
| 1056 | { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1057 | { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1058 | { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1059 | { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1060 | |
| 1061 | { "Port1_8 Mixer", "ADCL Switch", "ADC Left" }, |
| 1062 | { "Port1_8 Mixer", "ADCR Switch", "ADC Right" }, |
| 1063 | { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1064 | { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1065 | { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1066 | { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1067 | |
| 1068 | { "Port2_1 Mixer", "ADCL Switch", "ADC Left" }, |
| 1069 | { "Port2_1 Mixer", "ADCR Switch", "ADC Right" }, |
| 1070 | { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1071 | { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1072 | { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1073 | { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1074 | |
| 1075 | { "Port2_2 Mixer", "ADCL Switch", "ADC Left" }, |
| 1076 | { "Port2_2 Mixer", "ADCR Switch", "ADC Right" }, |
| 1077 | { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" }, |
| 1078 | { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" }, |
| 1079 | { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" }, |
| 1080 | { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" }, |
| 1081 | |
| 1082 | { "P1_1_TX", NULL, "Port1_1 Mixer" }, |
| 1083 | { "P1_2_TX", NULL, "Port1_2 Mixer" }, |
| 1084 | { "P1_3_TX", NULL, "Port1_3 Mixer" }, |
| 1085 | { "P1_4_TX", NULL, "Port1_4 Mixer" }, |
| 1086 | { "P1_5_TX", NULL, "Port1_5 Mixer" }, |
| 1087 | { "P1_6_TX", NULL, "Port1_6 Mixer" }, |
| 1088 | { "P1_7_TX", NULL, "Port1_7 Mixer" }, |
| 1089 | { "P1_8_TX", NULL, "Port1_8 Mixer" }, |
| 1090 | |
| 1091 | { "P2_1_TX", NULL, "Port2_1 Mixer" }, |
| 1092 | { "P2_2_TX", NULL, "Port2_2 Mixer" }, |
| 1093 | |
| 1094 | { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"}, |
| 1095 | { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"}, |
| 1096 | { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"}, |
| 1097 | { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"}, |
| 1098 | { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"}, |
| 1099 | { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"}, |
| 1100 | { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"}, |
| 1101 | { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"}, |
| 1102 | |
| 1103 | { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"}, |
| 1104 | { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"}, |
| 1105 | |
| 1106 | { "Mic1 Input", NULL, "AMIC1" }, |
| 1107 | { "Mic2 Input", NULL, "AMIC2" }, |
| 1108 | |
| 1109 | { "AUXL Input", NULL, "AUXL" }, |
| 1110 | { "AUXR Input", NULL, "AUXR" }, |
| 1111 | |
| 1112 | /* AUX connections */ |
| 1113 | { "ADCL Mux", "Aux_L", "AUXL Input" }, |
| 1114 | { "ADCL Mux", "MIC1", "Mic1 Input" }, |
| 1115 | |
| 1116 | { "ADCR Mux", "Aux_R", "AUXR Input" }, |
| 1117 | { "ADCR Mux", "MIC2", "Mic2 Input" }, |
| 1118 | |
| 1119 | /* ADC connection */ |
| 1120 | { "ADC Left", NULL, "ADCL Mux"}, |
| 1121 | { "ADC Right", NULL, "ADCR Mux"}, |
| 1122 | |
| 1123 | { "DMIC1 Left", NULL, "DMIC1DAT"}, |
| 1124 | { "DMIC1 Right", NULL, "DMIC1DAT"}, |
| 1125 | { "DMIC2 Left", NULL, "DMIC2DAT"}, |
| 1126 | { "DMIC2 Right", NULL, "DMIC2DAT"}, |
| 1127 | |
| 1128 | /* Sidetone map */ |
| 1129 | { "Sidetone Mixer", NULL, "ADC Left" }, |
| 1130 | { "Sidetone Mixer", NULL, "ADC Right" }, |
| 1131 | { "Sidetone Mixer", NULL, "DMIC1 Left" }, |
| 1132 | { "Sidetone Mixer", NULL, "DMIC1 Right" }, |
| 1133 | { "Sidetone Mixer", NULL, "DMIC2 Left" }, |
| 1134 | { "Sidetone Mixer", NULL, "DMIC2 Right" }, |
| 1135 | |
| 1136 | { "Sidetone", "Sidetone Switch", "Sidetone Mixer" }, |
| 1137 | }; |
| 1138 | |
| 1139 | static int lm49453_hw_params(struct snd_pcm_substream *substream, |
| 1140 | struct snd_pcm_hw_params *params, |
| 1141 | struct snd_soc_dai *dai) |
| 1142 | { |
Mark Brown | e6968a1 | 2012-04-04 15:58:16 +0100 | [diff] [blame^] | 1143 | struct snd_soc_codec *codec = dai->codec; |
M R Swami Reddy | dbf7a73 | 2012-03-30 16:03:43 +0530 | [diff] [blame] | 1144 | struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec); |
| 1145 | u16 clk_div = 0; |
| 1146 | |
| 1147 | lm49453->fs_rate = params_rate(params); |
| 1148 | |
| 1149 | /* Setting DAC clock dividers based on substream sample rate. */ |
| 1150 | switch (lm49453->fs_rate) { |
| 1151 | case 8000: |
| 1152 | case 16000: |
| 1153 | case 32000: |
| 1154 | case 24000: |
| 1155 | case 48000: |
| 1156 | clk_div = 256; |
| 1157 | break; |
| 1158 | case 11025: |
| 1159 | case 22050: |
| 1160 | case 44100: |
| 1161 | clk_div = 216; |
| 1162 | break; |
| 1163 | case 96000: |
| 1164 | clk_div = 127; |
| 1165 | break; |
| 1166 | default: |
| 1167 | return -EINVAL; |
| 1168 | } |
| 1169 | |
| 1170 | snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div); |
| 1171 | snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div); |
| 1172 | |
| 1173 | return 0; |
| 1174 | } |
| 1175 | |
| 1176 | static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
| 1177 | { |
| 1178 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1179 | |
| 1180 | int aif_val = 0; |
| 1181 | int mode = 0; |
| 1182 | int clk_phase = 0; |
| 1183 | int clk_shift = 0; |
| 1184 | |
| 1185 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1186 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1187 | aif_val = ~LM49453_AUDIO_PORT1_BASIC_CLK_MS | |
| 1188 | ~LM49453_AUDIO_PORT1_BASIC_SYNC_MS; |
| 1189 | break; |
| 1190 | case SND_SOC_DAIFMT_CBS_CFM: |
| 1191 | aif_val = ~LM49453_AUDIO_PORT1_BASIC_CLK_MS | |
| 1192 | LM49453_AUDIO_PORT1_BASIC_SYNC_MS; |
| 1193 | break; |
| 1194 | case SND_SOC_DAIFMT_CBM_CFS: |
| 1195 | aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS | |
| 1196 | ~LM49453_AUDIO_PORT1_BASIC_SYNC_MS; |
| 1197 | break; |
| 1198 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1199 | aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS | |
| 1200 | LM49453_AUDIO_PORT1_BASIC_SYNC_MS; |
| 1201 | break; |
| 1202 | default: |
| 1203 | return -EINVAL; |
| 1204 | } |
| 1205 | |
| 1206 | |
| 1207 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1208 | case SND_SOC_DAIFMT_I2S: |
| 1209 | break; |
| 1210 | case SND_SOC_DAIFMT_DSP_A: |
| 1211 | mode = 1; |
| 1212 | clk_phase = (1 << 5); |
| 1213 | clk_shift = 1; |
| 1214 | break; |
| 1215 | case SND_SOC_DAIFMT_DSP_B: |
| 1216 | mode = 1; |
| 1217 | clk_phase = (1 << 5); |
| 1218 | clk_shift = 0; |
| 1219 | break; |
| 1220 | default: |
| 1221 | return -EINVAL; |
| 1222 | } |
| 1223 | |
| 1224 | snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG, |
| 1225 | LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(1)|BIT(5), |
| 1226 | (aif_val | mode | clk_phase)); |
| 1227 | |
| 1228 | snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift); |
| 1229 | |
| 1230 | return 0; |
| 1231 | } |
| 1232 | |
| 1233 | static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
| 1234 | unsigned int freq, int dir) |
| 1235 | { |
| 1236 | struct snd_soc_codec *codec = dai->codec; |
| 1237 | u16 pll_clk = 0; |
| 1238 | |
| 1239 | switch (freq) { |
| 1240 | case 12288000: |
| 1241 | case 26000000: |
| 1242 | case 19200000: |
| 1243 | /* pll clk slection */ |
| 1244 | pll_clk = 0; |
| 1245 | break; |
| 1246 | case 48000: |
| 1247 | case 32576: |
| 1248 | /* fll clk slection */ |
| 1249 | pll_clk = BIT(4); |
| 1250 | return 0; |
| 1251 | default: |
| 1252 | return -EINVAL; |
| 1253 | } |
| 1254 | |
| 1255 | snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk); |
| 1256 | |
| 1257 | return 0; |
| 1258 | } |
| 1259 | |
| 1260 | static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute) |
| 1261 | { |
| 1262 | snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0), |
| 1263 | (mute ? (BIT(1)|BIT(0)) : 0)); |
| 1264 | return 0; |
| 1265 | } |
| 1266 | |
| 1267 | static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute) |
| 1268 | { |
| 1269 | snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2), |
| 1270 | (mute ? (BIT(3)|BIT(2)) : 0)); |
| 1271 | return 0; |
| 1272 | } |
| 1273 | |
| 1274 | static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute) |
| 1275 | { |
| 1276 | snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4), |
| 1277 | (mute ? (BIT(5)|BIT(4)) : 0)); |
| 1278 | return 0; |
| 1279 | } |
| 1280 | |
| 1281 | static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute) |
| 1282 | { |
| 1283 | snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4), |
| 1284 | (mute ? BIT(4) : 0)); |
| 1285 | return 0; |
| 1286 | } |
| 1287 | |
| 1288 | static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute) |
| 1289 | { |
| 1290 | snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6), |
| 1291 | (mute ? (BIT(7)|BIT(6)) : 0)); |
| 1292 | return 0; |
| 1293 | } |
| 1294 | |
| 1295 | static int lm49453_set_bias_level(struct snd_soc_codec *codec, |
| 1296 | enum snd_soc_bias_level level) |
| 1297 | { |
| 1298 | struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec); |
| 1299 | |
| 1300 | switch (level) { |
| 1301 | case SND_SOC_BIAS_ON: |
| 1302 | case SND_SOC_BIAS_PREPARE: |
| 1303 | break; |
| 1304 | |
| 1305 | case SND_SOC_BIAS_STANDBY: |
| 1306 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
| 1307 | regcache_sync(lm49453->regmap); |
| 1308 | |
| 1309 | snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, |
| 1310 | LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN); |
| 1311 | break; |
| 1312 | |
| 1313 | case SND_SOC_BIAS_OFF: |
| 1314 | snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, |
| 1315 | LM49453_PMC_SETUP_CHIP_EN, 0); |
| 1316 | break; |
| 1317 | } |
| 1318 | |
| 1319 | codec->dapm.bias_level = level; |
| 1320 | |
| 1321 | return 0; |
| 1322 | } |
| 1323 | |
| 1324 | /* Formates supported by LM49453 driver. */ |
| 1325 | #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 1326 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 1327 | |
| 1328 | static struct snd_soc_dai_ops lm49453_headset_dai_ops = { |
| 1329 | .hw_params = lm49453_hw_params, |
| 1330 | .set_sysclk = lm49453_set_dai_sysclk, |
| 1331 | .set_fmt = lm49453_set_dai_fmt, |
| 1332 | .digital_mute = lm49453_hp_mute, |
| 1333 | }; |
| 1334 | |
| 1335 | static struct snd_soc_dai_ops lm49453_speaker_dai_ops = { |
| 1336 | .hw_params = lm49453_hw_params, |
| 1337 | .set_sysclk = lm49453_set_dai_sysclk, |
| 1338 | .set_fmt = lm49453_set_dai_fmt, |
| 1339 | .digital_mute = lm49453_ls_mute, |
| 1340 | }; |
| 1341 | |
| 1342 | static struct snd_soc_dai_ops lm49453_haptic_dai_ops = { |
| 1343 | .hw_params = lm49453_hw_params, |
| 1344 | .set_sysclk = lm49453_set_dai_sysclk, |
| 1345 | .set_fmt = lm49453_set_dai_fmt, |
| 1346 | .digital_mute = lm49453_ha_mute, |
| 1347 | }; |
| 1348 | |
| 1349 | static struct snd_soc_dai_ops lm49453_ep_dai_ops = { |
| 1350 | .hw_params = lm49453_hw_params, |
| 1351 | .set_sysclk = lm49453_set_dai_sysclk, |
| 1352 | .set_fmt = lm49453_set_dai_fmt, |
| 1353 | .digital_mute = lm49453_ep_mute, |
| 1354 | }; |
| 1355 | |
| 1356 | static struct snd_soc_dai_ops lm49453_lineout_dai_ops = { |
| 1357 | .hw_params = lm49453_hw_params, |
| 1358 | .set_sysclk = lm49453_set_dai_sysclk, |
| 1359 | .set_fmt = lm49453_set_dai_fmt, |
| 1360 | .digital_mute = lm49453_lo_mute, |
| 1361 | }; |
| 1362 | |
| 1363 | /* LM49453 dai structure. */ |
| 1364 | struct snd_soc_dai_driver lm49453_dai[] = { |
| 1365 | { |
| 1366 | .name = "LM49453 Headset", |
| 1367 | .playback = { |
| 1368 | .stream_name = "Headset", |
| 1369 | .channels_min = 2, |
| 1370 | .channels_max = 2, |
| 1371 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1372 | .formats = LM49453_FORMATS, |
| 1373 | }, |
| 1374 | .capture = { |
| 1375 | .stream_name = "Capture", |
| 1376 | .channels_min = 1, |
| 1377 | .channels_max = 5, |
| 1378 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1379 | .formats = LM49453_FORMATS, |
| 1380 | }, |
| 1381 | .ops = &lm49453_headset_dai_ops, |
| 1382 | .symmetric_rates = 1, |
| 1383 | }, |
| 1384 | { |
| 1385 | .name = "LM49453 Speaker", |
| 1386 | .playback = { |
| 1387 | .stream_name = "Speaker", |
| 1388 | .channels_min = 2, |
| 1389 | .channels_max = 2, |
| 1390 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1391 | .formats = LM49453_FORMATS, |
| 1392 | }, |
| 1393 | .ops = &lm49453_speaker_dai_ops, |
| 1394 | }, |
| 1395 | { |
| 1396 | .name = "LM49453 Haptic", |
| 1397 | .playback = { |
| 1398 | .stream_name = "Haptic", |
| 1399 | .channels_min = 2, |
| 1400 | .channels_max = 2, |
| 1401 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1402 | .formats = LM49453_FORMATS, |
| 1403 | }, |
| 1404 | .ops = &lm49453_haptic_dai_ops, |
| 1405 | }, |
| 1406 | { |
| 1407 | .name = "LM49453 Earpiece", |
| 1408 | .playback = { |
| 1409 | .stream_name = "Earpiece", |
| 1410 | .channels_min = 1, |
| 1411 | .channels_max = 1, |
| 1412 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1413 | .formats = LM49453_FORMATS, |
| 1414 | }, |
| 1415 | .ops = &lm49453_ep_dai_ops, |
| 1416 | }, |
| 1417 | { |
| 1418 | .name = "LM49453 line out", |
| 1419 | .playback = { |
| 1420 | .stream_name = "Lineout", |
| 1421 | .channels_min = 2, |
| 1422 | .channels_max = 2, |
| 1423 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 1424 | .formats = LM49453_FORMATS, |
| 1425 | }, |
| 1426 | .ops = &lm49453_lineout_dai_ops, |
| 1427 | }, |
| 1428 | }; |
| 1429 | |
| 1430 | static int lm49453_suspend(struct snd_soc_codec *codec) |
| 1431 | { |
| 1432 | lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1433 | return 0; |
| 1434 | } |
| 1435 | |
| 1436 | static int lm49453_resume(struct snd_soc_codec *codec) |
| 1437 | { |
| 1438 | lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1439 | return 0; |
| 1440 | } |
| 1441 | |
| 1442 | static int lm49453_probe(struct snd_soc_codec *codec) |
| 1443 | { |
| 1444 | struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec); |
| 1445 | int ret = 0; |
| 1446 | |
| 1447 | codec->control_data = lm49453->regmap; |
| 1448 | |
| 1449 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); |
| 1450 | if (ret < 0) { |
| 1451 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 1452 | return ret; |
| 1453 | } |
| 1454 | |
| 1455 | return 0; |
| 1456 | } |
| 1457 | |
| 1458 | /* power down chip */ |
| 1459 | static int lm49453_remove(struct snd_soc_codec *codec) |
| 1460 | { |
| 1461 | lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
| 1465 | static struct snd_soc_codec_driver soc_codec_dev_lm49453 = { |
| 1466 | .probe = lm49453_probe, |
| 1467 | .remove = lm49453_remove, |
| 1468 | .suspend = lm49453_suspend, |
| 1469 | .resume = lm49453_resume, |
| 1470 | .set_bias_level = lm49453_set_bias_level, |
| 1471 | .controls = lm49453_snd_controls, |
| 1472 | .num_controls = ARRAY_SIZE(lm49453_snd_controls), |
| 1473 | .dapm_widgets = lm49453_dapm_widgets, |
| 1474 | .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets), |
| 1475 | .dapm_routes = lm49453_audio_map, |
| 1476 | .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map), |
| 1477 | .idle_bias_off = true, |
| 1478 | }; |
| 1479 | |
| 1480 | static const struct regmap_config lm49453_regmap_config = { |
| 1481 | .reg_bits = 8, |
| 1482 | .val_bits = 8, |
| 1483 | |
| 1484 | .max_register = LM49453_MAX_REGISTER, |
| 1485 | .reg_defaults = lm49453_reg_defs, |
| 1486 | .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs), |
| 1487 | .cache_type = REGCACHE_RBTREE, |
| 1488 | }; |
| 1489 | |
| 1490 | static __devinit int lm49453_i2c_probe(struct i2c_client *i2c, |
| 1491 | const struct i2c_device_id *id) |
| 1492 | { |
| 1493 | struct lm49453_priv *lm49453; |
| 1494 | int ret = 0; |
| 1495 | |
| 1496 | lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv), |
| 1497 | GFP_KERNEL); |
| 1498 | |
| 1499 | if (lm49453 == NULL) |
| 1500 | return -ENOMEM; |
| 1501 | |
| 1502 | i2c_set_clientdata(i2c, lm49453); |
| 1503 | |
| 1504 | lm49453->regmap = regmap_init_i2c(i2c, &lm49453_regmap_config); |
| 1505 | if (IS_ERR(lm49453->regmap)) { |
| 1506 | ret = PTR_ERR(lm49453->regmap); |
| 1507 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 1508 | ret); |
| 1509 | return ret; |
| 1510 | } |
| 1511 | |
| 1512 | ret = snd_soc_register_codec(&i2c->dev, |
| 1513 | &soc_codec_dev_lm49453, |
| 1514 | lm49453_dai, ARRAY_SIZE(lm49453_dai)); |
| 1515 | if (ret < 0) { |
| 1516 | dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); |
| 1517 | regmap_exit(lm49453->regmap); |
| 1518 | return ret; |
| 1519 | } |
| 1520 | |
| 1521 | return ret; |
| 1522 | } |
| 1523 | |
| 1524 | static int __devexit lm49453_i2c_remove(struct i2c_client *client) |
| 1525 | { |
| 1526 | struct lm49453_priv *lm49453 = i2c_get_clientdata(client); |
| 1527 | |
| 1528 | snd_soc_unregister_codec(&client->dev); |
| 1529 | regmap_exit(lm49453->regmap); |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | static const struct i2c_device_id lm49453_i2c_id[] = { |
| 1534 | { "lm49453", 0 }, |
| 1535 | { } |
| 1536 | }; |
| 1537 | MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id); |
| 1538 | |
| 1539 | static struct i2c_driver lm49453_i2c_driver = { |
| 1540 | .driver = { |
| 1541 | .name = "lm49453", |
| 1542 | .owner = THIS_MODULE, |
| 1543 | }, |
| 1544 | .probe = lm49453_i2c_probe, |
| 1545 | .remove = __devexit_p(lm49453_i2c_remove), |
| 1546 | .id_table = lm49453_i2c_id, |
| 1547 | }; |
| 1548 | |
| 1549 | module_i2c_driver(lm49453_i2c_driver); |
| 1550 | |
| 1551 | MODULE_DESCRIPTION("ASoC LM49453 driver"); |
| 1552 | MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com"); |
| 1553 | MODULE_LICENSE("GPL v2"); |