| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * |
| 3 | * philips saa7134 registers |
| 4 | */ |
| 5 | |
| 6 | /* ------------------------------------------------------------------ */ |
| 7 | /* |
| 8 | * PCI ID's |
| 9 | */ |
| 10 | #ifndef PCI_DEVICE_ID_PHILIPS_SAA7130 |
| 11 | # define PCI_DEVICE_ID_PHILIPS_SAA7130 0x7130 |
| 12 | #endif |
| 13 | #ifndef PCI_DEVICE_ID_PHILIPS_SAA7133 |
| 14 | # define PCI_DEVICE_ID_PHILIPS_SAA7133 0x7133 |
| 15 | #endif |
| 16 | #ifndef PCI_DEVICE_ID_PHILIPS_SAA7134 |
| 17 | # define PCI_DEVICE_ID_PHILIPS_SAA7134 0x7134 |
| 18 | #endif |
| 19 | #ifndef PCI_DEVICE_ID_PHILIPS_SAA7135 |
| 20 | # define PCI_DEVICE_ID_PHILIPS_SAA7135 0x7135 |
| 21 | #endif |
| 22 | |
| 23 | /* ------------------------------------------------------------------ */ |
| 24 | /* |
| 25 | * registers -- 32 bit |
| 26 | */ |
| 27 | |
| 28 | /* DMA channels, n = 0 ... 6 */ |
| 29 | #define SAA7134_RS_BA1(n) ((0x200 >> 2) + 4*n) |
| Mauro Carvalho Chehab | 4ac9791 | 2005-11-08 21:37:43 -0800 | [diff] [blame] | 30 | #define SAA7134_RS_BA2(n) ((0x204 >> 2) + 4*n) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #define SAA7134_RS_PITCH(n) ((0x208 >> 2) + 4*n) |
| 32 | #define SAA7134_RS_CONTROL(n) ((0x20c >> 2) + 4*n) |
| 33 | #define SAA7134_RS_CONTROL_WSWAP (0x01 << 25) |
| 34 | #define SAA7134_RS_CONTROL_BSWAP (0x01 << 24) |
| 35 | #define SAA7134_RS_CONTROL_BURST_2 (0x01 << 21) |
| 36 | #define SAA7134_RS_CONTROL_BURST_4 (0x02 << 21) |
| 37 | #define SAA7134_RS_CONTROL_BURST_8 (0x03 << 21) |
| 38 | #define SAA7134_RS_CONTROL_BURST_16 (0x04 << 21) |
| 39 | #define SAA7134_RS_CONTROL_BURST_32 (0x05 << 21) |
| 40 | #define SAA7134_RS_CONTROL_BURST_64 (0x06 << 21) |
| 41 | #define SAA7134_RS_CONTROL_BURST_MAX (0x07 << 21) |
| 42 | #define SAA7134_RS_CONTROL_ME (0x01 << 20) |
| 43 | #define SAA7134_FIFO_SIZE (0x2a0 >> 2) |
| 44 | #define SAA7134_THRESHOULD (0x2a4 >> 2) |
| 45 | |
| Ricardo Cerqueira | bd15eba | 2005-11-08 21:37:11 -0800 | [diff] [blame] | 46 | #define SAA7133_NUM_SAMPLES (0x588 >> 2) |
| 47 | #define SAA7133_AUDIO_CHANNEL (0x58c >> 2) |
| 48 | #define SAA7133_AUDIO_FORMAT (0x58f >> 2) |
| 49 | #define SAA7133_DIGITAL_OUTPUT_SEL1 (0x46c >> 2) |
| 50 | #define SAA7133_DIGITAL_OUTPUT_SEL2 (0x470 >> 2) |
| 51 | #define SAA7133_DIGITAL_INPUT_XBAR1 (0x464 >> 2) |
| 52 | #define SAA7133_ANALOG_IO_SELECT (0x594 >> 2) |
| 53 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | /* main control */ |
| 55 | #define SAA7134_MAIN_CTRL (0x2a8 >> 2) |
| Mauro Carvalho Chehab | 4ac9791 | 2005-11-08 21:37:43 -0800 | [diff] [blame] | 56 | #define SAA7134_MAIN_CTRL_VPLLE (1 << 15) |
| 57 | #define SAA7134_MAIN_CTRL_APLLE (1 << 14) |
| 58 | #define SAA7134_MAIN_CTRL_EXOSC (1 << 13) |
| 59 | #define SAA7134_MAIN_CTRL_EVFE1 (1 << 12) |
| 60 | #define SAA7134_MAIN_CTRL_EVFE2 (1 << 11) |
| 61 | #define SAA7134_MAIN_CTRL_ESFE (1 << 10) |
| 62 | #define SAA7134_MAIN_CTRL_EBADC (1 << 9) |
| 63 | #define SAA7134_MAIN_CTRL_EBDAC (1 << 8) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | #define SAA7134_MAIN_CTRL_TE6 (1 << 6) |
| 65 | #define SAA7134_MAIN_CTRL_TE5 (1 << 5) |
| 66 | #define SAA7134_MAIN_CTRL_TE4 (1 << 4) |
| 67 | #define SAA7134_MAIN_CTRL_TE3 (1 << 3) |
| 68 | #define SAA7134_MAIN_CTRL_TE2 (1 << 2) |
| 69 | #define SAA7134_MAIN_CTRL_TE1 (1 << 1) |
| 70 | #define SAA7134_MAIN_CTRL_TE0 (1 << 0) |
| 71 | |
| 72 | /* DMA status */ |
| 73 | #define SAA7134_DMA_STATUS (0x2ac >> 2) |
| 74 | |
| 75 | /* audio / video status */ |
| 76 | #define SAA7134_AV_STATUS (0x2c0 >> 2) |
| 77 | #define SAA7134_AV_STATUS_STEREO (1 << 17) |
| 78 | #define SAA7134_AV_STATUS_DUAL (1 << 16) |
| 79 | #define SAA7134_AV_STATUS_PILOT (1 << 15) |
| 80 | #define SAA7134_AV_STATUS_SMB (1 << 14) |
| 81 | #define SAA7134_AV_STATUS_DMB (1 << 13) |
| 82 | #define SAA7134_AV_STATUS_VDSP (1 << 12) |
| 83 | #define SAA7134_AV_STATUS_IIC_STATUS (3 << 10) |
| 84 | #define SAA7134_AV_STATUS_MVM (7 << 7) |
| 85 | #define SAA7134_AV_STATUS_FIDT (1 << 6) |
| 86 | #define SAA7134_AV_STATUS_INTL (1 << 5) |
| 87 | #define SAA7134_AV_STATUS_RDCAP (1 << 4) |
| 88 | #define SAA7134_AV_STATUS_PWR_ON (1 << 3) |
| 89 | #define SAA7134_AV_STATUS_LOAD_ERR (1 << 2) |
| 90 | #define SAA7134_AV_STATUS_TRIG_ERR (1 << 1) |
| 91 | #define SAA7134_AV_STATUS_CONF_ERR (1 << 0) |
| 92 | |
| 93 | /* interrupt */ |
| 94 | #define SAA7134_IRQ1 (0x2c4 >> 2) |
| 95 | #define SAA7134_IRQ1_INTE_RA3_1 (1 << 25) |
| 96 | #define SAA7134_IRQ1_INTE_RA3_0 (1 << 24) |
| 97 | #define SAA7134_IRQ1_INTE_RA2_3 (1 << 19) |
| 98 | #define SAA7134_IRQ1_INTE_RA2_2 (1 << 18) |
| 99 | #define SAA7134_IRQ1_INTE_RA2_1 (1 << 17) |
| 100 | #define SAA7134_IRQ1_INTE_RA2_0 (1 << 16) |
| 101 | #define SAA7134_IRQ1_INTE_RA1_3 (1 << 11) |
| 102 | #define SAA7134_IRQ1_INTE_RA1_2 (1 << 10) |
| 103 | #define SAA7134_IRQ1_INTE_RA1_1 (1 << 9) |
| 104 | #define SAA7134_IRQ1_INTE_RA1_0 (1 << 8) |
| 105 | #define SAA7134_IRQ1_INTE_RA0_7 (1 << 7) |
| 106 | #define SAA7134_IRQ1_INTE_RA0_6 (1 << 6) |
| 107 | #define SAA7134_IRQ1_INTE_RA0_5 (1 << 5) |
| 108 | #define SAA7134_IRQ1_INTE_RA0_4 (1 << 4) |
| 109 | #define SAA7134_IRQ1_INTE_RA0_3 (1 << 3) |
| 110 | #define SAA7134_IRQ1_INTE_RA0_2 (1 << 2) |
| 111 | #define SAA7134_IRQ1_INTE_RA0_1 (1 << 1) |
| 112 | #define SAA7134_IRQ1_INTE_RA0_0 (1 << 0) |
| 113 | |
| 114 | #define SAA7134_IRQ2 (0x2c8 >> 2) |
| Mauro Carvalho Chehab | 3629e1d | 2010-04-03 01:43:36 -0300 | [diff] [blame] | 115 | #define SAA7134_IRQ2_INTE_GPIO23_N (1 << 17) /* negative edge */ |
| 116 | #define SAA7134_IRQ2_INTE_GPIO23_P (1 << 16) /* positive edge */ |
| 117 | #define SAA7134_IRQ2_INTE_GPIO22_N (1 << 15) /* negative edge */ |
| 118 | #define SAA7134_IRQ2_INTE_GPIO22_P (1 << 14) /* positive edge */ |
| 119 | #define SAA7134_IRQ2_INTE_GPIO18_N (1 << 13) /* negative edge */ |
| 120 | #define SAA7134_IRQ2_INTE_GPIO18_P (1 << 12) /* positive edge */ |
| 121 | #define SAA7134_IRQ2_INTE_GPIO16_N (1 << 11) /* negative edge */ |
| 122 | #define SAA7134_IRQ2_INTE_GPIO16_P (1 << 10) /* positive edge */ |
| 123 | #define SAA7134_IRQ2_INTE_SC2 (1 << 9) |
| 124 | #define SAA7134_IRQ2_INTE_SC1 (1 << 8) |
| 125 | #define SAA7134_IRQ2_INTE_SC0 (1 << 7) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | #define SAA7134_IRQ2_INTE_DEC4 (1 << 6) |
| 127 | #define SAA7134_IRQ2_INTE_DEC3 (1 << 5) |
| 128 | #define SAA7134_IRQ2_INTE_DEC2 (1 << 4) |
| 129 | #define SAA7134_IRQ2_INTE_DEC1 (1 << 3) |
| 130 | #define SAA7134_IRQ2_INTE_DEC0 (1 << 2) |
| 131 | #define SAA7134_IRQ2_INTE_PE (1 << 1) |
| 132 | #define SAA7134_IRQ2_INTE_AR (1 << 0) |
| 133 | |
| 134 | #define SAA7134_IRQ_REPORT (0x2cc >> 2) |
| 135 | #define SAA7134_IRQ_REPORT_GPIO23 (1 << 17) |
| 136 | #define SAA7134_IRQ_REPORT_GPIO22 (1 << 16) |
| 137 | #define SAA7134_IRQ_REPORT_GPIO18 (1 << 15) |
| Mauro Carvalho Chehab | 3629e1d | 2010-04-03 01:43:36 -0300 | [diff] [blame] | 138 | #define SAA7134_IRQ_REPORT_GPIO16 (1 << 14) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | #define SAA7134_IRQ_REPORT_LOAD_ERR (1 << 13) |
| 140 | #define SAA7134_IRQ_REPORT_CONF_ERR (1 << 12) |
| 141 | #define SAA7134_IRQ_REPORT_TRIG_ERR (1 << 11) |
| 142 | #define SAA7134_IRQ_REPORT_MMC (1 << 10) |
| 143 | #define SAA7134_IRQ_REPORT_FIDT (1 << 9) |
| 144 | #define SAA7134_IRQ_REPORT_INTL (1 << 8) |
| 145 | #define SAA7134_IRQ_REPORT_RDCAP (1 << 7) |
| 146 | #define SAA7134_IRQ_REPORT_PWR_ON (1 << 6) |
| 147 | #define SAA7134_IRQ_REPORT_PE (1 << 5) |
| 148 | #define SAA7134_IRQ_REPORT_AR (1 << 4) |
| 149 | #define SAA7134_IRQ_REPORT_DONE_RA3 (1 << 3) |
| 150 | #define SAA7134_IRQ_REPORT_DONE_RA2 (1 << 2) |
| 151 | #define SAA7134_IRQ_REPORT_DONE_RA1 (1 << 1) |
| 152 | #define SAA7134_IRQ_REPORT_DONE_RA0 (1 << 0) |
| 153 | #define SAA7134_IRQ_STATUS (0x2d0 >> 2) |
| 154 | |
| 155 | |
| 156 | /* ------------------------------------------------------------------ */ |
| 157 | /* |
| 158 | * registers -- 8 bit |
| 159 | */ |
| 160 | |
| 161 | /* video decoder */ |
| 162 | #define SAA7134_INCR_DELAY 0x101 |
| 163 | #define SAA7134_ANALOG_IN_CTRL1 0x102 |
| 164 | #define SAA7134_ANALOG_IN_CTRL2 0x103 |
| 165 | #define SAA7134_ANALOG_IN_CTRL3 0x104 |
| 166 | #define SAA7134_ANALOG_IN_CTRL4 0x105 |
| 167 | #define SAA7134_HSYNC_START 0x106 |
| 168 | #define SAA7134_HSYNC_STOP 0x107 |
| 169 | #define SAA7134_SYNC_CTRL 0x108 |
| Mikhail Domrachev | 707b7f8 | 2014-04-01 09:28:17 -0300 | [diff] [blame] | 170 | #define SAA7134_SYNC_CTRL_AUFD (1 << 7) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | #define SAA7134_LUMA_CTRL 0x109 |
| Mikhail Domrachev | 707b7f8 | 2014-04-01 09:28:17 -0300 | [diff] [blame] | 172 | #define SAA7134_LUMA_CTRL_LDEL (1 << 5) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | #define SAA7134_DEC_LUMA_BRIGHT 0x10a |
| 174 | #define SAA7134_DEC_LUMA_CONTRAST 0x10b |
| 175 | #define SAA7134_DEC_CHROMA_SATURATION 0x10c |
| 176 | #define SAA7134_DEC_CHROMA_HUE 0x10d |
| 177 | #define SAA7134_CHROMA_CTRL1 0x10e |
| Mikhail Domrachev | 707b7f8 | 2014-04-01 09:28:17 -0300 | [diff] [blame] | 178 | #define SAA7134_CHROMA_CTRL1_AUTO0 (1 << 1) |
| 179 | #define SAA7134_CHROMA_CTRL1_FCTC (1 << 2) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | #define SAA7134_CHROMA_GAIN 0x10f |
| 181 | #define SAA7134_CHROMA_CTRL2 0x110 |
| 182 | #define SAA7134_MODE_DELAY_CTRL 0x111 |
| 183 | |
| 184 | #define SAA7134_ANALOG_ADC 0x114 |
| Mikhail Domrachev | 707b7f8 | 2014-04-01 09:28:17 -0300 | [diff] [blame] | 185 | #define SAA7134_ANALOG_ADC_AUTO1 (1 << 2) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | #define SAA7134_VGATE_START 0x115 |
| 187 | #define SAA7134_VGATE_STOP 0x116 |
| 188 | #define SAA7134_MISC_VGATE_MSB 0x117 |
| 189 | #define SAA7134_RAW_DATA_GAIN 0x118 |
| 190 | #define SAA7134_RAW_DATA_OFFSET 0x119 |
| 191 | #define SAA7134_STATUS_VIDEO1 0x11e |
| 192 | #define SAA7134_STATUS_VIDEO2 0x11f |
| 193 | |
| 194 | /* video scaler */ |
| 195 | #define SAA7134_SOURCE_TIMING1 0x000 |
| 196 | #define SAA7134_SOURCE_TIMING2 0x001 |
| 197 | #define SAA7134_REGION_ENABLE 0x004 |
| 198 | #define SAA7134_SCALER_STATUS0 0x006 |
| 199 | #define SAA7134_SCALER_STATUS1 0x007 |
| 200 | #define SAA7134_START_GREEN 0x00c |
| 201 | #define SAA7134_START_BLUE 0x00d |
| 202 | #define SAA7134_START_RED 0x00e |
| 203 | #define SAA7134_GREEN_PATH(x) (0x010 +x) |
| 204 | #define SAA7134_BLUE_PATH(x) (0x020 +x) |
| 205 | #define SAA7134_RED_PATH(x) (0x030 +x) |
| 206 | |
| 207 | #define TASK_A 0x040 |
| 208 | #define TASK_B 0x080 |
| 209 | #define SAA7134_TASK_CONDITIONS(t) (0x000 +t) |
| 210 | #define SAA7134_FIELD_HANDLING(t) (0x001 +t) |
| 211 | #define SAA7134_DATA_PATH(t) (0x002 +t) |
| 212 | #define SAA7134_VBI_H_START1(t) (0x004 +t) |
| 213 | #define SAA7134_VBI_H_START2(t) (0x005 +t) |
| 214 | #define SAA7134_VBI_H_STOP1(t) (0x006 +t) |
| 215 | #define SAA7134_VBI_H_STOP2(t) (0x007 +t) |
| 216 | #define SAA7134_VBI_V_START1(t) (0x008 +t) |
| 217 | #define SAA7134_VBI_V_START2(t) (0x009 +t) |
| 218 | #define SAA7134_VBI_V_STOP1(t) (0x00a +t) |
| 219 | #define SAA7134_VBI_V_STOP2(t) (0x00b +t) |
| 220 | #define SAA7134_VBI_H_LEN1(t) (0x00c +t) |
| 221 | #define SAA7134_VBI_H_LEN2(t) (0x00d +t) |
| 222 | #define SAA7134_VBI_V_LEN1(t) (0x00e +t) |
| 223 | #define SAA7134_VBI_V_LEN2(t) (0x00f +t) |
| 224 | |
| 225 | #define SAA7134_VIDEO_H_START1(t) (0x014 +t) |
| 226 | #define SAA7134_VIDEO_H_START2(t) (0x015 +t) |
| 227 | #define SAA7134_VIDEO_H_STOP1(t) (0x016 +t) |
| 228 | #define SAA7134_VIDEO_H_STOP2(t) (0x017 +t) |
| 229 | #define SAA7134_VIDEO_V_START1(t) (0x018 +t) |
| 230 | #define SAA7134_VIDEO_V_START2(t) (0x019 +t) |
| 231 | #define SAA7134_VIDEO_V_STOP1(t) (0x01a +t) |
| 232 | #define SAA7134_VIDEO_V_STOP2(t) (0x01b +t) |
| 233 | #define SAA7134_VIDEO_PIXELS1(t) (0x01c +t) |
| 234 | #define SAA7134_VIDEO_PIXELS2(t) (0x01d +t) |
| 235 | #define SAA7134_VIDEO_LINES1(t) (0x01e +t) |
| 236 | #define SAA7134_VIDEO_LINES2(t) (0x01f +t) |
| 237 | |
| 238 | #define SAA7134_H_PRESCALE(t) (0x020 +t) |
| 239 | #define SAA7134_ACC_LENGTH(t) (0x021 +t) |
| 240 | #define SAA7134_LEVEL_CTRL(t) (0x022 +t) |
| 241 | #define SAA7134_FIR_PREFILTER_CTRL(t) (0x023 +t) |
| 242 | #define SAA7134_LUMA_BRIGHT(t) (0x024 +t) |
| 243 | #define SAA7134_LUMA_CONTRAST(t) (0x025 +t) |
| 244 | #define SAA7134_CHROMA_SATURATION(t) (0x026 +t) |
| 245 | #define SAA7134_VBI_H_SCALE_INC1(t) (0x028 +t) |
| 246 | #define SAA7134_VBI_H_SCALE_INC2(t) (0x029 +t) |
| 247 | #define SAA7134_VBI_PHASE_OFFSET_LUMA(t) (0x02a +t) |
| 248 | #define SAA7134_VBI_PHASE_OFFSET_CHROMA(t) (0x02b +t) |
| 249 | #define SAA7134_H_SCALE_INC1(t) (0x02c +t) |
| 250 | #define SAA7134_H_SCALE_INC2(t) (0x02d +t) |
| 251 | #define SAA7134_H_PHASE_OFF_LUMA(t) (0x02e +t) |
| 252 | #define SAA7134_H_PHASE_OFF_CHROMA(t) (0x02f +t) |
| 253 | #define SAA7134_V_SCALE_RATIO1(t) (0x030 +t) |
| 254 | #define SAA7134_V_SCALE_RATIO2(t) (0x031 +t) |
| 255 | #define SAA7134_V_FILTER(t) (0x032 +t) |
| 256 | #define SAA7134_V_PHASE_OFFSET0(t) (0x034 +t) |
| 257 | #define SAA7134_V_PHASE_OFFSET1(t) (0x035 +t) |
| 258 | #define SAA7134_V_PHASE_OFFSET2(t) (0x036 +t) |
| 259 | #define SAA7134_V_PHASE_OFFSET3(t) (0x037 +t) |
| 260 | |
| 261 | /* clipping & dma */ |
| 262 | #define SAA7134_OFMT_VIDEO_A 0x300 |
| 263 | #define SAA7134_OFMT_DATA_A 0x301 |
| 264 | #define SAA7134_OFMT_VIDEO_B 0x302 |
| 265 | #define SAA7134_OFMT_DATA_B 0x303 |
| 266 | #define SAA7134_ALPHA_NOCLIP 0x304 |
| 267 | #define SAA7134_ALPHA_CLIP 0x305 |
| 268 | #define SAA7134_UV_PIXEL 0x308 |
| 269 | #define SAA7134_CLIP_RED 0x309 |
| 270 | #define SAA7134_CLIP_GREEN 0x30a |
| 271 | #define SAA7134_CLIP_BLUE 0x30b |
| 272 | |
| 273 | /* i2c bus */ |
| 274 | #define SAA7134_I2C_ATTR_STATUS 0x180 |
| 275 | #define SAA7134_I2C_DATA 0x181 |
| 276 | #define SAA7134_I2C_CLOCK_SELECT 0x182 |
| 277 | #define SAA7134_I2C_TIMER 0x183 |
| 278 | |
| 279 | /* audio */ |
| 280 | #define SAA7134_NICAM_ADD_DATA1 0x140 |
| 281 | #define SAA7134_NICAM_ADD_DATA2 0x141 |
| 282 | #define SAA7134_NICAM_STATUS 0x142 |
| 283 | #define SAA7134_AUDIO_STATUS 0x143 |
| 284 | #define SAA7134_NICAM_ERROR_COUNT 0x144 |
| 285 | #define SAA7134_IDENT_SIF 0x145 |
| 286 | #define SAA7134_LEVEL_READOUT1 0x146 |
| 287 | #define SAA7134_LEVEL_READOUT2 0x147 |
| 288 | #define SAA7134_NICAM_ERROR_LOW 0x148 |
| 289 | #define SAA7134_NICAM_ERROR_HIGH 0x149 |
| 290 | #define SAA7134_DCXO_IDENT_CTRL 0x14a |
| 291 | #define SAA7134_DEMODULATOR 0x14b |
| 292 | #define SAA7134_AGC_GAIN_SELECT 0x14c |
| 293 | #define SAA7134_CARRIER1_FREQ0 0x150 |
| 294 | #define SAA7134_CARRIER1_FREQ1 0x151 |
| 295 | #define SAA7134_CARRIER1_FREQ2 0x152 |
| 296 | #define SAA7134_CARRIER2_FREQ0 0x154 |
| 297 | #define SAA7134_CARRIER2_FREQ1 0x155 |
| 298 | #define SAA7134_CARRIER2_FREQ2 0x156 |
| 299 | #define SAA7134_NUM_SAMPLES0 0x158 |
| 300 | #define SAA7134_NUM_SAMPLES1 0x159 |
| 301 | #define SAA7134_NUM_SAMPLES2 0x15a |
| 302 | #define SAA7134_AUDIO_FORMAT_CTRL 0x15b |
| 303 | #define SAA7134_MONITOR_SELECT 0x160 |
| 304 | #define SAA7134_FM_DEEMPHASIS 0x161 |
| 305 | #define SAA7134_FM_DEMATRIX 0x162 |
| 306 | #define SAA7134_CHANNEL1_LEVEL 0x163 |
| 307 | #define SAA7134_CHANNEL2_LEVEL 0x164 |
| 308 | #define SAA7134_NICAM_CONFIG 0x165 |
| 309 | #define SAA7134_NICAM_LEVEL_ADJUST 0x166 |
| 310 | #define SAA7134_STEREO_DAC_OUTPUT_SELECT 0x167 |
| 311 | #define SAA7134_I2S_OUTPUT_FORMAT 0x168 |
| 312 | #define SAA7134_I2S_OUTPUT_SELECT 0x169 |
| 313 | #define SAA7134_I2S_OUTPUT_LEVEL 0x16a |
| 314 | #define SAA7134_DSP_OUTPUT_SELECT 0x16b |
| 315 | #define SAA7134_AUDIO_MUTE_CTRL 0x16c |
| 316 | #define SAA7134_SIF_SAMPLE_FREQ 0x16d |
| 317 | #define SAA7134_ANALOG_IO_SELECT 0x16e |
| 318 | #define SAA7134_AUDIO_CLOCK0 0x170 |
| 319 | #define SAA7134_AUDIO_CLOCK1 0x171 |
| 320 | #define SAA7134_AUDIO_CLOCK2 0x172 |
| 321 | #define SAA7134_AUDIO_PLL_CTRL 0x173 |
| 322 | #define SAA7134_AUDIO_CLOCKS_PER_FIELD0 0x174 |
| 323 | #define SAA7134_AUDIO_CLOCKS_PER_FIELD1 0x175 |
| 324 | #define SAA7134_AUDIO_CLOCKS_PER_FIELD2 0x176 |
| 325 | |
| 326 | /* video port output */ |
| 327 | #define SAA7134_VIDEO_PORT_CTRL0 0x190 |
| 328 | #define SAA7134_VIDEO_PORT_CTRL1 0x191 |
| 329 | #define SAA7134_VIDEO_PORT_CTRL2 0x192 |
| 330 | #define SAA7134_VIDEO_PORT_CTRL3 0x193 |
| 331 | #define SAA7134_VIDEO_PORT_CTRL4 0x194 |
| 332 | #define SAA7134_VIDEO_PORT_CTRL5 0x195 |
| 333 | #define SAA7134_VIDEO_PORT_CTRL6 0x196 |
| 334 | #define SAA7134_VIDEO_PORT_CTRL7 0x197 |
| 335 | #define SAA7134_VIDEO_PORT_CTRL8 0x198 |
| 336 | |
| 337 | /* transport stream interface */ |
| 338 | #define SAA7134_TS_PARALLEL 0x1a0 |
| 339 | #define SAA7134_TS_PARALLEL_SERIAL 0x1a1 |
| 340 | #define SAA7134_TS_SERIAL0 0x1a2 |
| 341 | #define SAA7134_TS_SERIAL1 0x1a3 |
| 342 | #define SAA7134_TS_DMA0 0x1a4 |
| 343 | #define SAA7134_TS_DMA1 0x1a5 |
| 344 | #define SAA7134_TS_DMA2 0x1a6 |
| 345 | |
| 346 | /* GPIO Controls */ |
| 347 | #define SAA7134_GPIO_GPRESCAN 0x80 |
| 348 | #define SAA7134_GPIO_27_25 0x0E |
| 349 | |
| 350 | #define SAA7134_GPIO_GPMODE0 0x1B0 |
| 351 | #define SAA7134_GPIO_GPMODE1 0x1B1 |
| 352 | #define SAA7134_GPIO_GPMODE2 0x1B2 |
| 353 | #define SAA7134_GPIO_GPMODE3 0x1B3 |
| 354 | #define SAA7134_GPIO_GPSTATUS0 0x1B4 |
| 355 | #define SAA7134_GPIO_GPSTATUS1 0x1B5 |
| 356 | #define SAA7134_GPIO_GPSTATUS2 0x1B6 |
| 357 | #define SAA7134_GPIO_GPSTATUS3 0x1B7 |
| 358 | |
| 359 | /* I2S output */ |
| 360 | #define SAA7134_I2S_AUDIO_OUTPUT 0x1c0 |
| 361 | |
| 362 | /* test modes */ |
| 363 | #define SAA7134_SPECIAL_MODE 0x1d0 |
| Nickolay V. Shmyrev | bb881f1 | 2005-11-08 21:36:35 -0800 | [diff] [blame] | 364 | #define SAA7134_PRODUCTION_TEST_MODE 0x1d1 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | |
| 366 | /* audio -- saa7133 + saa7135 only */ |
| 367 | #define SAA7135_DSP_RWSTATE 0x580 |
| 368 | #define SAA7135_DSP_RWSTATE_ERR (1 << 3) |
| 369 | #define SAA7135_DSP_RWSTATE_IDA (1 << 2) |
| 370 | #define SAA7135_DSP_RWSTATE_RDB (1 << 1) |
| 371 | #define SAA7135_DSP_RWSTATE_WRR (1 << 0) |
| 372 | |
| Hartmut Hackmann | 867bc6c | 2008-04-22 14:46:07 -0300 | [diff] [blame] | 373 | #define SAA7135_DSP_RWCLEAR 0x586 |
| 374 | #define SAA7135_DSP_RWCLEAR_RERR 1 |
| 375 | |
| Dmitry Belimov | 37df96d | 2008-06-10 12:43:58 -0300 | [diff] [blame] | 376 | #define SAA7133_I2S_AUDIO_CONTROL 0x591 |