Ariel D'Alessandro | 7c25f8c | 2015-08-01 15:37:16 -0300 | [diff] [blame] | 1 | /* |
| 2 | * NXP LPC18xx Watchdog Timer (WDT) |
| 3 | * |
| 4 | * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | * |
| 10 | * Notes |
| 11 | * ----- |
| 12 | * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit |
| 13 | * counter which decrements on every clock cycle. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/reboot.h> |
| 22 | #include <linux/watchdog.h> |
| 23 | |
| 24 | /* Registers */ |
| 25 | #define LPC18XX_WDT_MOD 0x00 |
| 26 | #define LPC18XX_WDT_MOD_WDEN BIT(0) |
| 27 | #define LPC18XX_WDT_MOD_WDRESET BIT(1) |
| 28 | |
| 29 | #define LPC18XX_WDT_TC 0x04 |
| 30 | #define LPC18XX_WDT_TC_MIN 0xff |
| 31 | #define LPC18XX_WDT_TC_MAX 0xffffff |
| 32 | |
| 33 | #define LPC18XX_WDT_FEED 0x08 |
| 34 | #define LPC18XX_WDT_FEED_MAGIC1 0xaa |
| 35 | #define LPC18XX_WDT_FEED_MAGIC2 0x55 |
| 36 | |
| 37 | #define LPC18XX_WDT_TV 0x0c |
| 38 | |
| 39 | /* Clock pre-scaler */ |
| 40 | #define LPC18XX_WDT_CLK_DIV 4 |
| 41 | |
| 42 | /* Timeout values in seconds */ |
| 43 | #define LPC18XX_WDT_DEF_TIMEOUT 30U |
| 44 | |
| 45 | static int heartbeat; |
| 46 | module_param(heartbeat, int, 0); |
| 47 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default=" |
| 48 | __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")"); |
| 49 | |
| 50 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 51 | module_param(nowayout, bool, 0); |
| 52 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 53 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 54 | |
| 55 | struct lpc18xx_wdt_dev { |
| 56 | struct watchdog_device wdt_dev; |
| 57 | struct clk *reg_clk; |
| 58 | struct clk *wdt_clk; |
| 59 | unsigned long clk_rate; |
| 60 | void __iomem *base; |
| 61 | struct timer_list timer; |
| 62 | struct notifier_block restart_handler; |
| 63 | spinlock_t lock; |
| 64 | }; |
| 65 | |
| 66 | static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev) |
| 67 | { |
| 68 | struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev); |
| 69 | unsigned long flags; |
| 70 | |
| 71 | /* |
| 72 | * An abort condition will occur if an interrupt happens during the feed |
| 73 | * sequence. |
| 74 | */ |
| 75 | spin_lock_irqsave(&lpc18xx_wdt->lock, flags); |
| 76 | writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 77 | writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 78 | spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags); |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static void lpc18xx_wdt_timer_feed(unsigned long data) |
| 84 | { |
| 85 | struct watchdog_device *wdt_dev = (struct watchdog_device *)data; |
| 86 | struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev); |
| 87 | |
| 88 | lpc18xx_wdt_feed(wdt_dev); |
| 89 | |
| 90 | /* Use safe value (1/2 of real timeout) */ |
| 91 | mod_timer(&lpc18xx_wdt->timer, jiffies + |
| 92 | msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2)); |
| 93 | } |
| 94 | |
| 95 | /* |
| 96 | * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding |
| 97 | * it with a timer until userspace watchdog software takes over. |
| 98 | */ |
| 99 | static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev) |
| 100 | { |
| 101 | lpc18xx_wdt_timer_feed((unsigned long)wdt_dev); |
| 102 | |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt) |
| 107 | { |
| 108 | unsigned int val; |
| 109 | |
| 110 | val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate, |
| 111 | LPC18XX_WDT_CLK_DIV); |
| 112 | writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC); |
| 113 | } |
| 114 | |
| 115 | static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev, |
| 116 | unsigned int new_timeout) |
| 117 | { |
| 118 | struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev); |
| 119 | |
| 120 | lpc18xx_wdt->wdt_dev.timeout = new_timeout; |
| 121 | __lpc18xx_wdt_set_timeout(lpc18xx_wdt); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
Fengguang Wu | 6cd8a1b | 2015-08-07 10:28:40 -0700 | [diff] [blame] | 126 | static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev) |
Ariel D'Alessandro | 7c25f8c | 2015-08-01 15:37:16 -0300 | [diff] [blame] | 127 | { |
| 128 | struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev); |
| 129 | unsigned int val; |
| 130 | |
| 131 | val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV); |
| 132 | return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; |
| 133 | } |
| 134 | |
| 135 | static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev) |
| 136 | { |
| 137 | struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev); |
| 138 | unsigned int val; |
| 139 | |
| 140 | if (timer_pending(&lpc18xx_wdt->timer)) |
| 141 | del_timer(&lpc18xx_wdt->timer); |
| 142 | |
| 143 | val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); |
| 144 | val |= LPC18XX_WDT_MOD_WDEN; |
| 145 | val |= LPC18XX_WDT_MOD_WDRESET; |
| 146 | writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); |
| 147 | |
| 148 | /* |
| 149 | * Setting the WDEN bit in the WDMOD register is not sufficient to |
| 150 | * enable the Watchdog. A valid feed sequence must be completed after |
| 151 | * setting WDEN before the Watchdog is capable of generating a reset. |
| 152 | */ |
| 153 | lpc18xx_wdt_feed(wdt_dev); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | static struct watchdog_info lpc18xx_wdt_info = { |
| 159 | .identity = "NXP LPC18xx Watchdog", |
| 160 | .options = WDIOF_SETTIMEOUT | |
| 161 | WDIOF_KEEPALIVEPING | |
| 162 | WDIOF_MAGICCLOSE, |
| 163 | }; |
| 164 | |
| 165 | static const struct watchdog_ops lpc18xx_wdt_ops = { |
| 166 | .owner = THIS_MODULE, |
| 167 | .start = lpc18xx_wdt_start, |
| 168 | .stop = lpc18xx_wdt_stop, |
| 169 | .ping = lpc18xx_wdt_feed, |
| 170 | .set_timeout = lpc18xx_wdt_set_timeout, |
| 171 | .get_timeleft = lpc18xx_wdt_get_timeleft, |
| 172 | }; |
| 173 | |
| 174 | static int lpc18xx_wdt_restart(struct notifier_block *this, unsigned long mode, |
| 175 | void *cmd) |
| 176 | { |
| 177 | struct lpc18xx_wdt_dev *lpc18xx_wdt = container_of(this, |
| 178 | struct lpc18xx_wdt_dev, restart_handler); |
| 179 | unsigned long flags; |
| 180 | int val; |
| 181 | |
| 182 | /* |
| 183 | * Incorrect feed sequence causes immediate watchdog reset if enabled. |
| 184 | */ |
| 185 | spin_lock_irqsave(&lpc18xx_wdt->lock, flags); |
| 186 | |
| 187 | val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); |
| 188 | val |= LPC18XX_WDT_MOD_WDEN; |
| 189 | val |= LPC18XX_WDT_MOD_WDRESET; |
| 190 | writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); |
| 191 | |
| 192 | writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 193 | writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 194 | |
| 195 | writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 196 | writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); |
| 197 | |
| 198 | spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags); |
| 199 | |
| 200 | return NOTIFY_OK; |
| 201 | } |
| 202 | |
| 203 | static int lpc18xx_wdt_probe(struct platform_device *pdev) |
| 204 | { |
| 205 | struct lpc18xx_wdt_dev *lpc18xx_wdt; |
| 206 | struct device *dev = &pdev->dev; |
| 207 | struct resource *res; |
| 208 | int ret; |
| 209 | |
| 210 | lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL); |
| 211 | if (!lpc18xx_wdt) |
| 212 | return -ENOMEM; |
| 213 | |
| 214 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 215 | lpc18xx_wdt->base = devm_ioremap_resource(dev, res); |
| 216 | if (IS_ERR(lpc18xx_wdt->base)) |
| 217 | return PTR_ERR(lpc18xx_wdt->base); |
| 218 | |
| 219 | lpc18xx_wdt->reg_clk = devm_clk_get(dev, "reg"); |
| 220 | if (IS_ERR(lpc18xx_wdt->reg_clk)) { |
| 221 | dev_err(dev, "failed to get the reg clock\n"); |
| 222 | return PTR_ERR(lpc18xx_wdt->reg_clk); |
| 223 | } |
| 224 | |
| 225 | lpc18xx_wdt->wdt_clk = devm_clk_get(dev, "wdtclk"); |
| 226 | if (IS_ERR(lpc18xx_wdt->wdt_clk)) { |
| 227 | dev_err(dev, "failed to get the wdt clock\n"); |
| 228 | return PTR_ERR(lpc18xx_wdt->wdt_clk); |
| 229 | } |
| 230 | |
| 231 | ret = clk_prepare_enable(lpc18xx_wdt->reg_clk); |
| 232 | if (ret) { |
| 233 | dev_err(dev, "could not prepare or enable sys clock\n"); |
| 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | ret = clk_prepare_enable(lpc18xx_wdt->wdt_clk); |
| 238 | if (ret) { |
| 239 | dev_err(dev, "could not prepare or enable wdt clock\n"); |
| 240 | goto disable_reg_clk; |
| 241 | } |
| 242 | |
| 243 | /* We use the clock rate to calculate timeouts */ |
| 244 | lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk); |
| 245 | if (lpc18xx_wdt->clk_rate == 0) { |
| 246 | dev_err(dev, "failed to get clock rate\n"); |
| 247 | ret = -EINVAL; |
| 248 | goto disable_wdt_clk; |
| 249 | } |
| 250 | |
| 251 | lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info; |
| 252 | lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops; |
| 253 | |
| 254 | lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN * |
| 255 | LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate); |
| 256 | |
| 257 | lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX * |
| 258 | LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; |
| 259 | |
| 260 | lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout, |
| 261 | LPC18XX_WDT_DEF_TIMEOUT); |
| 262 | |
| 263 | spin_lock_init(&lpc18xx_wdt->lock); |
| 264 | |
| 265 | lpc18xx_wdt->wdt_dev.parent = dev; |
| 266 | watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt); |
| 267 | |
| 268 | ret = watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev); |
| 269 | |
| 270 | __lpc18xx_wdt_set_timeout(lpc18xx_wdt); |
| 271 | |
| 272 | setup_timer(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, |
| 273 | (unsigned long)&lpc18xx_wdt->wdt_dev); |
| 274 | |
| 275 | watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout); |
| 276 | |
| 277 | platform_set_drvdata(pdev, lpc18xx_wdt); |
| 278 | |
| 279 | ret = watchdog_register_device(&lpc18xx_wdt->wdt_dev); |
| 280 | if (ret) |
| 281 | goto disable_wdt_clk; |
| 282 | |
| 283 | lpc18xx_wdt->restart_handler.notifier_call = lpc18xx_wdt_restart; |
| 284 | lpc18xx_wdt->restart_handler.priority = 128; |
| 285 | ret = register_restart_handler(&lpc18xx_wdt->restart_handler); |
| 286 | if (ret) |
| 287 | dev_warn(dev, "failed to register restart handler: %d\n", ret); |
| 288 | |
| 289 | return 0; |
| 290 | |
| 291 | disable_wdt_clk: |
| 292 | clk_disable_unprepare(lpc18xx_wdt->wdt_clk); |
| 293 | disable_reg_clk: |
| 294 | clk_disable_unprepare(lpc18xx_wdt->reg_clk); |
| 295 | return ret; |
| 296 | } |
| 297 | |
| 298 | static void lpc18xx_wdt_shutdown(struct platform_device *pdev) |
| 299 | { |
| 300 | struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev); |
| 301 | |
| 302 | lpc18xx_wdt_stop(&lpc18xx_wdt->wdt_dev); |
| 303 | } |
| 304 | |
| 305 | static int lpc18xx_wdt_remove(struct platform_device *pdev) |
| 306 | { |
| 307 | struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev); |
| 308 | |
| 309 | unregister_restart_handler(&lpc18xx_wdt->restart_handler); |
| 310 | |
| 311 | dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n"); |
| 312 | del_timer(&lpc18xx_wdt->timer); |
| 313 | |
| 314 | watchdog_unregister_device(&lpc18xx_wdt->wdt_dev); |
| 315 | clk_disable_unprepare(lpc18xx_wdt->wdt_clk); |
| 316 | clk_disable_unprepare(lpc18xx_wdt->reg_clk); |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static const struct of_device_id lpc18xx_wdt_match[] = { |
| 322 | { .compatible = "nxp,lpc1850-wwdt" }, |
| 323 | {} |
| 324 | }; |
| 325 | MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match); |
| 326 | |
| 327 | static struct platform_driver lpc18xx_wdt_driver = { |
| 328 | .driver = { |
| 329 | .name = "lpc18xx-wdt", |
| 330 | .of_match_table = lpc18xx_wdt_match, |
| 331 | }, |
| 332 | .probe = lpc18xx_wdt_probe, |
| 333 | .remove = lpc18xx_wdt_remove, |
| 334 | .shutdown = lpc18xx_wdt_shutdown, |
| 335 | }; |
| 336 | module_platform_driver(lpc18xx_wdt_driver); |
| 337 | |
| 338 | MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); |
| 339 | MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver"); |
| 340 | MODULE_LICENSE("GPL v2"); |