blob: 03fcbd082593b18eb32373f079dc15ae47392b8e [file] [log] [blame]
Sascha Hauer198016e2009-02-06 15:38:22 +01001
2#include <linux/module.h>
Fabio Estevambb07d752012-02-29 10:28:08 -03003#include <linux/io.h>
Shawn Guo50f2de62012-09-14 14:14:45 +08004
5#include "hardware.h"
Sascha Hauer198016e2009-02-06 15:38:22 +01006
7unsigned int __mxc_cpu_type;
8EXPORT_SYMBOL(__mxc_cpu_type);
9
10void mxc_set_cpu_type(unsigned int type)
11{
12 __mxc_cpu_type = type;
13}
14
Fabio Estevam059e58f2011-08-26 13:35:18 +080015void imx_print_silicon_rev(const char *cpu, int srev)
16{
17 if (srev == IMX_CHIP_REVISION_UNKNOWN)
18 pr_info("CPU identified as %s, unknown revision\n", cpu);
19 else
20 pr_info("CPU identified as %s, silicon rev %d.%d\n",
21 cpu, (srev >> 4) & 0xf, srev & 0xf);
22}
Fabio Estevambb07d752012-02-29 10:28:08 -030023
24void __init imx_set_aips(void __iomem *base)
25{
26 unsigned int reg;
27/*
28 * Set all MPROTx to be non-bufferable, trusted for R/W,
29 * not forced to user-mode.
30 */
31 __raw_writel(0x77777777, base + 0x0);
32 __raw_writel(0x77777777, base + 0x4);
33
34/*
35 * Set all OPACRx to be non-bufferable, to not require
36 * supervisor privilege level for access, allow for
37 * write access and untrusted master access.
38 */
39 __raw_writel(0x0, base + 0x40);
40 __raw_writel(0x0, base + 0x44);
41 __raw_writel(0x0, base + 0x48);
42 __raw_writel(0x0, base + 0x4C);
43 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
44 __raw_writel(reg, base + 0x50);
45}