| Barry Song | 5fa2f9a | 2013-03-18 15:04:39 +0800 | [diff] [blame] | 1 | /* |
| 2 | * DTS file for CSR SiRFatlas6 SoC |
| 3 | * |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 5 | * |
| 6 | * Licensed under GPLv2 or later. |
| 7 | */ |
| 8 | |
| 9 | /include/ "skeleton.dtsi" |
| 10 | / { |
| 11 | compatible = "sirf,atlas6"; |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | interrupt-parent = <&intc>; |
| 15 | |
| 16 | cpus { |
| 17 | #address-cells = <1>; |
| 18 | #size-cells = <0>; |
| 19 | |
| 20 | cpu@0 { |
| 21 | reg = <0x0>; |
| 22 | d-cache-line-size = <32>; |
| 23 | i-cache-line-size = <32>; |
| 24 | d-cache-size = <32768>; |
| 25 | i-cache-size = <32768>; |
| 26 | /* from bootloader */ |
| 27 | timebase-frequency = <0>; |
| 28 | bus-frequency = <0>; |
| 29 | clock-frequency = <0>; |
| 30 | }; |
| 31 | }; |
| 32 | |
| 33 | axi { |
| 34 | compatible = "simple-bus"; |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <1>; |
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; |
| 38 | |
| 39 | intc: interrupt-controller@80020000 { |
| 40 | #interrupt-cells = <1>; |
| 41 | interrupt-controller; |
| 42 | compatible = "sirf,prima2-intc"; |
| 43 | reg = <0x80020000 0x1000>; |
| 44 | }; |
| 45 | |
| 46 | sys-iobg { |
| 47 | compatible = "simple-bus"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | ranges = <0x88000000 0x88000000 0x40000>; |
| 51 | |
| 52 | clks: clock-controller@88000000 { |
| 53 | compatible = "sirf,atlas6-clkc"; |
| 54 | reg = <0x88000000 0x1000>; |
| 55 | interrupts = <3>; |
| 56 | #clock-cells = <1>; |
| 57 | }; |
| 58 | |
| 59 | reset-controller@88010000 { |
| 60 | compatible = "sirf,prima2-rstc"; |
| 61 | reg = <0x88010000 0x1000>; |
| 62 | }; |
| 63 | |
| 64 | rsc-controller@88020000 { |
| 65 | compatible = "sirf,prima2-rsc"; |
| 66 | reg = <0x88020000 0x1000>; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | mem-iobg { |
| 71 | compatible = "simple-bus"; |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <1>; |
| 74 | ranges = <0x90000000 0x90000000 0x10000>; |
| 75 | |
| 76 | memory-controller@90000000 { |
| 77 | compatible = "sirf,prima2-memc"; |
| 78 | reg = <0x90000000 0x10000>; |
| 79 | interrupts = <27>; |
| 80 | clocks = <&clks 5>; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | disp-iobg { |
| 85 | compatible = "simple-bus"; |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <1>; |
| 88 | ranges = <0x90010000 0x90010000 0x30000>; |
| 89 | |
| 90 | lcd@90010000 { |
| 91 | compatible = "sirf,prima2-lcd"; |
| 92 | reg = <0x90010000 0x20000>; |
| 93 | interrupts = <30>; |
| 94 | clocks = <&clks 34>; |
| 95 | display=<&display>; |
| 96 | /* later transfer to pwm */ |
| 97 | bl-gpio = <&gpio 7 0>; |
| 98 | default-panel = <&panel0>; |
| 99 | }; |
| 100 | |
| 101 | vpp@90020000 { |
| 102 | compatible = "sirf,prima2-vpp"; |
| 103 | reg = <0x90020000 0x10000>; |
| 104 | interrupts = <31>; |
| 105 | clocks = <&clks 35>; |
| 106 | }; |
| 107 | }; |
| 108 | |
| 109 | graphics-iobg { |
| 110 | compatible = "simple-bus"; |
| 111 | #address-cells = <1>; |
| 112 | #size-cells = <1>; |
| 113 | ranges = <0x98000000 0x98000000 0x8000000>; |
| 114 | |
| 115 | graphics@98000000 { |
| 116 | compatible = "powervr,sgx510"; |
| 117 | reg = <0x98000000 0x8000000>; |
| 118 | interrupts = <6>; |
| 119 | clocks = <&clks 32>; |
| 120 | }; |
| 121 | }; |
| 122 | |
| 123 | dsp-iobg { |
| 124 | compatible = "simple-bus"; |
| 125 | #address-cells = <1>; |
| 126 | #size-cells = <1>; |
| 127 | ranges = <0xa8000000 0xa8000000 0x2000000>; |
| 128 | |
| 129 | dspif@a8000000 { |
| 130 | compatible = "sirf,prima2-dspif"; |
| 131 | reg = <0xa8000000 0x10000>; |
| 132 | interrupts = <9>; |
| 133 | }; |
| 134 | |
| 135 | gps@a8010000 { |
| 136 | compatible = "sirf,prima2-gps"; |
| 137 | reg = <0xa8010000 0x10000>; |
| 138 | interrupts = <7>; |
| 139 | clocks = <&clks 9>; |
| 140 | }; |
| 141 | |
| 142 | dsp@a9000000 { |
| 143 | compatible = "sirf,prima2-dsp"; |
| 144 | reg = <0xa9000000 0x1000000>; |
| 145 | interrupts = <8>; |
| 146 | clocks = <&clks 8>; |
| 147 | }; |
| 148 | }; |
| 149 | |
| 150 | peri-iobg { |
| 151 | compatible = "simple-bus"; |
| 152 | #address-cells = <1>; |
| 153 | #size-cells = <1>; |
| 154 | ranges = <0xb0000000 0xb0000000 0x180000>, |
| 155 | <0x56000000 0x56000000 0x1b00000>; |
| 156 | |
| 157 | timer@b0020000 { |
| 158 | compatible = "sirf,prima2-tick"; |
| 159 | reg = <0xb0020000 0x1000>; |
| 160 | interrupts = <0>; |
| 161 | }; |
| 162 | |
| 163 | nand@b0030000 { |
| 164 | compatible = "sirf,prima2-nand"; |
| 165 | reg = <0xb0030000 0x10000>; |
| 166 | interrupts = <41>; |
| 167 | clocks = <&clks 26>; |
| 168 | }; |
| 169 | |
| 170 | audio@b0040000 { |
| 171 | compatible = "sirf,prima2-audio"; |
| 172 | reg = <0xb0040000 0x10000>; |
| 173 | interrupts = <35>; |
| 174 | clocks = <&clks 27>; |
| 175 | }; |
| 176 | |
| 177 | uart0: uart@b0050000 { |
| 178 | cell-index = <0>; |
| 179 | compatible = "sirf,prima2-uart"; |
| 180 | reg = <0xb0050000 0x1000>; |
| 181 | interrupts = <17>; |
| 182 | fifosize = <128>; |
| 183 | clocks = <&clks 13>; |
| 184 | }; |
| 185 | |
| 186 | uart1: uart@b0060000 { |
| 187 | cell-index = <1>; |
| 188 | compatible = "sirf,prima2-uart"; |
| 189 | reg = <0xb0060000 0x1000>; |
| 190 | interrupts = <18>; |
| 191 | fifosize = <32>; |
| 192 | clocks = <&clks 14>; |
| 193 | }; |
| 194 | |
| 195 | uart2: uart@b0070000 { |
| 196 | cell-index = <2>; |
| 197 | compatible = "sirf,prima2-uart"; |
| 198 | reg = <0xb0070000 0x1000>; |
| 199 | interrupts = <19>; |
| 200 | fifosize = <128>; |
| 201 | clocks = <&clks 15>; |
| 202 | }; |
| 203 | |
| 204 | usp0: usp@b0080000 { |
| 205 | cell-index = <0>; |
| 206 | compatible = "sirf,prima2-usp"; |
| 207 | reg = <0xb0080000 0x10000>; |
| 208 | interrupts = <20>; |
| 209 | clocks = <&clks 28>; |
| 210 | }; |
| 211 | |
| 212 | usp1: usp@b0090000 { |
| 213 | cell-index = <1>; |
| 214 | compatible = "sirf,prima2-usp"; |
| 215 | reg = <0xb0090000 0x10000>; |
| 216 | interrupts = <21>; |
| 217 | clocks = <&clks 29>; |
| 218 | }; |
| 219 | |
| 220 | dmac0: dma-controller@b00b0000 { |
| 221 | cell-index = <0>; |
| 222 | compatible = "sirf,prima2-dmac"; |
| 223 | reg = <0xb00b0000 0x10000>; |
| 224 | interrupts = <12>; |
| 225 | clocks = <&clks 24>; |
| 226 | }; |
| 227 | |
| 228 | dmac1: dma-controller@b0160000 { |
| 229 | cell-index = <1>; |
| 230 | compatible = "sirf,prima2-dmac"; |
| 231 | reg = <0xb0160000 0x10000>; |
| 232 | interrupts = <13>; |
| 233 | clocks = <&clks 25>; |
| 234 | }; |
| 235 | |
| 236 | vip@b00C0000 { |
| 237 | compatible = "sirf,prima2-vip"; |
| 238 | reg = <0xb00C0000 0x10000>; |
| 239 | clocks = <&clks 31>; |
| 240 | }; |
| 241 | |
| 242 | spi0: spi@b00d0000 { |
| 243 | cell-index = <0>; |
| 244 | compatible = "sirf,prima2-spi"; |
| 245 | reg = <0xb00d0000 0x10000>; |
| 246 | interrupts = <15>; |
| 247 | sirf,spi-num-chipselects = <1>; |
| 248 | cs-gpios = <&gpio 0 0>; |
| 249 | sirf,spi-dma-rx-channel = <25>; |
| 250 | sirf,spi-dma-tx-channel = <20>; |
| 251 | #address-cells = <1>; |
| 252 | #size-cells = <0>; |
| 253 | clocks = <&clks 19>; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
| 257 | spi1: spi@b0170000 { |
| 258 | cell-index = <1>; |
| 259 | compatible = "sirf,prima2-spi"; |
| 260 | reg = <0xb0170000 0x10000>; |
| 261 | interrupts = <16>; |
| 262 | clocks = <&clks 20>; |
| 263 | status = "disabled"; |
| 264 | }; |
| 265 | |
| 266 | i2c0: i2c@b00e0000 { |
| 267 | cell-index = <0>; |
| 268 | compatible = "sirf,prima2-i2c"; |
| 269 | reg = <0xb00e0000 0x10000>; |
| 270 | interrupts = <24>; |
| 271 | #address-cells = <1>; |
| 272 | #size-cells = <0>; |
| 273 | clocks = <&clks 17>; |
| 274 | }; |
| 275 | |
| 276 | i2c1: i2c@b00f0000 { |
| 277 | cell-index = <1>; |
| 278 | compatible = "sirf,prima2-i2c"; |
| 279 | reg = <0xb00f0000 0x10000>; |
| 280 | interrupts = <25>; |
| 281 | #address-cells = <1>; |
| 282 | #size-cells = <0>; |
| 283 | clocks = <&clks 18>; |
| 284 | }; |
| 285 | |
| 286 | tsc@b0110000 { |
| 287 | compatible = "sirf,prima2-tsc"; |
| 288 | reg = <0xb0110000 0x10000>; |
| 289 | interrupts = <33>; |
| 290 | clocks = <&clks 16>; |
| 291 | }; |
| 292 | |
| 293 | gpio: pinctrl@b0120000 { |
| 294 | #gpio-cells = <2>; |
| 295 | #interrupt-cells = <2>; |
| 296 | compatible = "sirf,atlas6-pinctrl"; |
| 297 | reg = <0xb0120000 0x10000>; |
| 298 | interrupts = <43 44 45 46 47>; |
| 299 | gpio-controller; |
| 300 | interrupt-controller; |
| 301 | |
| 302 | lcd_16pins_a: lcd0@0 { |
| 303 | lcd { |
| 304 | sirf,pins = "lcd_16bitsgrp"; |
| 305 | sirf,function = "lcd_16bits"; |
| 306 | }; |
| 307 | }; |
| 308 | lcd_18pins_a: lcd0@1 { |
| 309 | lcd { |
| 310 | sirf,pins = "lcd_18bitsgrp"; |
| 311 | sirf,function = "lcd_18bits"; |
| 312 | }; |
| 313 | }; |
| 314 | lcd_24pins_a: lcd0@2 { |
| 315 | lcd { |
| 316 | sirf,pins = "lcd_24bitsgrp"; |
| 317 | sirf,function = "lcd_24bits"; |
| 318 | }; |
| 319 | }; |
| 320 | lcdrom_pins_a: lcdrom0@0 { |
| 321 | lcd { |
| 322 | sirf,pins = "lcdromgrp"; |
| 323 | sirf,function = "lcdrom"; |
| 324 | }; |
| 325 | }; |
| 326 | uart0_pins_a: uart0@0 { |
| 327 | uart { |
| 328 | sirf,pins = "uart0grp"; |
| 329 | sirf,function = "uart0"; |
| 330 | }; |
| 331 | }; |
| 332 | uart1_pins_a: uart1@0 { |
| 333 | uart { |
| 334 | sirf,pins = "uart1grp"; |
| 335 | sirf,function = "uart1"; |
| 336 | }; |
| 337 | }; |
| 338 | uart2_pins_a: uart2@0 { |
| 339 | uart { |
| 340 | sirf,pins = "uart2grp"; |
| 341 | sirf,function = "uart2"; |
| 342 | }; |
| 343 | }; |
| 344 | uart2_noflow_pins_a: uart2@1 { |
| 345 | uart { |
| 346 | sirf,pins = "uart2_nostreamctrlgrp"; |
| 347 | sirf,function = "uart2_nostreamctrl"; |
| 348 | }; |
| 349 | }; |
| 350 | spi0_pins_a: spi0@0 { |
| 351 | spi { |
| 352 | sirf,pins = "spi0grp"; |
| 353 | sirf,function = "spi0"; |
| 354 | }; |
| 355 | }; |
| 356 | spi1_pins_a: spi1@0 { |
| 357 | spi { |
| 358 | sirf,pins = "spi1grp"; |
| 359 | sirf,function = "spi1"; |
| 360 | }; |
| 361 | }; |
| 362 | i2c0_pins_a: i2c0@0 { |
| 363 | i2c { |
| 364 | sirf,pins = "i2c0grp"; |
| 365 | sirf,function = "i2c0"; |
| 366 | }; |
| 367 | }; |
| 368 | i2c1_pins_a: i2c1@0 { |
| 369 | i2c { |
| 370 | sirf,pins = "i2c1grp"; |
| 371 | sirf,function = "i2c1"; |
| 372 | }; |
| 373 | }; |
| 374 | pwm0_pins_a: pwm0@0 { |
| 375 | pwm { |
| 376 | sirf,pins = "pwm0grp"; |
| 377 | sirf,function = "pwm0"; |
| 378 | }; |
| 379 | }; |
| 380 | pwm1_pins_a: pwm1@0 { |
| 381 | pwm { |
| 382 | sirf,pins = "pwm1grp"; |
| 383 | sirf,function = "pwm1"; |
| 384 | }; |
| 385 | }; |
| 386 | pwm2_pins_a: pwm2@0 { |
| 387 | pwm { |
| 388 | sirf,pins = "pwm2grp"; |
| 389 | sirf,function = "pwm2"; |
| 390 | }; |
| 391 | }; |
| 392 | pwm3_pins_a: pwm3@0 { |
| 393 | pwm { |
| 394 | sirf,pins = "pwm3grp"; |
| 395 | sirf,function = "pwm3"; |
| 396 | }; |
| 397 | }; |
| 398 | pwm4_pins_a: pwm4@0 { |
| 399 | pwm { |
| 400 | sirf,pins = "pwm4grp"; |
| 401 | sirf,function = "pwm4"; |
| 402 | }; |
| 403 | }; |
| 404 | gps_pins_a: gps@0 { |
| 405 | gps { |
| 406 | sirf,pins = "gpsgrp"; |
| 407 | sirf,function = "gps"; |
| 408 | }; |
| 409 | }; |
| 410 | vip_pins_a: vip@0 { |
| 411 | vip { |
| 412 | sirf,pins = "vipgrp"; |
| 413 | sirf,function = "vip"; |
| 414 | }; |
| 415 | }; |
| 416 | sdmmc0_pins_a: sdmmc0@0 { |
| 417 | sdmmc0 { |
| 418 | sirf,pins = "sdmmc0grp"; |
| 419 | sirf,function = "sdmmc0"; |
| 420 | }; |
| 421 | }; |
| 422 | sdmmc1_pins_a: sdmmc1@0 { |
| 423 | sdmmc1 { |
| 424 | sirf,pins = "sdmmc1grp"; |
| 425 | sirf,function = "sdmmc1"; |
| 426 | }; |
| 427 | }; |
| 428 | sdmmc2_pins_a: sdmmc2@0 { |
| 429 | sdmmc2 { |
| 430 | sirf,pins = "sdmmc2grp"; |
| 431 | sirf,function = "sdmmc2"; |
| 432 | }; |
| 433 | }; |
| 434 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { |
| 435 | sdmmc2_nowp { |
| 436 | sirf,pins = "sdmmc2_nowpgrp"; |
| 437 | sirf,function = "sdmmc2_nowp"; |
| 438 | }; |
| 439 | }; |
| 440 | sdmmc3_pins_a: sdmmc3@0 { |
| 441 | sdmmc3 { |
| 442 | sirf,pins = "sdmmc3grp"; |
| 443 | sirf,function = "sdmmc3"; |
| 444 | }; |
| 445 | }; |
| 446 | sdmmc5_pins_a: sdmmc5@0 { |
| 447 | sdmmc5 { |
| 448 | sirf,pins = "sdmmc5grp"; |
| 449 | sirf,function = "sdmmc5"; |
| 450 | }; |
| 451 | }; |
| 452 | i2s_pins_a: i2s@0 { |
| 453 | i2s { |
| 454 | sirf,pins = "i2sgrp"; |
| 455 | sirf,function = "i2s"; |
| 456 | }; |
| 457 | }; |
| 458 | i2s_no_din_pins_a: i2s_no_din@0 { |
| 459 | i2s_no_din { |
| 460 | sirf,pins = "i2s_no_dingrp"; |
| 461 | sirf,function = "i2s_no_din"; |
| 462 | }; |
| 463 | }; |
| 464 | i2s_6chn_pins_a: i2s_6chn@0 { |
| 465 | i2s_6chn { |
| 466 | sirf,pins = "i2s_6chngrp"; |
| 467 | sirf,function = "i2s_6chn"; |
| 468 | }; |
| 469 | }; |
| 470 | ac97_pins_a: ac97@0 { |
| 471 | ac97 { |
| 472 | sirf,pins = "ac97grp"; |
| 473 | sirf,function = "ac97"; |
| 474 | }; |
| 475 | }; |
| 476 | nand_pins_a: nand@0 { |
| 477 | nand { |
| 478 | sirf,pins = "nandgrp"; |
| 479 | sirf,function = "nand"; |
| 480 | }; |
| 481 | }; |
| 482 | usp0_pins_a: usp0@0 { |
| 483 | usp0 { |
| 484 | sirf,pins = "usp0grp"; |
| 485 | sirf,function = "usp0"; |
| 486 | }; |
| 487 | }; |
| 488 | usp1_pins_a: usp1@0 { |
| 489 | usp1 { |
| 490 | sirf,pins = "usp1grp"; |
| 491 | sirf,function = "usp1"; |
| 492 | }; |
| 493 | }; |
| 494 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { |
| 495 | usb0_upli_drvbus { |
| 496 | sirf,pins = "usb0_upli_drvbusgrp"; |
| 497 | sirf,function = "usb0_upli_drvbus"; |
| 498 | }; |
| 499 | }; |
| 500 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { |
| 501 | usb1_utmi_drvbus { |
| 502 | sirf,pins = "usb1_utmi_drvbusgrp"; |
| 503 | sirf,function = "usb1_utmi_drvbus"; |
| 504 | }; |
| 505 | }; |
| 506 | warm_rst_pins_a: warm_rst@0 { |
| 507 | warm_rst { |
| 508 | sirf,pins = "warm_rstgrp"; |
| 509 | sirf,function = "warm_rst"; |
| 510 | }; |
| 511 | }; |
| 512 | pulse_count_pins_a: pulse_count@0 { |
| 513 | pulse_count { |
| 514 | sirf,pins = "pulse_countgrp"; |
| 515 | sirf,function = "pulse_count"; |
| 516 | }; |
| 517 | }; |
| 518 | cko0_rst_pins_a: cko0_rst@0 { |
| 519 | cko0_rst { |
| 520 | sirf,pins = "cko0_rstgrp"; |
| 521 | sirf,function = "cko0_rst"; |
| 522 | }; |
| 523 | }; |
| 524 | cko1_rst_pins_a: cko1_rst@0 { |
| 525 | cko1_rst { |
| 526 | sirf,pins = "cko1_rstgrp"; |
| 527 | sirf,function = "cko1_rst"; |
| 528 | }; |
| 529 | }; |
| 530 | }; |
| 531 | |
| 532 | pwm@b0130000 { |
| 533 | compatible = "sirf,prima2-pwm"; |
| 534 | reg = <0xb0130000 0x10000>; |
| 535 | clocks = <&clks 21>; |
| 536 | }; |
| 537 | |
| 538 | efusesys@b0140000 { |
| 539 | compatible = "sirf,prima2-efuse"; |
| 540 | reg = <0xb0140000 0x10000>; |
| 541 | clocks = <&clks 22>; |
| 542 | }; |
| 543 | |
| 544 | pulsec@b0150000 { |
| 545 | compatible = "sirf,prima2-pulsec"; |
| 546 | reg = <0xb0150000 0x10000>; |
| 547 | interrupts = <48>; |
| 548 | clocks = <&clks 23>; |
| 549 | }; |
| 550 | |
| 551 | pci-iobg { |
| 552 | compatible = "sirf,prima2-pciiobg", "simple-bus"; |
| 553 | #address-cells = <1>; |
| 554 | #size-cells = <1>; |
| 555 | ranges = <0x56000000 0x56000000 0x1b00000>; |
| 556 | |
| 557 | sd0: sdhci@56000000 { |
| 558 | cell-index = <0>; |
| 559 | compatible = "sirf,prima2-sdhc"; |
| 560 | reg = <0x56000000 0x100000>; |
| 561 | interrupts = <38>; |
| 562 | bus-width = <8>; |
| 563 | clocks = <&clks 36>; |
| 564 | }; |
| 565 | |
| 566 | sd1: sdhci@56100000 { |
| 567 | cell-index = <1>; |
| 568 | compatible = "sirf,prima2-sdhc"; |
| 569 | reg = <0x56100000 0x100000>; |
| 570 | interrupts = <38>; |
| 571 | status = "disabled"; |
| 572 | clocks = <&clks 36>; |
| 573 | }; |
| 574 | |
| 575 | sd2: sdhci@56200000 { |
| 576 | cell-index = <2>; |
| 577 | compatible = "sirf,prima2-sdhc"; |
| 578 | reg = <0x56200000 0x100000>; |
| 579 | interrupts = <23>; |
| 580 | status = "disabled"; |
| 581 | clocks = <&clks 37>; |
| 582 | }; |
| 583 | |
| 584 | sd3: sdhci@56300000 { |
| 585 | cell-index = <3>; |
| 586 | compatible = "sirf,prima2-sdhc"; |
| 587 | reg = <0x56300000 0x100000>; |
| 588 | interrupts = <23>; |
| 589 | status = "disabled"; |
| 590 | clocks = <&clks 37>; |
| 591 | }; |
| 592 | |
| 593 | sd5: sdhci@56500000 { |
| 594 | cell-index = <5>; |
| 595 | compatible = "sirf,prima2-sdhc"; |
| 596 | reg = <0x56500000 0x100000>; |
| 597 | interrupts = <39>; |
| 598 | status = "disabled"; |
| 599 | clocks = <&clks 38>; |
| 600 | }; |
| 601 | |
| 602 | pci-copy@57900000 { |
| 603 | compatible = "sirf,prima2-pcicp"; |
| 604 | reg = <0x57900000 0x100000>; |
| 605 | interrupts = <40>; |
| 606 | }; |
| 607 | |
| 608 | rom-interface@57a00000 { |
| 609 | compatible = "sirf,prima2-romif"; |
| 610 | reg = <0x57a00000 0x100000>; |
| 611 | }; |
| 612 | }; |
| 613 | }; |
| 614 | |
| 615 | rtc-iobg { |
| Xianglong Du | e88b815 | 2013-07-03 15:08:04 -0700 | [diff] [blame^] | 616 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
| Barry Song | 5fa2f9a | 2013-03-18 15:04:39 +0800 | [diff] [blame] | 617 | #address-cells = <1>; |
| 618 | #size-cells = <1>; |
| 619 | reg = <0x80030000 0x10000>; |
| 620 | |
| 621 | gpsrtc@1000 { |
| 622 | compatible = "sirf,prima2-gpsrtc"; |
| 623 | reg = <0x1000 0x1000>; |
| 624 | interrupts = <55 56 57>; |
| 625 | }; |
| 626 | |
| 627 | sysrtc@2000 { |
| 628 | compatible = "sirf,prima2-sysrtc"; |
| 629 | reg = <0x2000 0x1000>; |
| 630 | interrupts = <52 53 54>; |
| 631 | }; |
| 632 | |
| 633 | pwrc@3000 { |
| 634 | compatible = "sirf,prima2-pwrc"; |
| 635 | reg = <0x3000 0x1000>; |
| 636 | interrupts = <32>; |
| 637 | }; |
| 638 | }; |
| 639 | |
| 640 | uus-iobg { |
| 641 | compatible = "simple-bus"; |
| 642 | #address-cells = <1>; |
| 643 | #size-cells = <1>; |
| 644 | ranges = <0xb8000000 0xb8000000 0x40000>; |
| 645 | |
| 646 | usb0: usb@b00e0000 { |
| 647 | compatible = "chipidea,ci13611a-prima2"; |
| 648 | reg = <0xb8000000 0x10000>; |
| 649 | interrupts = <10>; |
| 650 | clocks = <&clks 40>; |
| 651 | }; |
| 652 | |
| 653 | usb1: usb@b00f0000 { |
| 654 | compatible = "chipidea,ci13611a-prima2"; |
| 655 | reg = <0xb8010000 0x10000>; |
| 656 | interrupts = <11>; |
| 657 | clocks = <&clks 41>; |
| 658 | }; |
| 659 | |
| 660 | security@b00f0000 { |
| 661 | compatible = "sirf,prima2-security"; |
| 662 | reg = <0xb8030000 0x10000>; |
| 663 | interrupts = <42>; |
| 664 | clocks = <&clks 7>; |
| 665 | }; |
| 666 | }; |
| 667 | }; |
| 668 | }; |