| Steven King | bea8bcb | 2012-06-06 14:28:31 -0700 | [diff] [blame] | 1 | /* |
| 2 | * m5441xsim.h -- Coldfire 5441x register definitions |
| 3 | * |
| 4 | * (C) Copyright 2012, Steven King <sfking@fdwdc.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef m5441xsim_h |
| 8 | #define m5441xsim_h |
| 9 | |
| 10 | #define CPU_NAME "COLDFIRE(m5441x)" |
| 11 | #define CPU_INSTR_PER_JIFFY 2 |
| 12 | #define MCF_BUSCLK (MCF_CLK / 2) |
| 13 | |
| 14 | #include <asm/m54xxacr.h> |
| 15 | |
| 16 | /* |
| 17 | * Reset Controller Module. |
| 18 | */ |
| 19 | |
| 20 | #define MCF_RCR 0xec090000 |
| 21 | #define MCF_RSR 0xec090001 |
| 22 | |
| 23 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 24 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| 25 | |
| 26 | /* |
| 27 | * Interrupt Controller Modules. |
| 28 | */ |
| 29 | /* the 5441x have 3 interrupt controllers, each control 64 interrupts */ |
| 30 | #define MCFINT_VECBASE 64 |
| 31 | #define MCFINT0_VECBASE MCFINT_VECBASE |
| 32 | #define MCFINT1_VECBASE (MCFINT0_VECBASE + 64) |
| 33 | #define MCFINT2_VECBASE (MCFINT1_VECBASE + 64) |
| 34 | |
| 35 | /* interrupt controller 0 */ |
| 36 | #define MCFINTC0_SIMR 0xfc04801c |
| 37 | #define MCFINTC0_CIMR 0xfc04801d |
| 38 | #define MCFINTC0_ICR0 0xfc048040 |
| 39 | /* interrupt controller 1 */ |
| 40 | #define MCFINTC1_SIMR 0xfc04c01c |
| 41 | #define MCFINTC1_CIMR 0xfc04c01d |
| 42 | #define MCFINTC1_ICR0 0xfc04c040 |
| 43 | /* interrupt controller 2 */ |
| 44 | #define MCFINTC2_SIMR 0xfc05001c |
| 45 | #define MCFINTC2_CIMR 0xfc05001d |
| 46 | #define MCFINTC2_ICR0 0xfc050040 |
| 47 | |
| 48 | /* on interrupt controller 0 */ |
| 49 | #define MCFINT0_EPORT0 1 |
| 50 | #define MCFINT0_UART0 26 |
| 51 | #define MCFINT0_UART1 27 |
| 52 | #define MCFINT0_UART2 28 |
| 53 | #define MCFINT0_UART3 29 |
| 54 | #define MCFINT0_I2C0 30 |
| 55 | #define MCFINT0_DSPI0 31 |
| 56 | |
| 57 | #define MCFINT0_TIMER0 32 |
| 58 | #define MCFINT0_TIMER1 33 |
| 59 | #define MCFINT0_TIMER2 34 |
| 60 | #define MCFINT0_TIMER3 35 |
| 61 | |
| 62 | #define MCFINT0_FECRX0 36 |
| 63 | #define MCFINT0_FECTX0 40 |
| 64 | #define MCFINT0_FECENTC0 42 |
| 65 | |
| 66 | #define MCFINT0_FECRX1 49 |
| 67 | #define MCFINT0_FECTX1 53 |
| 68 | #define MCFINT0_FECENTC1 55 |
| 69 | |
| 70 | /* on interrupt controller 1 */ |
| 71 | #define MCFINT1_UART4 48 |
| 72 | #define MCFINT1_UART5 49 |
| 73 | #define MCFINT1_UART6 50 |
| 74 | #define MCFINT1_UART7 51 |
| 75 | #define MCFINT1_UART8 52 |
| 76 | #define MCFINT1_UART9 53 |
| 77 | #define MCFINT1_DSPI1 54 |
| 78 | #define MCFINT1_DSPI2 55 |
| 79 | #define MCFINT1_DSPI3 56 |
| 80 | #define MCFINT1_I2C1 57 |
| 81 | #define MCFINT1_I2C2 58 |
| 82 | #define MCFINT1_I2C3 59 |
| 83 | #define MCFINT1_I2C4 60 |
| 84 | #define MCFINT1_I2C5 61 |
| 85 | |
| 86 | /* on interrupt controller 2 */ |
| 87 | #define MCFINT2_PIT0 13 |
| 88 | #define MCFINT2_PIT1 14 |
| 89 | #define MCFINT2_PIT2 15 |
| 90 | #define MCFINT2_PIT3 16 |
| 91 | #define MCFINT2_RTC 26 |
| 92 | |
| 93 | /* |
| 94 | * PIT timer module. |
| 95 | */ |
| 96 | #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */ |
| 97 | #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */ |
| 98 | #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */ |
| 99 | #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */ |
| 100 | |
| 101 | |
| 102 | #define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1) |
| 103 | |
| 104 | /* |
| 105 | * Power Management |
| 106 | */ |
| 107 | #define MCFPM_WCR 0xfc040013 |
| 108 | #define MCFPM_PPMSR0 0xfc04002c |
| 109 | #define MCFPM_PPMCR0 0xfc04002d |
| 110 | #define MCFPM_PPMSR1 0xfc04002e |
| 111 | #define MCFPM_PPMCR1 0xfc04002f |
| 112 | #define MCFPM_PPMHR0 0xfc040030 |
| 113 | #define MCFPM_PPMLR0 0xfc040034 |
| 114 | #define MCFPM_PPMHR1 0xfc040038 |
| 115 | #define MCFPM_PPMLR1 0xfc04003c |
| 116 | #define MCFPM_LPCR 0xec090007 |
| 117 | /* |
| 118 | * UART module. |
| 119 | */ |
| 120 | #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */ |
| 121 | #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */ |
| 122 | #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */ |
| 123 | #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */ |
| 124 | #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */ |
| 125 | #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */ |
| 126 | #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */ |
| 127 | #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */ |
| 128 | #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */ |
| 129 | #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */ |
| 130 | |
| 131 | #define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0) |
| 132 | #define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1) |
| 133 | #define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2) |
| 134 | #define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3) |
| 135 | #define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4) |
| 136 | #define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5) |
| 137 | #define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6) |
| 138 | #define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7) |
| 139 | #define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8) |
| 140 | #define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9) |
| 141 | /* |
| 142 | * FEC modules. |
| 143 | */ |
| 144 | #define MCFFEC_BASE0 0xfc0d4000 |
| 145 | #define MCFFEC_SIZE0 0x800 |
| 146 | #define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0) |
| 147 | #define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0) |
| 148 | #define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0) |
| 149 | |
| 150 | #define MCFFEC_BASE1 0xfc0d8000 |
| 151 | #define MCFFEC_SIZE1 0x800 |
| 152 | #define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1) |
| 153 | #define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1) |
| 154 | #define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1) |
| 155 | /* |
| 156 | * I2C modules. |
| 157 | */ |
| 158 | #define MCFI2C_BASE0 0xfc058000 |
| 159 | #define MCFI2C_SIZE0 0x20 |
| 160 | #define MCFI2C_BASE1 0xfc038000 |
| 161 | #define MCFI2C_SIZE1 0x20 |
| 162 | #define MCFI2C_BASE2 0xec010000 |
| 163 | #define MCFI2C_SIZE2 0x20 |
| 164 | #define MCFI2C_BASE3 0xec014000 |
| 165 | #define MCFI2C_SIZE3 0x20 |
| 166 | #define MCFI2C_BASE4 0xec018000 |
| 167 | #define MCFI2C_SIZE4 0x20 |
| 168 | #define MCFI2C_BASE5 0xec01c000 |
| 169 | #define MCFI2C_SIZE5 0x20 |
| 170 | |
| 171 | #define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0) |
| 172 | #define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1) |
| 173 | #define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2) |
| 174 | #define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3) |
| 175 | #define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4) |
| 176 | #define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5) |
| 177 | /* |
| 178 | * EPORT Module. |
| 179 | */ |
| 180 | #define MCFEPORT_EPPAR 0xfc090000 |
| 181 | #define MCFEPORT_EPIER 0xfc090003 |
| 182 | #define MCFEPORT_EPFR 0xfc090006 |
| Steven King | c785a3d | 2012-06-17 01:03:38 -0700 | [diff] [blame] | 183 | /* |
| 184 | * RTC Module. |
| 185 | */ |
| 186 | #define MCFRTC_BASE 0xfc0a8000 |
| 187 | #define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000) |
| 188 | #define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC) |
| Steven King | bea8bcb | 2012-06-06 14:28:31 -0700 | [diff] [blame] | 189 | |
| 190 | /* |
| 191 | * GPIO Module. |
| 192 | */ |
| 193 | #define MCFGPIO_PODR_A 0xec094000 |
| 194 | #define MCFGPIO_PODR_B 0xec094001 |
| 195 | #define MCFGPIO_PODR_C 0xec094002 |
| 196 | #define MCFGPIO_PODR_D 0xec094003 |
| 197 | #define MCFGPIO_PODR_E 0xec094004 |
| 198 | #define MCFGPIO_PODR_F 0xec094005 |
| 199 | #define MCFGPIO_PODR_G 0xec094006 |
| 200 | #define MCFGPIO_PODR_H 0xec094007 |
| 201 | #define MCFGPIO_PODR_I 0xec094008 |
| 202 | #define MCFGPIO_PODR_J 0xec094009 |
| 203 | #define MCFGPIO_PODR_K 0xec09400a |
| 204 | |
| 205 | #define MCFGPIO_PDDR_A 0xec09400c |
| 206 | #define MCFGPIO_PDDR_B 0xec09400d |
| 207 | #define MCFGPIO_PDDR_C 0xec09400e |
| 208 | #define MCFGPIO_PDDR_D 0xec09400f |
| 209 | #define MCFGPIO_PDDR_E 0xec094010 |
| 210 | #define MCFGPIO_PDDR_F 0xec094011 |
| 211 | #define MCFGPIO_PDDR_G 0xec094012 |
| 212 | #define MCFGPIO_PDDR_H 0xec094013 |
| 213 | #define MCFGPIO_PDDR_I 0xec094014 |
| 214 | #define MCFGPIO_PDDR_J 0xec094015 |
| 215 | #define MCFGPIO_PDDR_K 0xec094016 |
| 216 | |
| 217 | #define MCFGPIO_PPDSDR_A 0xec094018 |
| 218 | #define MCFGPIO_PPDSDR_B 0xec094019 |
| 219 | #define MCFGPIO_PPDSDR_C 0xec09401a |
| 220 | #define MCFGPIO_PPDSDR_D 0xec09401b |
| 221 | #define MCFGPIO_PPDSDR_E 0xec09401c |
| 222 | #define MCFGPIO_PPDSDR_F 0xec09401d |
| 223 | #define MCFGPIO_PPDSDR_G 0xec09401e |
| 224 | #define MCFGPIO_PPDSDR_H 0xec09401f |
| 225 | #define MCFGPIO_PPDSDR_I 0xec094020 |
| 226 | #define MCFGPIO_PPDSDR_J 0xec094021 |
| 227 | #define MCFGPIO_PPDSDR_K 0xec094022 |
| 228 | |
| 229 | #define MCFGPIO_PCLRR_A 0xec094024 |
| 230 | #define MCFGPIO_PCLRR_B 0xec094025 |
| 231 | #define MCFGPIO_PCLRR_C 0xec094026 |
| 232 | #define MCFGPIO_PCLRR_D 0xec094027 |
| 233 | #define MCFGPIO_PCLRR_E 0xec094028 |
| 234 | #define MCFGPIO_PCLRR_F 0xec094029 |
| 235 | #define MCFGPIO_PCLRR_G 0xec09402a |
| 236 | #define MCFGPIO_PCLRR_H 0xec09402b |
| 237 | #define MCFGPIO_PCLRR_I 0xec09402c |
| 238 | #define MCFGPIO_PCLRR_J 0xec09402d |
| 239 | #define MCFGPIO_PCLRR_K 0xec09402e |
| 240 | |
| 241 | #define MCFGPIO_PAR_FBCTL 0xec094048 |
| 242 | #define MCFGPIO_PAR_BE 0xec094049 |
| 243 | #define MCFGPIO_PAR_CS 0xec09404a |
| 244 | #define MCFGPIO_PAR_CANI2C 0xec09404b |
| 245 | #define MCFGPIO_PAR_IRQ0H 0xec09404c |
| 246 | #define MCFGPIO_PAR_IRQ0L 0xec09404d |
| 247 | #define MCFGPIO_PAR_DSPIOWH 0xec09404e |
| 248 | #define MCFGPIO_PAR_DSPIOWL 0xec09404f |
| 249 | #define MCFGPIO_PAR_TIMER 0xec094050 |
| 250 | #define MCFGPIO_PAR_UART2 0xec094051 |
| 251 | #define MCFGPIO_PAR_UART1 0xec094052 |
| 252 | #define MCFGPIO_PAR_UART0 0xec094053 |
| 253 | #define MCFGPIO_PAR_SDHCH 0xec094054 |
| 254 | #define MCFGPIO_PAR_SDHCL 0xec094055 |
| 255 | #define MCFGPIO_PAR_SIMP0H 0xec094056 |
| 256 | #define MCFGPIO_PAR_SIMP0L 0xec094057 |
| 257 | #define MCFGPIO_PAR_SSI0H 0xec094058 |
| 258 | #define MCFGPIO_PAR_SSI0L 0xec094059 |
| 259 | #define MCFGPIO_PAR_DEBUGH1 0xec09405a |
| 260 | #define MCFGPIO_PAR_DEBUGH0 0xec09405b |
| 261 | #define MCFGPIO_PAR_DEBUGl 0xec09405c |
| 262 | #define MCFGPIO_PAR_FEC 0xec09405e |
| 263 | |
| 264 | /* generalization for generic gpio support */ |
| 265 | #define MCFGPIO_PODR MCFGPIO_PODR_A |
| 266 | #define MCFGPIO_PDDR MCFGPIO_PDDR_A |
| 267 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A |
| 268 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_A |
| 269 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_A |
| 270 | |
| 271 | #define MCFGPIO_IRQ_MIN 17 |
| 272 | #define MCFGPIO_IRQ_MAX 24 |
| 273 | #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN) |
| 274 | #define MCFGPIO_PIN_MAX 87 |
| 275 | |
| 276 | #endif /* m5441xsim_h */ |