Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Xilinx, Inc. |
| 3 | * CEVA AHCI SATA platform driver |
| 4 | * |
| 5 | * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/ahci_platform.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/libata.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/of_device.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include "ahci.h" |
| 27 | |
| 28 | /* Vendor Specific Register Offsets */ |
| 29 | #define AHCI_VEND_PCFG 0xA4 |
| 30 | #define AHCI_VEND_PPCFG 0xA8 |
| 31 | #define AHCI_VEND_PP2C 0xAC |
| 32 | #define AHCI_VEND_PP3C 0xB0 |
| 33 | #define AHCI_VEND_PP4C 0xB4 |
| 34 | #define AHCI_VEND_PP5C 0xB8 |
| 35 | #define AHCI_VEND_PAXIC 0xC0 |
| 36 | #define AHCI_VEND_PTC 0xC8 |
| 37 | |
| 38 | /* Vendor Specific Register bit definitions */ |
| 39 | #define PAXIC_ADBW_BW64 0x1 |
| 40 | #define PAXIC_MAWIDD (1 << 8) |
| 41 | #define PAXIC_MARIDD (1 << 16) |
| 42 | #define PAXIC_OTL (0x4 << 20) |
| 43 | |
| 44 | #define PCFG_TPSS_VAL (0x32 << 16) |
| 45 | #define PCFG_TPRS_VAL (0x2 << 12) |
| 46 | #define PCFG_PAD_VAL 0x2 |
| 47 | |
| 48 | #define PPCFG_TTA 0x1FFFE |
| 49 | #define PPCFG_PSSO_EN (1 << 28) |
| 50 | #define PPCFG_PSS_EN (1 << 29) |
| 51 | #define PPCFG_ESDF_EN (1 << 31) |
| 52 | |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 53 | #define PP5C_RIT 0x60216 |
| 54 | #define PP5C_RCT (0x7f0 << 20) |
| 55 | |
| 56 | #define PTC_RX_WM_VAL 0x40 |
| 57 | #define PTC_RSVD (1 << 27) |
| 58 | |
| 59 | #define PORT0_BASE 0x100 |
| 60 | #define PORT1_BASE 0x180 |
| 61 | |
| 62 | /* Port Control Register Bit Definitions */ |
Anurag Kumar Vulisha | e8fc8b8 | 2017-08-21 13:17:18 +0200 | [diff] [blame^] | 63 | #define PORT_SCTL_SPD_GEN3 (0x3 << 4) |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 64 | #define PORT_SCTL_SPD_GEN2 (0x2 << 4) |
| 65 | #define PORT_SCTL_SPD_GEN1 (0x1 << 4) |
| 66 | #define PORT_SCTL_IPM (0x3 << 8) |
| 67 | |
| 68 | #define PORT_BASE 0x100 |
| 69 | #define PORT_OFFSET 0x80 |
| 70 | #define NR_PORTS 2 |
| 71 | #define DRV_NAME "ahci-ceva" |
| 72 | #define CEVA_FLAG_BROKEN_GEN2 1 |
| 73 | |
| 74 | struct ceva_ahci_priv { |
| 75 | struct platform_device *ahci_pdev; |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 76 | /* Port Phy2Cfg Register */ |
| 77 | u32 pp2c[NR_PORTS]; |
| 78 | u32 pp3c[NR_PORTS]; |
| 79 | u32 pp4c[NR_PORTS]; |
| 80 | u32 pp5c[NR_PORTS]; |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 81 | int flags; |
| 82 | }; |
| 83 | |
| 84 | static struct ata_port_operations ahci_ceva_ops = { |
| 85 | .inherits = &ahci_platform_ops, |
| 86 | }; |
| 87 | |
| 88 | static const struct ata_port_info ahci_ceva_port_info = { |
| 89 | .flags = AHCI_FLAG_COMMON, |
| 90 | .pio_mask = ATA_PIO4, |
| 91 | .udma_mask = ATA_UDMA6, |
| 92 | .port_ops = &ahci_ceva_ops, |
| 93 | }; |
| 94 | |
| 95 | static void ahci_ceva_setup(struct ahci_host_priv *hpriv) |
| 96 | { |
| 97 | void __iomem *mmio = hpriv->mmio; |
| 98 | struct ceva_ahci_priv *cevapriv = hpriv->plat_data; |
| 99 | u32 tmp; |
| 100 | int i; |
| 101 | |
| 102 | /* |
| 103 | * AXI Data bus width to 64 |
| 104 | * Set Mem Addr Read, Write ID for data transfers |
| 105 | * Transfer limit to 72 DWord |
| 106 | */ |
| 107 | tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; |
| 108 | writel(tmp, mmio + AHCI_VEND_PAXIC); |
| 109 | |
| 110 | /* Set AHCI Enable */ |
| 111 | tmp = readl(mmio + HOST_CTL); |
| 112 | tmp |= HOST_AHCI_EN; |
| 113 | writel(tmp, mmio + HOST_CTL); |
| 114 | |
| 115 | for (i = 0; i < NR_PORTS; i++) { |
| 116 | /* TPSS TPRS scalars, CISE and Port Addr */ |
| 117 | tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); |
| 118 | writel(tmp, mmio + AHCI_VEND_PCFG); |
| 119 | |
| 120 | /* Port Phy Cfg register enables */ |
| 121 | tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; |
| 122 | writel(tmp, mmio + AHCI_VEND_PPCFG); |
| 123 | |
| 124 | /* Phy Control OOB timing parameters COMINIT */ |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 125 | writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 126 | |
| 127 | /* Phy Control OOB timing parameters COMWAKE */ |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 128 | writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 129 | |
| 130 | /* Phy Control Burst timing setting */ |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 131 | writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C); |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 132 | |
| 133 | /* Rate Change Timer and Retry Interval Timer setting */ |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 134 | writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C); |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 135 | |
| 136 | /* Rx Watermark setting */ |
| 137 | tmp = PTC_RX_WM_VAL | PTC_RSVD; |
| 138 | writel(tmp, mmio + AHCI_VEND_PTC); |
| 139 | |
Anurag Kumar Vulisha | e8fc8b8 | 2017-08-21 13:17:18 +0200 | [diff] [blame^] | 140 | /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */ |
| 141 | tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 142 | if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2) |
| 143 | tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM; |
| 144 | writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | static struct scsi_host_template ahci_platform_sht = { |
| 149 | AHCI_SHT(DRV_NAME), |
| 150 | }; |
| 151 | |
| 152 | static int ceva_ahci_probe(struct platform_device *pdev) |
| 153 | { |
| 154 | struct device_node *np = pdev->dev.of_node; |
| 155 | struct device *dev = &pdev->dev; |
| 156 | struct ahci_host_priv *hpriv; |
| 157 | struct ceva_ahci_priv *cevapriv; |
| 158 | int rc; |
| 159 | |
| 160 | cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); |
| 161 | if (!cevapriv) |
| 162 | return -ENOMEM; |
| 163 | |
| 164 | cevapriv->ahci_pdev = pdev; |
| 165 | |
| 166 | hpriv = ahci_platform_get_resources(pdev); |
| 167 | if (IS_ERR(hpriv)) |
| 168 | return PTR_ERR(hpriv); |
| 169 | |
| 170 | rc = ahci_platform_enable_resources(hpriv); |
| 171 | if (rc) |
| 172 | return rc; |
| 173 | |
| 174 | if (of_property_read_bool(np, "ceva,broken-gen2")) |
| 175 | cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; |
| 176 | |
Anurag Kumar Vulisha | fe8365b | 2017-08-21 13:17:17 +0200 | [diff] [blame] | 177 | /* Read OOB timing value for COMINIT from device-tree */ |
| 178 | if (of_property_read_u8_array(np, "ceva,p0-cominit-params", |
| 179 | (u8 *)&cevapriv->pp2c[0], 4) < 0) { |
| 180 | dev_warn(dev, "ceva,p0-cominit-params property not defined\n"); |
| 181 | return -EINVAL; |
| 182 | } |
| 183 | |
| 184 | if (of_property_read_u8_array(np, "ceva,p1-cominit-params", |
| 185 | (u8 *)&cevapriv->pp2c[1], 4) < 0) { |
| 186 | dev_warn(dev, "ceva,p1-cominit-params property not defined\n"); |
| 187 | return -EINVAL; |
| 188 | } |
| 189 | |
| 190 | /* Read OOB timing value for COMWAKE from device-tree*/ |
| 191 | if (of_property_read_u8_array(np, "ceva,p0-comwake-params", |
| 192 | (u8 *)&cevapriv->pp3c[0], 4) < 0) { |
| 193 | dev_warn(dev, "ceva,p0-comwake-params property not defined\n"); |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | if (of_property_read_u8_array(np, "ceva,p1-comwake-params", |
| 198 | (u8 *)&cevapriv->pp3c[1], 4) < 0) { |
| 199 | dev_warn(dev, "ceva,p1-comwake-params property not defined\n"); |
| 200 | return -EINVAL; |
| 201 | } |
| 202 | |
| 203 | /* Read phy BURST timing value from device-tree */ |
| 204 | if (of_property_read_u8_array(np, "ceva,p0-burst-params", |
| 205 | (u8 *)&cevapriv->pp4c[0], 4) < 0) { |
| 206 | dev_warn(dev, "ceva,p0-burst-params property not defined\n"); |
| 207 | return -EINVAL; |
| 208 | } |
| 209 | |
| 210 | if (of_property_read_u8_array(np, "ceva,p1-burst-params", |
| 211 | (u8 *)&cevapriv->pp4c[1], 4) < 0) { |
| 212 | dev_warn(dev, "ceva,p1-burst-params property not defined\n"); |
| 213 | return -EINVAL; |
| 214 | } |
| 215 | |
| 216 | /* Read phy RETRY interval timing value from device-tree */ |
| 217 | if (of_property_read_u16_array(np, "ceva,p0-retry-params", |
| 218 | (u16 *)&cevapriv->pp5c[0], 2) < 0) { |
| 219 | dev_warn(dev, "ceva,p0-retry-params property not defined\n"); |
| 220 | return -EINVAL; |
| 221 | } |
| 222 | |
| 223 | if (of_property_read_u16_array(np, "ceva,p1-retry-params", |
| 224 | (u16 *)&cevapriv->pp5c[1], 2) < 0) { |
| 225 | dev_warn(dev, "ceva,p1-retry-params property not defined\n"); |
| 226 | return -EINVAL; |
| 227 | } |
| 228 | |
Suneel Garapati | a73ed35 | 2015-06-09 14:23:50 +0530 | [diff] [blame] | 229 | hpriv->plat_data = cevapriv; |
| 230 | |
| 231 | /* CEVA specific initialization */ |
| 232 | ahci_ceva_setup(hpriv); |
| 233 | |
| 234 | rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info, |
| 235 | &ahci_platform_sht); |
| 236 | if (rc) |
| 237 | goto disable_resources; |
| 238 | |
| 239 | return 0; |
| 240 | |
| 241 | disable_resources: |
| 242 | ahci_platform_disable_resources(hpriv); |
| 243 | return rc; |
| 244 | } |
| 245 | |
| 246 | static int __maybe_unused ceva_ahci_suspend(struct device *dev) |
| 247 | { |
| 248 | return ahci_platform_suspend_host(dev); |
| 249 | } |
| 250 | |
| 251 | static int __maybe_unused ceva_ahci_resume(struct device *dev) |
| 252 | { |
| 253 | return ahci_platform_resume_host(dev); |
| 254 | } |
| 255 | |
| 256 | static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume); |
| 257 | |
| 258 | static const struct of_device_id ceva_ahci_of_match[] = { |
| 259 | { .compatible = "ceva,ahci-1v84" }, |
| 260 | {}, |
| 261 | }; |
| 262 | MODULE_DEVICE_TABLE(of, ceva_ahci_of_match); |
| 263 | |
| 264 | static struct platform_driver ceva_ahci_driver = { |
| 265 | .probe = ceva_ahci_probe, |
| 266 | .remove = ata_platform_remove_one, |
| 267 | .driver = { |
| 268 | .name = DRV_NAME, |
| 269 | .of_match_table = ceva_ahci_of_match, |
| 270 | .pm = &ahci_ceva_pm_ops, |
| 271 | }, |
| 272 | }; |
| 273 | module_platform_driver(ceva_ahci_driver); |
| 274 | |
| 275 | MODULE_DESCRIPTION("CEVA AHCI SATA platform driver"); |
| 276 | MODULE_AUTHOR("Xilinx Inc."); |
| 277 | MODULE_LICENSE("GPL v2"); |