FUJITA Tomonori | e93be88 | 2008-07-10 08:27:49 +0900 | [diff] [blame^] | 1 | #ifndef _ASM_X8664_GART_H |
| 2 | #define _ASM_X8664_GART_H 1 |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 3 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 4 | #include <asm/e820.h> |
FUJITA Tomonori | e93be88 | 2008-07-10 08:27:49 +0900 | [diff] [blame^] | 5 | #include <asm/iommu.h> |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 6 | |
Rafael J. Wysocki | 6703f6d | 2008-06-10 00:10:48 +0200 | [diff] [blame] | 7 | extern void set_up_gart_resume(u32, u32); |
FUJITA Tomonori | e93be88 | 2008-07-10 08:27:49 +0900 | [diff] [blame^] | 8 | |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 9 | extern int fallback_aper_order; |
| 10 | extern int fallback_aper_force; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 11 | extern int fix_aperture; |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 12 | |
Pavel Machek | aa134f1 | 2008-04-08 10:49:03 +0200 | [diff] [blame] | 13 | /* PTE bits. */ |
| 14 | #define GPTE_VALID 1 |
| 15 | #define GPTE_COHERENT 2 |
| 16 | |
| 17 | /* Aperture control register bits. */ |
| 18 | #define GARTEN (1<<0) |
| 19 | #define DISGARTCPU (1<<4) |
| 20 | #define DISGARTIO (1<<5) |
| 21 | |
| 22 | /* GART cache control register bits. */ |
| 23 | #define INVGART (1<<0) |
| 24 | #define GARTPTEERR (1<<1) |
| 25 | |
| 26 | /* K8 On-cpu GART registers */ |
| 27 | #define AMD64_GARTAPERTURECTL 0x90 |
| 28 | #define AMD64_GARTAPERTUREBASE 0x94 |
| 29 | #define AMD64_GARTTABLEBASE 0x98 |
| 30 | #define AMD64_GARTCACHECTL 0x9c |
| 31 | #define AMD64_GARTEN (1<<0) |
| 32 | |
Pavel Machek | 3bb6fbf | 2008-04-15 12:43:57 +0200 | [diff] [blame] | 33 | static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) |
| 34 | { |
| 35 | u32 tmp, ctl; |
| 36 | |
| 37 | /* address of the mappings table */ |
| 38 | addr >>= 12; |
| 39 | tmp = (u32) addr<<4; |
| 40 | tmp &= ~0xf; |
| 41 | pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); |
| 42 | |
| 43 | /* Enable GART translation for this hammer. */ |
| 44 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
| 45 | ctl |= GARTEN; |
| 46 | ctl &= ~(DISGARTCPU | DISGARTIO); |
| 47 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| 48 | } |
| 49 | |
Pavel Machek | 0abbc78 | 2008-05-20 16:27:17 +0200 | [diff] [blame] | 50 | static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) |
| 51 | { |
| 52 | if (!aper_base) |
| 53 | return 0; |
| 54 | |
| 55 | if (aper_base + aper_size > 0x100000000ULL) { |
| 56 | printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n"); |
| 57 | return 0; |
| 58 | } |
| 59 | if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { |
| 60 | printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n"); |
| 61 | return 0; |
| 62 | } |
| 63 | if (aper_size < min_size) { |
| 64 | printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n", |
| 65 | aper_size>>20, min_size>>20); |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | return 1; |
| 70 | } |
| 71 | |
Joerg Roedel | 395624f | 2007-10-24 12:49:47 +0200 | [diff] [blame] | 72 | #endif |