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gerrit-public.fairphone.software / kernel / msm-4.19 / e945130b52bea65d15f9bdf54949d4cb7a88db7f / . / arch / arc / boot / dts / nsimosci_hs_idu.dts
blob: 5052917d4a99490ea77d2e18cc03b97ce3722f3a [file] [log] [blame]
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Vineet Gupta2e8cd932016-01-19 16:00:42 +0530[diff] [blame]10/include/ "skeleton_hs_idu.dtsi"
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]11
12/ {
Alexey Brodkin618a9cd2016-08-16 07:26:31 +0300[diff] [blame]13 model = "snps,nsimosci_hs-smp";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]14 compatible = "snps,nsimosci_hs";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&core_intc>;
18
19 chosen {
20 /* this is for console on serial */
Alexey Brodkin830c6572016-06-06 10:56:53 +0300[diff] [blame]21 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]22 };
23
24 aliases {
25 serial0 = &uart0;
26 };
27
28 fpga {
29 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 /* child and parent address space 1:1 mapped */
34 ranges;
35
Vineet Guptab3d6aba2016-01-01 18:48:40 +0530[diff] [blame]36 core_clk: core_clk {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <5000000>;
40 };
41
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]42 core_intc: core-interrupt-controller {
43 compatible = "snps,archs-intc";
44 interrupt-controller;
45 #interrupt-cells = <1>;
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]46 };
47
48 idu_intc: idu-interrupt-controller {
49 compatible = "snps,archs-idu-intc";
50 interrupt-controller;
51 interrupt-parent = <&core_intc>;
Yuriy Kolerovec69b262017-02-02 03:13:32 +0300[diff] [blame]52 #interrupt-cells = <1>;
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]53 };
54
55 uart0: serial@f0000000 {
56 compatible = "ns8250";
57 reg = <0xf0000000 0x2000>;
58 interrupt-parent = <&idu_intc>;
Yuriy Kolerovec69b262017-02-02 03:13:32 +0300[diff] [blame]59 interrupts = <0>;
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]60 clock-frequency = <3686400>;
61 baud = <115200>;
62 reg-shift = <2>;
63 reg-io-width = <4>;
64 no-loopback-test = <1>;
65 };
66
Alexey Brodkin830c6572016-06-06 10:56:53 +0300[diff] [blame]67 pguclk: pguclk {
68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <25175000>;
71 };
72
73 pgu@f9000000 {
74 compatible = "snps,arcpgu";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]75 reg = <0xf9000000 0x400>;
Alexey Brodkin830c6572016-06-06 10:56:53 +0300[diff] [blame]76 clocks = <&pguclk>;
77 clock-names = "pxlclk";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]78 };
79
80 ps2: ps2@f9001000 {
81 compatible = "snps,arc_ps2";
82 reg = <0xf9000400 0x14>;
Yuriy Kolerovec69b262017-02-02 03:13:32 +0300[diff] [blame]83 interrupts = <3>;
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]84 interrupt-parent = <&idu_intc>;
85 interrupt-names = "arc_ps2_irq";
86 };
87
88 eth0: ethernet@f0003000 {
Lada Trimasovadf420fd2016-03-14 17:11:57 +0300[diff] [blame]89 compatible = "ezchip,nps-mgt-enet";
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]90 reg = <0xf0003000 0x44>;
91 interrupt-parent = <&idu_intc>;
Yuriy Kolerovec69b262017-02-02 03:13:32 +0300[diff] [blame]92 interrupts = <1>;
Vineet Guptaa12ebe12015-03-09 14:30:19 +0530[diff] [blame]93 };
94
95 arcpct0: pct {
96 compatible = "snps,archs-pct";
97 #interrupt-cells = <1>;
98 interrupts = <20>;
99 };
100 };
101};