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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparded2145cd2011-03-16 08:20:46 +00002 * Copyright (C) 2005 - 2011 Emulex
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
Ajit Khaparded2145cd2011-03-16 08:20:46 +000011 * linux-drivers@emulex.com
Sathya Perla6b7c5b92009-03-11 23:32:03 -070012 *
Ajit Khaparded2145cd2011-03-16 08:20:46 +000013 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
Sathya Perla6b7c5b92009-03-11 23:32:03 -070016 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070023#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
Ajit Khaparde84517482009-09-04 03:12:16 +000030#include <linux/firmware.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Sathya Perlaab1594e2011-07-25 19:10:15 +000032#include <linux/u64_stats_sync.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070033
34#include "be_hw.h"
35
Ajit Khapardec8883852011-03-16 08:21:00 +000036#define DRV_VER "4.0.100u"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070037#define DRV_NAME "be2net"
38#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070039#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
Ajit Khapardec4ca2372009-05-18 15:38:55 -070040#define OC_NAME "Emulex OneConnect 10Gbps NIC"
Sathya Perlafe6d2a32010-11-21 23:25:50 +000041#define OC_NAME_BE OC_NAME "(be3)"
42#define OC_NAME_LANCER OC_NAME "(Lancer)"
Ajit Khaparde35ecf032010-02-09 01:38:06 +000043#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070044
Ajit Khapardec4ca2372009-05-18 15:38:55 -070045#define BE_VENDOR_ID 0x19a2
Sathya Perlafe6d2a32010-11-21 23:25:50 +000046#define EMULEX_VENDOR_ID 0x10df
Ajit Khapardec4ca2372009-05-18 15:38:55 -070047#define BE_DEVICE_ID1 0x211
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070048#define BE_DEVICE_ID2 0x221
Sathya Perlafe6d2a32010-11-21 23:25:50 +000049#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
50#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
51#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +000052#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
Ajit Khapardec4ca2372009-05-18 15:38:55 -070053
54static inline char *nic_name(struct pci_dev *pdev)
55{
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070056 switch (pdev->device) {
57 case OC_DEVICE_ID1:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070058 return OC_NAME;
Ajit Khapardee254f6e2010-02-09 01:28:35 +000059 case OC_DEVICE_ID2:
Sathya Perlafe6d2a32010-11-21 23:25:50 +000060 return OC_NAME_BE;
61 case OC_DEVICE_ID3:
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +000062 case OC_DEVICE_ID4:
Sathya Perlafe6d2a32010-11-21 23:25:50 +000063 return OC_NAME_LANCER;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070064 case BE_DEVICE_ID2:
65 return BE3_NAME;
66 default:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070067 return BE_NAME;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070068 }
Ajit Khapardec4ca2372009-05-18 15:38:55 -070069}
70
Sathya Perla6b7c5b92009-03-11 23:32:03 -070071/* Number of bytes of an RX frame that are copied to skb->data */
Sathya Perla2e588f82011-03-11 02:49:26 +000072#define BE_HDR_LEN ((u16) 64)
Sathya Perla6b7c5b92009-03-11 23:32:03 -070073#define BE_MAX_JUMBO_FRAME_SIZE 9018
74#define BE_MIN_MTU 256
75
76#define BE_NUM_VLANS_SUPPORTED 64
77#define BE_MAX_EQD 96
78#define BE_MAX_TX_FRAG_COUNT 30
79
80#define EVNT_Q_LEN 1024
81#define TX_Q_LEN 2048
82#define TX_CQ_LEN 1024
83#define RX_Q_LEN 1024 /* Does not support any other value */
84#define RX_CQ_LEN 1024
Sathya Perla5fb379e2009-06-18 00:02:59 +000085#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070086#define MCC_CQ_LEN 256
87
Sathya Perla3abcded2010-10-03 22:12:27 -070088#define MAX_RSS_QS 4 /* BE limit is 4 queues/port */
Sathya Perlaac6a0c42011-03-21 20:49:25 +000089#define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
Sathya Perla3c8def92011-06-12 20:01:58 +000090#define MAX_TX_QS 8
Sathya Perlaac6a0c42011-03-21 20:49:25 +000091#define BE_MAX_MSIX_VECTORS (MAX_RX_QS + 1)/* RX + TX */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070092#define BE_NAPI_WEIGHT 64
93#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
94#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
95
Sathya Perla8788fdc2009-07-27 22:52:03 +000096#define FW_VER_LEN 32
97
Sathya Perla6b7c5b92009-03-11 23:32:03 -070098struct be_dma_mem {
99 void *va;
100 dma_addr_t dma;
101 u32 size;
102};
103
104struct be_queue_info {
105 struct be_dma_mem dma_mem;
106 u16 len;
107 u16 entry_size; /* Size of an element in the queue */
108 u16 id;
109 u16 tail, head;
110 bool created;
111 atomic_t used; /* Number of valid elements in the queue */
112};
113
Sathya Perla5fb379e2009-06-18 00:02:59 +0000114static inline u32 MODULO(u16 val, u16 limit)
115{
116 BUG_ON(limit & (limit - 1));
117 return val & (limit - 1);
118}
119
120static inline void index_adv(u16 *index, u16 val, u16 limit)
121{
122 *index = MODULO((*index + val), limit);
123}
124
125static inline void index_inc(u16 *index, u16 limit)
126{
127 *index = MODULO((*index + 1), limit);
128}
129
130static inline void *queue_head_node(struct be_queue_info *q)
131{
132 return q->dma_mem.va + q->head * q->entry_size;
133}
134
135static inline void *queue_tail_node(struct be_queue_info *q)
136{
137 return q->dma_mem.va + q->tail * q->entry_size;
138}
139
140static inline void queue_head_inc(struct be_queue_info *q)
141{
142 index_inc(&q->head, q->len);
143}
144
145static inline void queue_tail_inc(struct be_queue_info *q)
146{
147 index_inc(&q->tail, q->len);
148}
149
Sathya Perla5fb379e2009-06-18 00:02:59 +0000150struct be_eq_obj {
151 struct be_queue_info q;
152 char desc[32];
153
154 /* Adaptive interrupt coalescing (AIC) info */
155 bool enable_aic;
156 u16 min_eqd; /* in usecs */
157 u16 max_eqd; /* in usecs */
158 u16 cur_eqd; /* in usecs */
Padmanabh Ratnakarecd62102011-04-03 01:54:11 +0000159 u8 eq_idx;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000160
161 struct napi_struct napi;
162};
163
164struct be_mcc_obj {
165 struct be_queue_info q;
166 struct be_queue_info cq;
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000167 bool rearm_cq;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000168};
169
Sathya Perla3abcded2010-10-03 22:12:27 -0700170struct be_tx_stats {
Sathya Perlaac124ff2011-07-25 19:10:14 +0000171 u64 tx_bytes;
172 u64 tx_pkts;
173 u64 tx_reqs;
174 u64 tx_wrbs;
175 u64 tx_compl;
176 ulong tx_jiffies;
177 u32 tx_stops;
Sathya Perlaab1594e2011-07-25 19:10:15 +0000178 struct u64_stats_sync sync;
179 struct u64_stats_sync sync_compl;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700180};
181
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700182struct be_tx_obj {
183 struct be_queue_info q;
184 struct be_queue_info cq;
185 /* Remember the skbs that were transmitted */
186 struct sk_buff *sent_skb_list[TX_Q_LEN];
Sathya Perla3c8def92011-06-12 20:01:58 +0000187 struct be_tx_stats stats;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700188};
189
190/* Struct to remember the pages posted for rx frags */
191struct be_rx_page_info {
192 struct page *page;
FUJITA Tomonorifac6da52010-04-01 16:53:22 +0000193 DEFINE_DMA_UNMAP_ADDR(bus);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700194 u16 page_offset;
195 bool last_page_user;
196};
197
Sathya Perla3abcded2010-10-03 22:12:27 -0700198struct be_rx_stats {
Sathya Perla3abcded2010-10-03 22:12:27 -0700199 u64 rx_bytes;
Sathya Perla3abcded2010-10-03 22:12:27 -0700200 u64 rx_pkts;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000201 u64 rx_pkts_prev;
202 ulong rx_jiffies;
203 u32 rx_drops_no_skbs; /* skb allocation errors */
204 u32 rx_drops_no_frags; /* HW has no fetched frags */
205 u32 rx_post_fail; /* page post alloc failures */
206 u32 rx_polls; /* NAPI calls */
207 u32 rx_events;
208 u32 rx_compl;
Sathya Perla3abcded2010-10-03 22:12:27 -0700209 u32 rx_mcast_pkts;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000210 u32 rx_compl_err; /* completions with err set */
211 u32 rx_pps; /* pkts per second */
Sathya Perlaab1594e2011-07-25 19:10:15 +0000212 struct u64_stats_sync sync;
Sathya Perla3abcded2010-10-03 22:12:27 -0700213};
214
Sathya Perla2e588f82011-03-11 02:49:26 +0000215struct be_rx_compl_info {
216 u32 rss_hash;
Somnath Kotur6709d952011-05-04 22:40:46 +0000217 u16 vlan_tag;
Sathya Perla2e588f82011-03-11 02:49:26 +0000218 u16 pkt_size;
219 u16 rxq_idx;
220 u16 mac_id;
221 u8 vlanf;
222 u8 num_rcvd;
223 u8 err;
224 u8 ipf;
225 u8 tcpf;
226 u8 udpf;
227 u8 ip_csum;
228 u8 l4_csum;
229 u8 ipv6;
230 u8 vtm;
231 u8 pkt_type;
232};
233
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700234struct be_rx_obj {
Sathya Perla3abcded2010-10-03 22:12:27 -0700235 struct be_adapter *adapter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700236 struct be_queue_info q;
237 struct be_queue_info cq;
Sathya Perla2e588f82011-03-11 02:49:26 +0000238 struct be_rx_compl_info rxcp;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700239 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
Sathya Perla3abcded2010-10-03 22:12:27 -0700240 struct be_eq_obj rx_eq;
241 struct be_rx_stats stats;
242 u8 rss_id;
243 bool rx_post_starved; /* Zero rx frags have been posted to BE */
Padmanabh Ratnakare80d9da2011-03-07 03:07:58 +0000244 u32 cache_line_barrier[16];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700245};
246
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000247struct be_drv_stats {
248 u8 be_on_die_temperature;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000249 u32 tx_events;
250 u32 eth_red_drops;
251 u32 rx_drops_no_pbuf;
252 u32 rx_drops_no_txpb;
253 u32 rx_drops_no_erx_descr;
254 u32 rx_drops_no_tpre_descr;
255 u32 rx_drops_too_many_frags;
256 u32 rx_drops_invalid_ring;
257 u32 forwarded_packets;
258 u32 rx_drops_mtu;
259 u32 rx_crc_errors;
260 u32 rx_alignment_symbol_errors;
261 u32 rx_pause_frames;
262 u32 rx_priority_pause_frames;
263 u32 rx_control_frames;
264 u32 rx_in_range_errors;
265 u32 rx_out_range_errors;
266 u32 rx_frame_too_long;
267 u32 rx_address_match_errors;
268 u32 rx_dropped_too_small;
269 u32 rx_dropped_too_short;
270 u32 rx_dropped_header_too_small;
271 u32 rx_dropped_tcp_length;
272 u32 rx_dropped_runt;
273 u32 rx_ip_checksum_errs;
274 u32 rx_tcp_checksum_errs;
275 u32 rx_udp_checksum_errs;
276 u32 tx_pauseframes;
277 u32 tx_priority_pauseframes;
278 u32 tx_controlframes;
279 u32 rxpp_fifo_overflow_drop;
280 u32 rx_input_fifo_overflow_drop;
281 u32 pmem_fifo_overflow_drop;
282 u32 jabber_events;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000283};
284
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000285struct be_vf_cfg {
286 unsigned char vf_mac_addr[ETH_ALEN];
287 u32 vf_if_handle;
288 u32 vf_pmac_id;
Ajit Khaparde1da87b72010-07-23 01:51:22 +0000289 u16 vf_vlan_tag;
Ajit Khapardee1d18732010-07-23 01:52:13 +0000290 u32 vf_tx_rate;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000291};
292
Ajit Khaparde9cd90002010-07-23 01:49:04 +0000293#define BE_INVALID_PMAC_ID 0xffffffff
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000294
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700295struct be_adapter {
296 struct pci_dev *pdev;
297 struct net_device *netdev;
298
Sathya Perla8788fdc2009-07-27 22:52:03 +0000299 u8 __iomem *csr;
300 u8 __iomem *db; /* Door Bell */
301 u8 __iomem *pcicfg; /* PCI config space */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000302
Ivan Vecera29849612010-12-14 05:43:19 +0000303 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000304 struct be_dma_mem mbox_mem;
305 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
306 * is stored for freeing purpose */
307 struct be_dma_mem mbox_mem_alloced;
308
309 struct be_mcc_obj mcc_obj;
310 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
311 spinlock_t mcc_cq_lock;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700312
Sathya Perla3abcded2010-10-03 22:12:27 -0700313 struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS];
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000314 u32 num_msix_vec;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700315 bool isr_registered;
316
317 /* TX Rings */
318 struct be_eq_obj tx_eq;
Sathya Perla3c8def92011-06-12 20:01:58 +0000319 struct be_tx_obj tx_obj[MAX_TX_QS];
320 u8 num_tx_qs;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700321
322 u32 cache_line_break[8];
323
324 /* Rx rings */
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000325 struct be_rx_obj rx_obj[MAX_RX_QS];
Sathya Perla3abcded2010-10-03 22:12:27 -0700326 u32 num_rx_qs;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700327 u32 big_page_size; /* Compounded page size shared by rx wrbs */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700328
Padmanabh Ratnakarecd62102011-04-03 01:54:11 +0000329 u8 eq_next_idx;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000330 struct be_drv_stats drv_stats;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000331
Ajit Khaparde82903e42010-02-09 01:34:57 +0000332 u16 vlans_added;
333 u16 max_vlans; /* Number of vlans supported */
Jesse Grossb7381272010-10-20 13:56:02 +0000334 u8 vlan_tag[VLAN_N_VID];
Somnath Koturcc4ce022010-10-21 07:11:14 -0700335 u8 vlan_prio_bmap; /* Available Priority BitMap */
336 u16 recommended_prio; /* Recommended Priority */
Sathya Perlae7b909a2009-11-22 22:01:10 +0000337 struct be_dma_mem mc_cmd_mem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700338
Sathya Perla3abcded2010-10-03 22:12:27 -0700339 struct be_dma_mem stats_cmd;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700340 /* Work queue used to perform periodic tasks like getting statistics */
341 struct delayed_work work;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000342 u16 work_counter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700343
344 /* Ethtool knobs and info */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700345 char fw_ver[FW_VER_LEN];
346 u32 if_handle; /* Used to configure filtering */
347 u32 pmac_id; /* MAC addr handle used by BE card */
stephen hemminger1a642462011-04-04 11:06:40 +0000348 u32 beacon_state; /* for set_phys_id */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700349
Sathya Perlacf588472010-02-14 21:22:01 +0000350 bool eeh_err;
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000351 bool link_up;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700352 u32 port_num;
Sathya Perla24307ee2009-06-18 00:09:25 +0000353 bool promiscuous;
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000354 bool wol;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000355 u32 function_mode;
Sathya Perla3abcded2010-10-03 22:12:27 -0700356 u32 function_caps;
Ajit Khaparde9e90c962009-11-06 02:06:59 +0000357 u32 rx_fc; /* Rx flow control */
358 u32 tx_fc; /* Tx flow control */
Ajit Khaparde7c185272010-07-29 06:16:33 +0000359 bool ue_detected;
Ajit Khapardeb2aebe62011-02-20 11:41:39 +0000360 bool stats_cmd_sent;
Ajit Khaparde0dffc832009-11-29 17:57:46 +0000361 int link_speed;
362 u8 port_type;
Sarveshwar Bandi16c02142009-12-23 04:42:51 +0000363 u8 transceiver;
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000364 u8 autoneg;
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000365 u8 generation; /* BladeEngine ASIC generation */
Sarveshwar Bandidd131e72010-05-25 16:16:32 -0700366 u32 flash_status;
367 struct completion flash_compl;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000368
Sathya Perla2e588f82011-03-11 02:49:26 +0000369 bool be3_native;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000370 bool sriov_enabled;
Ajit Khaparde48f5a192011-04-06 18:08:30 +0000371 struct be_vf_cfg *vf_cfg;
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000372 u8 is_virtfn;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000373 u32 sli_family;
Ajit Khaparde9e1453c2011-02-20 11:42:22 +0000374 u8 hba_port_num;
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000375 u16 pvid;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700376};
377
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000378#define be_physfn(adapter) (!adapter->is_virtfn)
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000379
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000380/* BladeEngine Generation numbers */
381#define BE_GEN2 2
382#define BE_GEN3 3
383
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +0000384#define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \
385 (adapter->pdev->device == OC_DEVICE_ID4))
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000386
Stephen Hemminger0fc0b732009-09-02 01:03:33 -0700387extern const struct ethtool_ops be_ethtool_ops;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700388
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000389#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
Sathya Perla3c8def92011-06-12 20:01:58 +0000390#define tx_stats(txo) (&txo->stats)
Sathya Perla3abcded2010-10-03 22:12:27 -0700391#define rx_stats(rxo) (&rxo->stats)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700392
393#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
394
Sathya Perla3abcded2010-10-03 22:12:27 -0700395#define for_all_rx_queues(adapter, rxo, i) \
396 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
397 i++, rxo++)
398
399/* Just skip the first default non-rss queue */
400#define for_all_rss_queues(adapter, rxo, i) \
401 for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\
402 i++, rxo++)
403
Sathya Perla3c8def92011-06-12 20:01:58 +0000404#define for_all_tx_queues(adapter, txo, i) \
405 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
406 i++, txo++)
407
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700408#define PAGE_SHIFT_4K 12
409#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
410
411/* Returns number of pages spanned by the data starting at the given addr */
412#define PAGES_4K_SPANNED(_address, size) \
413 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
414 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
415
416/* Byte offset into the page corresponding to given address */
417#define OFFSET_IN_PAGE(addr) \
418 ((size_t)(addr) & (PAGE_SIZE_4K-1))
419
420/* Returns bit offset within a DWORD of a bitfield */
421#define AMAP_BIT_OFFSET(_struct, field) \
422 (((size_t)&(((_struct *)0)->field))%32)
423
424/* Returns the bit mask of the field that is NOT shifted into location. */
425static inline u32 amap_mask(u32 bitsize)
426{
427 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
428}
429
430static inline void
431amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
432{
433 u32 *dw = (u32 *) ptr + dw_offset;
434 *dw &= ~(mask << offset);
435 *dw |= (mask & value) << offset;
436}
437
438#define AMAP_SET_BITS(_struct, field, ptr, val) \
439 amap_set(ptr, \
440 offsetof(_struct, field)/32, \
441 amap_mask(sizeof(((_struct *)0)->field)), \
442 AMAP_BIT_OFFSET(_struct, field), \
443 val)
444
445static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
446{
447 u32 *dw = (u32 *) ptr;
448 return mask & (*(dw + dw_offset) >> offset);
449}
450
451#define AMAP_GET_BITS(_struct, field, ptr) \
452 amap_get(ptr, \
453 offsetof(_struct, field)/32, \
454 amap_mask(sizeof(((_struct *)0)->field)), \
455 AMAP_BIT_OFFSET(_struct, field))
456
457#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
458#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
459static inline void swap_dws(void *wrb, int len)
460{
461#ifdef __BIG_ENDIAN
462 u32 *dw = wrb;
463 BUG_ON(len % 4);
464 do {
465 *dw = cpu_to_le32(*dw);
466 dw++;
467 len -= 4;
468 } while (len);
469#endif /* __BIG_ENDIAN */
470}
471
472static inline u8 is_tcp_pkt(struct sk_buff *skb)
473{
474 u8 val = 0;
475
476 if (ip_hdr(skb)->version == 4)
477 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
478 else if (ip_hdr(skb)->version == 6)
479 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
480
481 return val;
482}
483
484static inline u8 is_udp_pkt(struct sk_buff *skb)
485{
486 u8 val = 0;
487
488 if (ip_hdr(skb)->version == 4)
489 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
490 else if (ip_hdr(skb)->version == 6)
491 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
492
493 return val;
494}
495
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000496static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
497{
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000498 u32 sli_intf;
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000499
Ajit Khapardeb0060582011-04-06 18:08:01 +0000500 pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, &sli_intf);
501 adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000502}
503
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000504static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
505{
506 u32 addr;
507
508 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
509
510 mac[5] = (u8)(addr & 0xFF);
511 mac[4] = (u8)((addr >> 8) & 0xFF);
512 mac[3] = (u8)((addr >> 16) & 0xFF);
Ajit Khaparde7a2414a2011-02-11 13:36:18 +0000513 /* Use the OUI from the current MAC address */
514 memcpy(mac, adapter->netdev->dev_addr, 3);
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000515}
516
Ajit Khaparde4b972912011-04-06 18:07:43 +0000517static inline bool be_multi_rxq(const struct be_adapter *adapter)
518{
519 return adapter->num_rx_qs > 1;
520}
521
Sathya Perla8788fdc2009-07-27 22:52:03 +0000522extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000523 u16 num_popped);
Sathya Perlaea172a02011-08-02 19:57:42 +0000524extern void be_link_status_update(struct be_adapter *adapter, u32 link_status);
Ajit Khaparde89a88ab2011-05-16 07:36:18 +0000525extern void be_parse_stats(struct be_adapter *adapter);
Ajit Khaparde84517482009-09-04 03:12:16 +0000526extern int be_load_fw(struct be_adapter *adapter, u8 *func);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700527#endif /* BE_H */