| Daniel Walker | e502c37 | 2010-05-05 06:45:20 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. |
| 2 | * |
| David Brown | 3162aa2 | 2011-02-14 16:15:26 -0800 | [diff] [blame] | 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| Daniel Walker | e502c37 | 2010-05-05 06:45:20 -0700 | [diff] [blame] | 6 | * |
| David Brown | 3162aa2 | 2011-02-14 16:15:26 -0800 | [diff] [blame] | 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| Daniel Walker | e502c37 | 2010-05-05 06:45:20 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H |
| 14 | #define __ASM_ARCH_MSM_IRQS_8XXX_H |
| 15 | |
| 16 | /* MSM ACPU Interrupt Numbers */ |
| 17 | |
| 18 | #define INT_A9_M2A_0 0 |
| 19 | #define INT_A9_M2A_1 1 |
| 20 | #define INT_A9_M2A_2 2 |
| 21 | #define INT_A9_M2A_3 3 |
| 22 | #define INT_A9_M2A_4 4 |
| 23 | #define INT_A9_M2A_5 5 |
| 24 | #define INT_A9_M2A_6 6 |
| 25 | #define INT_GP_TIMER_EXP 7 |
| 26 | #define INT_DEBUG_TIMER_EXP 8 |
| 27 | #define INT_SIRC_0 9 |
| 28 | #define INT_SDC3_0 10 |
| 29 | #define INT_SDC3_1 11 |
| 30 | #define INT_SDC4_0 12 |
| 31 | #define INT_SDC4_1 13 |
| 32 | #define INT_AD6_EXT_VFR 14 |
| 33 | #define INT_USB_OTG 15 |
| 34 | #define INT_MDDI_PRI 16 |
| 35 | #define INT_MDDI_EXT 17 |
| 36 | #define INT_MDDI_CLIENT 18 |
| 37 | #define INT_MDP 19 |
| 38 | #define INT_GRAPHICS 20 |
| 39 | #define INT_ADM_AARM 21 |
| 40 | #define INT_ADSP_A11 22 |
| 41 | #define INT_ADSP_A9_A11 23 |
| 42 | #define INT_SDC1_0 24 |
| 43 | #define INT_SDC1_1 25 |
| 44 | #define INT_SDC2_0 26 |
| 45 | #define INT_SDC2_1 27 |
| 46 | #define INT_KEYSENSE 28 |
| 47 | #define INT_TCHSCRN_SSBI 29 |
| 48 | #define INT_TCHSCRN1 30 |
| 49 | #define INT_TCHSCRN2 31 |
| 50 | |
| 51 | #define INT_TCSR_MPRPH_SC1 (32 + 0) |
| 52 | #define INT_USB_FS2 (32 + 1) |
| 53 | #define INT_PWB_I2C (32 + 2) |
| 54 | #define INT_SOFTRESET (32 + 3) |
| 55 | #define INT_NAND_WR_ER_DONE (32 + 4) |
| 56 | #define INT_NAND_OP_DONE (32 + 5) |
| 57 | #define INT_TCSR_MPRPH_SC2 (32 + 6) |
| 58 | #define INT_OP_PEN (32 + 7) |
| 59 | #define INT_AD_HSSD (32 + 8) |
| 60 | #define INT_ARM11_PM (32 + 9) |
| 61 | #define INT_SDMA_NON_SECURE (32 + 10) |
| 62 | #define INT_TSIF_IRQ (32 + 11) |
| 63 | #define INT_UART1DM_IRQ (32 + 12) |
| 64 | #define INT_UART1DM_RX (32 + 13) |
| 65 | #define INT_SDMA_SECURE (32 + 14) |
| 66 | #define INT_SI2S_SLAVE (32 + 15) |
| 67 | #define INT_SC_I2CPU (32 + 16) |
| 68 | #define INT_SC_DBG_RDTRFULL (32 + 17) |
| 69 | #define INT_SC_DBG_WDTRFULL (32 + 18) |
| 70 | #define INT_SCPLL_CTL_DONE (32 + 19) |
| 71 | #define INT_UART2DM_IRQ (32 + 20) |
| 72 | #define INT_UART2DM_RX (32 + 21) |
| 73 | #define INT_VDC_MEC (32 + 22) |
| 74 | #define INT_VDC_DB (32 + 23) |
| 75 | #define INT_VDC_AXI (32 + 24) |
| 76 | #define INT_VFE (32 + 25) |
| 77 | #define INT_USB_HS (32 + 26) |
| 78 | #define INT_AUDIO_OUT0 (32 + 27) |
| 79 | #define INT_AUDIO_OUT1 (32 + 28) |
| 80 | #define INT_CRYPTO (32 + 29) |
| 81 | #define INT_AD6M_IDLE (32 + 30) |
| 82 | #define INT_SIRC_1 (32 + 31) |
| 83 | |
| 84 | #define NR_GPIO_IRQS 165 |
| 85 | #define NR_MSM_IRQS 64 |
| 86 | #define NR_BOARD_IRQS 64 |
| 87 | |
| 88 | #endif |