Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / ed9b8cefa91695119e634979db6090d0700a21f8 / . / virt / kvm / arm / vgic / vgic-mmio-v3.c
blob: 83a665474610771e59b863497cdfba3603790067 [file] [log] [blame]
Andre Przywaraed9b8ce2015-12-01 14:34:34 +0000[diff] [blame^]1/*
2 * VGICv3 MMIO handling functions
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/irqchip/arm-gic-v3.h>
15#include <linux/kvm.h>
16#include <linux/kvm_host.h>
17#include <kvm/iodev.h>
18#include <kvm/arm_vgic.h>
19
20#include <asm/kvm_emulate.h>
21
22#include "vgic.h"
23#include "vgic-mmio.h"
24
25/*
26 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
27 * redistributors, while SPIs are covered by registers in the distributor
28 * block. Trying to set private IRQs in this block gets ignored.
29 * We take some special care here to fix the calculation of the register
30 * offset.
31 */
32#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
33 { \
34 .reg_offset = off, \
35 .bits_per_irq = bpi, \
36 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
37 .access_flags = acc, \
38 .read = vgic_mmio_read_raz, \
39 .write = vgic_mmio_write_wi, \
40 }, { \
41 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
42 .bits_per_irq = bpi, \
43 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
44 .access_flags = acc, \
45 .read = rd, \
46 .write = wr, \
47 }
48
49static const struct vgic_register_region vgic_v3_dist_registers[] = {
50 REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
51 vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
52 VGIC_ACCESS_32bit),
53 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
54 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
55 VGIC_ACCESS_32bit),
56 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
57 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
58 VGIC_ACCESS_32bit),
59 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
60 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
61 VGIC_ACCESS_32bit),
62 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
63 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
64 VGIC_ACCESS_32bit),
65 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
66 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
67 VGIC_ACCESS_32bit),
68 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
69 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
70 VGIC_ACCESS_32bit),
71 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
72 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
73 VGIC_ACCESS_32bit),
74 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
75 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
76 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
77 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
78 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
79 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
80 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
81 vgic_mmio_read_config, vgic_mmio_write_config, 2,
82 VGIC_ACCESS_32bit),
83 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
84 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
85 VGIC_ACCESS_32bit),
86 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
87 vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
88 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
89 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
90 vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
91 VGIC_ACCESS_32bit),
92};
93
94static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
95 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
96 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
97 VGIC_ACCESS_32bit),
98 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
99 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
100 VGIC_ACCESS_32bit),
101 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
102 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
103 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
104 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
105 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
106 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
107 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
108 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
109 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
110 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
111 vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
112 VGIC_ACCESS_32bit),
113};
114
115static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
116 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
117 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
118 VGIC_ACCESS_32bit),
119 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
120 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
121 VGIC_ACCESS_32bit),
122 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
123 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
124 VGIC_ACCESS_32bit),
125 REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
126 vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
127 VGIC_ACCESS_32bit),
128 REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
129 vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
130 VGIC_ACCESS_32bit),
131 REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
132 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
133 VGIC_ACCESS_32bit),
134 REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
135 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
136 VGIC_ACCESS_32bit),
137 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
138 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
139 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
140 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
141 vgic_mmio_read_config, vgic_mmio_write_config, 8,
142 VGIC_ACCESS_32bit),
143 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
144 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
145 VGIC_ACCESS_32bit),
146 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
147 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
148 VGIC_ACCESS_32bit),
149};
150
151unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
152{
153 dev->regions = vgic_v3_dist_registers;
154 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
155
156 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
157
158 return SZ_64K;
159}
160
161int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
162{
163 int nr_vcpus = atomic_read(&kvm->online_vcpus);
164 struct kvm_vcpu *vcpu;
165 struct vgic_io_device *devices;
166 int c, ret = 0;
167
168 devices = kmalloc(sizeof(struct vgic_io_device) * nr_vcpus * 2,
169 GFP_KERNEL);
170 if (!devices)
171 return -ENOMEM;
172
173 kvm_for_each_vcpu(c, vcpu, kvm) {
174 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
175 gpa_t sgi_base = rd_base + SZ_64K;
176 struct vgic_io_device *rd_dev = &devices[c * 2];
177 struct vgic_io_device *sgi_dev = &devices[c * 2 + 1];
178
179 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
180 rd_dev->base_addr = rd_base;
181 rd_dev->regions = vgic_v3_rdbase_registers;
182 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
183 rd_dev->redist_vcpu = vcpu;
184
185 mutex_lock(&kvm->slots_lock);
186 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
187 SZ_64K, &rd_dev->dev);
188 mutex_unlock(&kvm->slots_lock);
189
190 if (ret)
191 break;
192
193 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
194 sgi_dev->base_addr = sgi_base;
195 sgi_dev->regions = vgic_v3_sgibase_registers;
196 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
197 sgi_dev->redist_vcpu = vcpu;
198
199 mutex_lock(&kvm->slots_lock);
200 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
201 SZ_64K, &sgi_dev->dev);
202 mutex_unlock(&kvm->slots_lock);
203 if (ret) {
204 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
205 &rd_dev->dev);
206 break;
207 }
208 }
209
210 if (ret) {
211 /* The current c failed, so we start with the previous one. */
212 for (c--; c >= 0; c--) {
213 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
214 &devices[c * 2].dev);
215 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
216 &devices[c * 2 + 1].dev);
217 }
218 kfree(devices);
219 } else {
220 kvm->arch.vgic.redist_iodevs = devices;
221 }
222
223 return ret;
224}