blob: d36a62377c098b075b82650de7a900fa5f456be9 [file] [log] [blame]
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8#include <linux/vmalloc.h>
9
10#include "qla_def.h"
11#include "qla_gbl.h"
12
13#include <linux/delay.h>
14
15/* 8044 Flash Read/Write functions */
16uint32_t
17qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
18{
19 return readl((void __iomem *) (ha->nx_pcibase + addr));
20}
21
22void
23qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
24{
25 writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
26}
27
28int
29qla8044_rd_direct(struct scsi_qla_host *vha,
30 const uint32_t crb_reg)
31{
32 struct qla_hw_data *ha = vha->hw;
33
34 if (crb_reg < CRB_REG_INDEX_MAX)
35 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
36 else
37 return QLA_FUNCTION_FAILED;
38}
39
40void
41qla8044_wr_direct(struct scsi_qla_host *vha,
42 const uint32_t crb_reg,
43 const uint32_t value)
44{
45 struct qla_hw_data *ha = vha->hw;
46
47 if (crb_reg < CRB_REG_INDEX_MAX)
48 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
49}
50
51static int
52qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
53{
54 uint32_t val;
55 int ret_val = QLA_SUCCESS;
56 struct qla_hw_data *ha = vha->hw;
57
58 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
59 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
60
61 if (val != addr) {
62 ql_log(ql_log_warn, vha, 0xb087,
63 "%s: Failed to set register window : "
64 "addr written 0x%x, read 0x%x!\n",
65 __func__, addr, val);
66 ret_val = QLA_FUNCTION_FAILED;
67 }
68 return ret_val;
69}
70
71static int
72qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
73{
74 int ret_val = QLA_SUCCESS;
75 struct qla_hw_data *ha = vha->hw;
76
77 ret_val = qla8044_set_win_base(vha, addr);
78 if (!ret_val)
79 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
80 else
81 ql_log(ql_log_warn, vha, 0xb088,
82 "%s: failed read of addr 0x%x!\n", __func__, addr);
83 return ret_val;
84}
85
86static int
87qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
88{
89 int ret_val = QLA_SUCCESS;
90 struct qla_hw_data *ha = vha->hw;
91
92 ret_val = qla8044_set_win_base(vha, addr);
93 if (!ret_val)
94 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
95 else
96 ql_log(ql_log_warn, vha, 0xb089,
97 "%s: failed wrt to addr 0x%x, data 0x%x\n",
98 __func__, addr, data);
99 return ret_val;
100}
101
102/*
103 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
104 *
105 * @ha : Pointer to adapter structure
106 * @raddr : CRB address to read from
107 * @waddr : CRB address to write to
108 *
109 */
110static void
111qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
112 uint32_t raddr, uint32_t waddr)
113{
114 uint32_t value;
115
116 qla8044_rd_reg_indirect(vha, raddr, &value);
117 qla8044_wr_reg_indirect(vha, waddr, value);
118}
119
120/*
121 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
122 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
123 *
124 * @vha : Pointer to adapter structure
125 * @raddr : CRB address to read from
126 * @waddr : CRB address to write to
127 * @p_rmw_hdr : header with shift/or/xor values.
128 *
129 */
130static void
131qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
132 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
133{
134 uint32_t value;
135
136 if (p_rmw_hdr->index_a)
137 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
138 else
139 qla8044_rd_reg_indirect(vha, raddr, &value);
140 value &= p_rmw_hdr->test_mask;
141 value <<= p_rmw_hdr->shl;
142 value >>= p_rmw_hdr->shr;
143 value |= p_rmw_hdr->or_value;
144 value ^= p_rmw_hdr->xor_value;
145 qla8044_wr_reg_indirect(vha, waddr, value);
146 return;
147}
148
149inline void
150qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
151{
152 uint32_t qsnt_state;
153 struct qla_hw_data *ha = vha->hw;
154
155 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
156 qsnt_state |= (1 << ha->portnum);
157 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
158 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
159 __func__, vha->host_no, qsnt_state);
160}
161
162void
163qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
164{
165 uint32_t qsnt_state;
166 struct qla_hw_data *ha = vha->hw;
167
168 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
169 qsnt_state &= ~(1 << ha->portnum);
170 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
171 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
172 __func__, vha->host_no, qsnt_state);
173}
174
175/**
176 *
177 * qla8044_lock_recovery - Recovers the idc_lock.
178 * @ha : Pointer to adapter structure
179 *
180 * Lock Recovery Register
181 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
182 * valid if bits 1..0 are set by driver doing lock recovery.
183 * 1-0 1 - Driver intends to force unlock the IDC lock.
184 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
185 * this field after force unlocking the IDC lock.
186 *
187 * Lock Recovery process
188 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
189 * greater than 0, then wait for the other driver to unlock otherwise
190 * move to the next step.
191 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
192 * register bits 1..0 and also set the function# in bits 5..2.
193 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
194 * Wait for the other driver to perform lock recovery if the function
195 * number in bits 5..2 has changed, otherwise move to the next step.
196 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
197 * leaving your function# in bits 5..2.
198 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
199 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
200 **/
201static int
202qla8044_lock_recovery(struct scsi_qla_host *vha)
203{
204 uint32_t lock = 0, lockid;
205 struct qla_hw_data *ha = vha->hw;
206
207 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
208
209 /* Check for other Recovery in progress, go wait */
210 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
211 return QLA_FUNCTION_FAILED;
212
213 /* Intent to Recover */
214 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
215 (ha->portnum <<
216 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
217 msleep(200);
218
219 /* Check Intent to Recover is advertised */
220 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
221 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
222 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
223 return QLA_FUNCTION_FAILED;
224
225 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
226 , __func__, ha->portnum);
227
228 /* Proceed to Recover */
229 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
230 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
231 PROCEED_TO_RECOVER);
232
233 /* Force Unlock() */
234 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
235 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
236
237 /* Clear bits 0-5 in IDC_RECOVERY register*/
238 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
239
240 /* Get lock() */
241 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
242 if (lock) {
243 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
244 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
245 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
246 return QLA_SUCCESS;
247 } else
248 return QLA_FUNCTION_FAILED;
249}
250
251int
252qla8044_idc_lock(struct qla_hw_data *ha)
253{
254 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
255 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
256 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
257
258 while (status == 0) {
259 /* acquire semaphore5 from PCI HW block */
260 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
261
262 if (status) {
263 /* Increment Counter (8-31) and update func_num (0-7) on
264 * getting a successful lock */
265 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
266 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
267 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
268 break;
269 }
270
271 if (timeout == 0)
272 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
273
274 if (++timeout >=
275 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
276 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
277 func_num = tmo_owner & 0xFF;
278 lock_cnt = tmo_owner >> 8;
279 ql_log(ql_log_warn, vha, 0xb114,
280 "%s: Lock by func %d failed after 2s, lock held "
281 "by func %d, lock count %d, first_owner %d\n",
282 __func__, ha->portnum, func_num, lock_cnt,
283 (first_owner & 0xFF));
284 if (first_owner != tmo_owner) {
285 /* Some other driver got lock,
286 * OR same driver got lock again (counter
287 * value changed), when we were waiting for
288 * lock. Retry for another 2 sec */
289 ql_dbg(ql_dbg_p3p, vha, 0xb115,
290 "%s: %d: IDC lock failed\n",
291 __func__, ha->portnum);
292 timeout = 0;
293 } else {
294 /* Same driver holding lock > 2sec.
295 * Force Recovery */
296 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
297 /* Recovered and got lock */
298 ret_val = QLA_SUCCESS;
299 ql_dbg(ql_dbg_p3p, vha, 0xb116,
300 "%s:IDC lock Recovery by %d"
301 "successful...\n", __func__,
302 ha->portnum);
303 }
304 /* Recovery Failed, some other function
305 * has the lock, wait for 2secs
306 * and retry
307 */
308 ql_dbg(ql_dbg_p3p, vha, 0xb08a,
309 "%s: IDC lock Recovery by %d "
310 "failed, Retrying timout\n", __func__,
311 ha->portnum);
312 timeout = 0;
313 }
314 }
315 msleep(QLA8044_DRV_LOCK_MSLEEP);
316 }
317 return ret_val;
318}
319
320void
321qla8044_idc_unlock(struct qla_hw_data *ha)
322{
323 int id;
324 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
325
326 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
327
328 if ((id & 0xFF) != ha->portnum) {
329 ql_log(ql_log_warn, vha, 0xb118,
330 "%s: IDC Unlock by %d failed, lock owner is %d!\n",
331 __func__, ha->portnum, (id & 0xFF));
332 return;
333 }
334
335 /* Keep lock counter value, update the ha->func_num to 0xFF */
336 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
337 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
338}
339
340/* 8044 Flash Lock/Unlock functions */
341static int
342qla8044_flash_lock(scsi_qla_host_t *vha)
343{
344 int lock_owner;
345 int timeout = 0;
346 uint32_t lock_status = 0;
347 int ret_val = QLA_SUCCESS;
348 struct qla_hw_data *ha = vha->hw;
349
350 while (lock_status == 0) {
351 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
352 if (lock_status)
353 break;
354
355 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
356 lock_owner = qla8044_rd_reg(ha,
357 QLA8044_FLASH_LOCK_ID);
358 ql_log(ql_log_warn, vha, 0xb113,
359 "%s: flash lock by %d failed, held by %d\n",
360 __func__, ha->portnum, lock_owner);
361 ret_val = QLA_FUNCTION_FAILED;
362 break;
363 }
364 msleep(20);
365 }
366 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
367 return ret_val;
368}
369
370static void
371qla8044_flash_unlock(scsi_qla_host_t *vha)
372{
373 int ret_val;
374 struct qla_hw_data *ha = vha->hw;
375
376 /* Reading FLASH_UNLOCK register unlocks the Flash */
377 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
378 ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
379}
380
381
382static
383void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
384{
385
386 if (qla8044_flash_lock(vha)) {
387 /* Someone else is holding the lock. */
388 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
389 }
390
391 /*
392 * Either we got the lock, or someone
393 * else died while holding it.
394 * In either case, unlock.
395 */
396 qla8044_flash_unlock(vha);
397}
398
399/*
400 * Address and length are byte address
401 */
402static int
403qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
404 uint32_t flash_addr, int u32_word_count)
405{
406 int i, ret_val = QLA_SUCCESS;
407 uint32_t u32_word;
408
409 if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
410 ret_val = QLA_FUNCTION_FAILED;
411 goto exit_lock_error;
412 }
413
414 if (flash_addr & 0x03) {
415 ql_log(ql_log_warn, vha, 0xb117,
416 "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
417 ret_val = QLA_FUNCTION_FAILED;
418 goto exit_flash_read;
419 }
420
421 for (i = 0; i < u32_word_count; i++) {
422 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
423 (flash_addr & 0xFFFF0000))) {
424 ql_log(ql_log_warn, vha, 0xb119,
425 "%s: failed to write addr 0x%x to "
426 "FLASH_DIRECT_WINDOW\n! ",
427 __func__, flash_addr);
428 ret_val = QLA_FUNCTION_FAILED;
429 goto exit_flash_read;
430 }
431
432 ret_val = qla8044_rd_reg_indirect(vha,
433 QLA8044_FLASH_DIRECT_DATA(flash_addr),
434 &u32_word);
435 if (ret_val != QLA_SUCCESS) {
436 ql_log(ql_log_warn, vha, 0xb08c,
437 "%s: failed to read addr 0x%x!\n",
438 __func__, flash_addr);
439 goto exit_flash_read;
440 }
441
442 *(uint32_t *)p_data = u32_word;
443 p_data = p_data + 4;
444 flash_addr = flash_addr + 4;
445 }
446
447exit_flash_read:
448 qla8044_flash_unlock(vha);
449
450exit_lock_error:
451 return ret_val;
452}
453
454/*
455 * Address and length are byte address
456 */
457uint8_t *
458qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
459 uint32_t offset, uint32_t length)
460{
461 scsi_block_requests(vha->host);
462 if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
463 != QLA_SUCCESS) {
464 ql_log(ql_log_warn, vha, 0xb08d,
465 "%s: Failed to read from flash\n",
466 __func__);
467 }
468 scsi_unblock_requests(vha->host);
469 return buf;
470}
471
472inline int
473qla8044_need_reset(struct scsi_qla_host *vha)
474{
475 uint32_t drv_state, drv_active;
476 int rval;
477 struct qla_hw_data *ha = vha->hw;
478
479 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
480 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
481
482 rval = drv_state & (1 << ha->portnum);
483
484 if (ha->flags.eeh_busy && drv_active)
485 rval = 1;
486 return rval;
487}
488
489/*
490 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
491 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
492 * entries.
493 *
494 * @vha : Pointer to adapter structure
495 * @p_hdr : reset_entry header for WRITE_LIST opcode.
496 *
497 */
498static void
499qla8044_write_list(struct scsi_qla_host *vha,
500 struct qla8044_reset_entry_hdr *p_hdr)
501{
502 struct qla8044_entry *p_entry;
503 uint32_t i;
504
505 p_entry = (struct qla8044_entry *)((char *)p_hdr +
506 sizeof(struct qla8044_reset_entry_hdr));
507
508 for (i = 0; i < p_hdr->count; i++, p_entry++) {
509 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
510 if (p_hdr->delay)
511 udelay((uint32_t)(p_hdr->delay));
512 }
513}
514
515/*
516 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
517 * write value read to address specified by p_entry->arg2, for all entries in
518 * header with delay of p_hdr->delay between entries.
519 *
520 * @vha : Pointer to adapter structure
521 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
522 *
523 */
524static void
525qla8044_read_write_list(struct scsi_qla_host *vha,
526 struct qla8044_reset_entry_hdr *p_hdr)
527{
528 struct qla8044_entry *p_entry;
529 uint32_t i;
530
531 p_entry = (struct qla8044_entry *)((char *)p_hdr +
532 sizeof(struct qla8044_reset_entry_hdr));
533
534 for (i = 0; i < p_hdr->count; i++, p_entry++) {
535 qla8044_read_write_crb_reg(vha, p_entry->arg1,
536 p_entry->arg2);
537 if (p_hdr->delay)
538 udelay((uint32_t)(p_hdr->delay));
539 }
540}
541
542/*
543 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
544 * value read ANDed with test_mask is equal to test_result.
545 *
546 * @ha : Pointer to adapter structure
547 * @addr : CRB register address
548 * @duration : Poll for total of "duration" msecs
549 * @test_mask : Mask value read with "test_mask"
550 * @test_result : Compare (value&test_mask) with test_result.
551 *
552 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
553 */
554static int
555qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
556 int duration, uint32_t test_mask, uint32_t test_result)
557{
558 uint32_t value;
559 int timeout_error;
560 uint8_t retries;
561 int ret_val = QLA_SUCCESS;
562
563 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
564 if (ret_val == QLA_FUNCTION_FAILED) {
565 timeout_error = 1;
566 goto exit_poll_reg;
567 }
568
569 /* poll every 1/10 of the total duration */
570 retries = duration/10;
571
572 do {
573 if ((value & test_mask) != test_result) {
574 timeout_error = 1;
575 msleep(duration/10);
576 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
577 if (ret_val == QLA_FUNCTION_FAILED) {
578 timeout_error = 1;
579 goto exit_poll_reg;
580 }
581 } else {
582 timeout_error = 0;
583 break;
584 }
585 } while (retries--);
586
587exit_poll_reg:
588 if (timeout_error) {
589 vha->reset_tmplt.seq_error++;
590 ql_log(ql_log_fatal, vha, 0xb090,
591 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
592 __func__, value, test_mask, test_result);
593 }
594
595 return timeout_error;
596}
597
598/*
599 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
600 * register specified by p_entry->arg1 and compare (value AND test_mask) with
601 * test_result to validate it. Wait for p_hdr->delay between processing entries.
602 *
603 * @ha : Pointer to adapter structure
604 * @p_hdr : reset_entry header for POLL_LIST opcode.
605 *
606 */
607static void
608qla8044_poll_list(struct scsi_qla_host *vha,
609 struct qla8044_reset_entry_hdr *p_hdr)
610{
611 long delay;
612 struct qla8044_entry *p_entry;
613 struct qla8044_poll *p_poll;
614 uint32_t i;
615 uint32_t value;
616
617 p_poll = (struct qla8044_poll *)
618 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
619
620 /* Entries start after 8 byte qla8044_poll, poll header contains
621 * the test_mask, test_value.
622 */
623 p_entry = (struct qla8044_entry *)((char *)p_poll +
624 sizeof(struct qla8044_poll));
625
626 delay = (long)p_hdr->delay;
627
628 if (!delay) {
629 for (i = 0; i < p_hdr->count; i++, p_entry++)
630 qla8044_poll_reg(vha, p_entry->arg1,
631 delay, p_poll->test_mask, p_poll->test_value);
632 } else {
633 for (i = 0; i < p_hdr->count; i++, p_entry++) {
634 if (delay) {
635 if (qla8044_poll_reg(vha,
636 p_entry->arg1, delay,
637 p_poll->test_mask,
638 p_poll->test_value)) {
639 /*If
640 * (data_read&test_mask != test_value)
641 * read TIMEOUT_ADDR (arg1) and
642 * ADDR (arg2) registers
643 */
644 qla8044_rd_reg_indirect(vha,
645 p_entry->arg1, &value);
646 qla8044_rd_reg_indirect(vha,
647 p_entry->arg2, &value);
648 }
649 }
650 }
651 }
652}
653
654/*
655 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
656 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
657 * expires.
658 *
659 * @vha : Pointer to adapter structure
660 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
661 *
662 */
663static void
664qla8044_poll_write_list(struct scsi_qla_host *vha,
665 struct qla8044_reset_entry_hdr *p_hdr)
666{
667 long delay;
668 struct qla8044_quad_entry *p_entry;
669 struct qla8044_poll *p_poll;
670 uint32_t i;
671
672 p_poll = (struct qla8044_poll *)((char *)p_hdr +
673 sizeof(struct qla8044_reset_entry_hdr));
674
675 p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
676 sizeof(struct qla8044_poll));
677
678 delay = (long)p_hdr->delay;
679
680 for (i = 0; i < p_hdr->count; i++, p_entry++) {
681 qla8044_wr_reg_indirect(vha,
682 p_entry->dr_addr, p_entry->dr_value);
683 qla8044_wr_reg_indirect(vha,
684 p_entry->ar_addr, p_entry->ar_value);
685 if (delay) {
686 if (qla8044_poll_reg(vha,
687 p_entry->ar_addr, delay,
688 p_poll->test_mask,
689 p_poll->test_value)) {
690 ql_dbg(ql_dbg_p3p, vha, 0xb091,
691 "%s: Timeout Error: poll list, ",
692 __func__);
693 ql_dbg(ql_dbg_p3p, vha, 0xb092,
694 "item_num %d, entry_num %d\n", i,
695 vha->reset_tmplt.seq_index);
696 }
697 }
698 }
699}
700
701/*
702 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
703 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
704 * between entries.
705 *
706 * @vha : Pointer to adapter structure
707 * @p_hdr : header with shift/or/xor values.
708 *
709 */
710static void
711qla8044_read_modify_write(struct scsi_qla_host *vha,
712 struct qla8044_reset_entry_hdr *p_hdr)
713{
714 struct qla8044_entry *p_entry;
715 struct qla8044_rmw *p_rmw_hdr;
716 uint32_t i;
717
718 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
719 sizeof(struct qla8044_reset_entry_hdr));
720
721 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
722 sizeof(struct qla8044_rmw));
723
724 for (i = 0; i < p_hdr->count; i++, p_entry++) {
725 qla8044_rmw_crb_reg(vha, p_entry->arg1,
726 p_entry->arg2, p_rmw_hdr);
727 if (p_hdr->delay)
728 udelay((uint32_t)(p_hdr->delay));
729 }
730}
731
732/*
733 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
734 * two entries of a sequence.
735 *
736 * @vha : Pointer to adapter structure
737 * @p_hdr : Common reset entry header.
738 *
739 */
740static
741void qla8044_pause(struct scsi_qla_host *vha,
742 struct qla8044_reset_entry_hdr *p_hdr)
743{
744 if (p_hdr->delay)
745 mdelay((uint32_t)((long)p_hdr->delay));
746}
747
748/*
749 * qla8044_template_end - Indicates end of reset sequence processing.
750 *
751 * @vha : Pointer to adapter structure
752 * @p_hdr : Common reset entry header.
753 *
754 */
755static void
756qla8044_template_end(struct scsi_qla_host *vha,
757 struct qla8044_reset_entry_hdr *p_hdr)
758{
759 vha->reset_tmplt.template_end = 1;
760
761 if (vha->reset_tmplt.seq_error == 0) {
762 ql_dbg(ql_dbg_p3p, vha, 0xb093,
763 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
764 } else {
765 ql_log(ql_log_fatal, vha, 0xb094,
766 "%s: Reset sequence completed with some timeout "
767 "errors.\n", __func__);
768 }
769}
770
771/*
772 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
773 * if (value & test_mask != test_value) re-read till timeout value expires,
774 * read dr_addr register and assign to reset_tmplt.array.
775 *
776 * @vha : Pointer to adapter structure
777 * @p_hdr : Common reset entry header.
778 *
779 */
780static void
781qla8044_poll_read_list(struct scsi_qla_host *vha,
782 struct qla8044_reset_entry_hdr *p_hdr)
783{
784 long delay;
785 int index;
786 struct qla8044_quad_entry *p_entry;
787 struct qla8044_poll *p_poll;
788 uint32_t i;
789 uint32_t value;
790
791 p_poll = (struct qla8044_poll *)
792 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
793
794 p_entry = (struct qla8044_quad_entry *)
795 ((char *)p_poll + sizeof(struct qla8044_poll));
796
797 delay = (long)p_hdr->delay;
798
799 for (i = 0; i < p_hdr->count; i++, p_entry++) {
800 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
801 p_entry->ar_value);
802 if (delay) {
803 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
804 p_poll->test_mask, p_poll->test_value)) {
805 ql_dbg(ql_dbg_p3p, vha, 0xb095,
806 "%s: Timeout Error: poll "
807 "list, ", __func__);
808 ql_dbg(ql_dbg_p3p, vha, 0xb096,
809 "Item_num %d, "
810 "entry_num %d\n", i,
811 vha->reset_tmplt.seq_index);
812 } else {
813 index = vha->reset_tmplt.array_index;
814 qla8044_rd_reg_indirect(vha,
815 p_entry->dr_addr, &value);
816 vha->reset_tmplt.array[index++] = value;
817 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
818 vha->reset_tmplt.array_index = 1;
819 }
820 }
821 }
822}
823
824/*
825 * qla8031_process_reset_template - Process all entries in reset template
826 * till entry with SEQ_END opcode, which indicates end of the reset template
827 * processing. Each entry has a Reset Entry header, entry opcode/command, with
828 * size of the entry, number of entries in sub-sequence and delay in microsecs
829 * or timeout in millisecs.
830 *
831 * @ha : Pointer to adapter structure
832 * @p_buff : Common reset entry header.
833 *
834 */
835static void
836qla8044_process_reset_template(struct scsi_qla_host *vha,
837 char *p_buff)
838{
839 int index, entries;
840 struct qla8044_reset_entry_hdr *p_hdr;
841 char *p_entry = p_buff;
842
843 vha->reset_tmplt.seq_end = 0;
844 vha->reset_tmplt.template_end = 0;
845 entries = vha->reset_tmplt.hdr->entries;
846 index = vha->reset_tmplt.seq_index;
847
848 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
849 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
850 switch (p_hdr->cmd) {
851 case OPCODE_NOP:
852 break;
853 case OPCODE_WRITE_LIST:
854 qla8044_write_list(vha, p_hdr);
855 break;
856 case OPCODE_READ_WRITE_LIST:
857 qla8044_read_write_list(vha, p_hdr);
858 break;
859 case OPCODE_POLL_LIST:
860 qla8044_poll_list(vha, p_hdr);
861 break;
862 case OPCODE_POLL_WRITE_LIST:
863 qla8044_poll_write_list(vha, p_hdr);
864 break;
865 case OPCODE_READ_MODIFY_WRITE:
866 qla8044_read_modify_write(vha, p_hdr);
867 break;
868 case OPCODE_SEQ_PAUSE:
869 qla8044_pause(vha, p_hdr);
870 break;
871 case OPCODE_SEQ_END:
872 vha->reset_tmplt.seq_end = 1;
873 break;
874 case OPCODE_TMPL_END:
875 qla8044_template_end(vha, p_hdr);
876 break;
877 case OPCODE_POLL_READ_LIST:
878 qla8044_poll_read_list(vha, p_hdr);
879 break;
880 default:
881 ql_log(ql_log_fatal, vha, 0xb097,
882 "%s: Unknown command ==> 0x%04x on "
883 "entry = %d\n", __func__, p_hdr->cmd, index);
884 break;
885 }
886 /*
887 *Set pointer to next entry in the sequence.
888 */
889 p_entry += p_hdr->size;
890 }
891 vha->reset_tmplt.seq_index = index;
892}
893
894static void
895qla8044_process_init_seq(struct scsi_qla_host *vha)
896{
897 qla8044_process_reset_template(vha,
898 vha->reset_tmplt.init_offset);
899 if (vha->reset_tmplt.seq_end != 1)
900 ql_log(ql_log_fatal, vha, 0xb098,
901 "%s: Abrupt INIT Sub-Sequence end.\n",
902 __func__);
903}
904
905static void
906qla8044_process_stop_seq(struct scsi_qla_host *vha)
907{
908 vha->reset_tmplt.seq_index = 0;
909 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
910 if (vha->reset_tmplt.seq_end != 1)
911 ql_log(ql_log_fatal, vha, 0xb099,
912 "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
913}
914
915static void
916qla8044_process_start_seq(struct scsi_qla_host *vha)
917{
918 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
919 if (vha->reset_tmplt.template_end != 1)
920 ql_log(ql_log_fatal, vha, 0xb09a,
921 "%s: Abrupt START Sub-Sequence end.\n",
922 __func__);
923}
924
925static int
926qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
927 uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
928{
929 uint32_t i;
930 uint32_t u32_word;
931 uint32_t flash_offset;
932 uint32_t addr = flash_addr;
933 int ret_val = QLA_SUCCESS;
934
935 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
936
937 if (addr & 0x3) {
938 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
939 __func__, addr);
940 ret_val = QLA_FUNCTION_FAILED;
941 goto exit_lockless_read;
942 }
943
944 ret_val = qla8044_wr_reg_indirect(vha,
945 QLA8044_FLASH_DIRECT_WINDOW, (addr));
946
947 if (ret_val != QLA_SUCCESS) {
948 ql_log(ql_log_fatal, vha, 0xb09c,
949 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
950 __func__, addr);
951 goto exit_lockless_read;
952 }
953
954 /* Check if data is spread across multiple sectors */
955 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
956 (QLA8044_FLASH_SECTOR_SIZE - 1)) {
957 /* Multi sector read */
958 for (i = 0; i < u32_word_count; i++) {
959 ret_val = qla8044_rd_reg_indirect(vha,
960 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
961 if (ret_val != QLA_SUCCESS) {
962 ql_log(ql_log_fatal, vha, 0xb09d,
963 "%s: failed to read addr 0x%x!\n",
964 __func__, addr);
965 goto exit_lockless_read;
966 }
967 *(uint32_t *)p_data = u32_word;
968 p_data = p_data + 4;
969 addr = addr + 4;
970 flash_offset = flash_offset + 4;
971 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
972 /* This write is needed once for each sector */
973 ret_val = qla8044_wr_reg_indirect(vha,
974 QLA8044_FLASH_DIRECT_WINDOW, (addr));
975 if (ret_val != QLA_SUCCESS) {
976 ql_log(ql_log_fatal, vha, 0xb09f,
977 "%s: failed to write addr "
978 "0x%x to FLASH_DIRECT_WINDOW!\n",
979 __func__, addr);
980 goto exit_lockless_read;
981 }
982 flash_offset = 0;
983 }
984 }
985 } else {
986 /* Single sector read */
987 for (i = 0; i < u32_word_count; i++) {
988 ret_val = qla8044_rd_reg_indirect(vha,
989 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
990 if (ret_val != QLA_SUCCESS) {
991 ql_log(ql_log_fatal, vha, 0xb0a0,
992 "%s: failed to read addr 0x%x!\n",
993 __func__, addr);
994 goto exit_lockless_read;
995 }
996 *(uint32_t *)p_data = u32_word;
997 p_data = p_data + 4;
998 addr = addr + 4;
999 }
1000 }
1001
1002exit_lockless_read:
1003 return ret_val;
1004}
1005
1006/*
1007 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1008 *
1009 * @vha : Pointer to adapter structure
1010 * addr : Flash address to write to
1011 * data : Data to be written
1012 * count : word_count to be written
1013 *
1014 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1015 */
1016static int
1017qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1018 uint64_t addr, uint32_t *data, uint32_t count)
1019{
1020 int i, j, ret_val = QLA_SUCCESS;
1021 uint32_t agt_ctrl;
1022 unsigned long flags;
1023 struct qla_hw_data *ha = vha->hw;
1024
1025 /* Only 128-bit aligned access */
1026 if (addr & 0xF) {
1027 ret_val = QLA_FUNCTION_FAILED;
1028 goto exit_ms_mem_write;
1029 }
1030 write_lock_irqsave(&ha->hw_lock, flags);
1031
1032 /* Write address */
1033 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1034 if (ret_val == QLA_FUNCTION_FAILED) {
1035 ql_log(ql_log_fatal, vha, 0xb0a1,
1036 "%s: write to AGT_ADDR_HI failed!\n", __func__);
1037 goto exit_ms_mem_write_unlock;
1038 }
1039
1040 for (i = 0; i < count; i++, addr += 16) {
1041 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1042 QLA8044_ADDR_QDR_NET_MAX)) ||
1043 (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1044 QLA8044_ADDR_DDR_NET_MAX)))) {
1045 ret_val = QLA_FUNCTION_FAILED;
1046 goto exit_ms_mem_write_unlock;
1047 }
1048
1049 ret_val = qla8044_wr_reg_indirect(vha,
1050 MD_MIU_TEST_AGT_ADDR_LO, addr);
1051
1052 /* Write data */
1053 ret_val += qla8044_wr_reg_indirect(vha,
1054 MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1055 ret_val += qla8044_wr_reg_indirect(vha,
1056 MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1057 ret_val += qla8044_wr_reg_indirect(vha,
1058 MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1059 ret_val += qla8044_wr_reg_indirect(vha,
1060 MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1061 if (ret_val == QLA_FUNCTION_FAILED) {
1062 ql_log(ql_log_fatal, vha, 0xb0a2,
1063 "%s: write to AGT_WRDATA failed!\n",
1064 __func__);
1065 goto exit_ms_mem_write_unlock;
1066 }
1067
1068 /* Check write status */
1069 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1070 MIU_TA_CTL_WRITE_ENABLE);
1071 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1072 MIU_TA_CTL_WRITE_START);
1073 if (ret_val == QLA_FUNCTION_FAILED) {
1074 ql_log(ql_log_fatal, vha, 0xb0a3,
1075 "%s: write to AGT_CTRL failed!\n", __func__);
1076 goto exit_ms_mem_write_unlock;
1077 }
1078
1079 for (j = 0; j < MAX_CTL_CHECK; j++) {
1080 ret_val = qla8044_rd_reg_indirect(vha,
1081 MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1082 if (ret_val == QLA_FUNCTION_FAILED) {
1083 ql_log(ql_log_fatal, vha, 0xb0a4,
1084 "%s: failed to read "
1085 "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1086 goto exit_ms_mem_write_unlock;
1087 }
1088 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1089 break;
1090 }
1091
1092 /* Status check failed */
1093 if (j >= MAX_CTL_CHECK) {
1094 ql_log(ql_log_fatal, vha, 0xb0a5,
1095 "%s: MS memory write failed!\n",
1096 __func__);
1097 ret_val = QLA_FUNCTION_FAILED;
1098 goto exit_ms_mem_write_unlock;
1099 }
1100 }
1101
1102exit_ms_mem_write_unlock:
1103 write_unlock_irqrestore(&ha->hw_lock, flags);
1104
1105exit_ms_mem_write:
1106 return ret_val;
1107}
1108
1109static int
1110qla8044_copy_bootloader(struct scsi_qla_host *vha)
1111{
1112 uint8_t *p_cache;
1113 uint32_t src, count, size;
1114 uint64_t dest;
1115 int ret_val = QLA_SUCCESS;
1116 struct qla_hw_data *ha = vha->hw;
1117
1118 src = QLA8044_BOOTLOADER_FLASH_ADDR;
1119 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1120 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1121
1122 /* 128 bit alignment check */
1123 if (size & 0xF)
1124 size = (size + 16) & ~0xF;
1125
1126 /* 16 byte count */
1127 count = size/16;
1128
1129 p_cache = vmalloc(size);
1130 if (p_cache == NULL) {
1131 ql_log(ql_log_fatal, vha, 0xb0a6,
1132 "%s: Failed to allocate memory for "
1133 "boot loader cache\n", __func__);
1134 ret_val = QLA_FUNCTION_FAILED;
1135 goto exit_copy_bootloader;
1136 }
1137
1138 ret_val = qla8044_lockless_flash_read_u32(vha, src,
1139 p_cache, size/sizeof(uint32_t));
1140 if (ret_val == QLA_FUNCTION_FAILED) {
1141 ql_log(ql_log_fatal, vha, 0xb0a7,
1142 "%s: Error reading F/W from flash!!!\n", __func__);
1143 goto exit_copy_error;
1144 }
1145 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1146 __func__);
1147
1148 /* 128 bit/16 byte write to MS memory */
1149 ret_val = qla8044_ms_mem_write_128b(vha, dest,
1150 (uint32_t *)p_cache, count);
1151 if (ret_val == QLA_FUNCTION_FAILED) {
1152 ql_log(ql_log_fatal, vha, 0xb0a9,
1153 "%s: Error writing F/W to MS !!!\n", __func__);
1154 goto exit_copy_error;
1155 }
1156 ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1157 "%s: Wrote F/W (size %d) to MS !!!\n",
1158 __func__, size);
1159
1160exit_copy_error:
1161 vfree(p_cache);
1162
1163exit_copy_bootloader:
1164 return ret_val;
1165}
1166
1167static int
1168qla8044_restart(struct scsi_qla_host *vha)
1169{
1170 int ret_val = QLA_SUCCESS;
1171 struct qla_hw_data *ha = vha->hw;
1172
1173 qla8044_process_stop_seq(vha);
1174
1175 /* Collect minidump */
1176 if (ql2xmdenable)
1177 qla8044_get_minidump(vha);
1178 else
1179 ql_log(ql_log_fatal, vha, 0xb14c,
1180 "Minidump disabled.\n");
1181
1182 qla8044_process_init_seq(vha);
1183
1184 if (qla8044_copy_bootloader(vha)) {
1185 ql_log(ql_log_fatal, vha, 0xb0ab,
1186 "%s: Copy bootloader, firmware restart failed!\n",
1187 __func__);
1188 ret_val = QLA_FUNCTION_FAILED;
1189 goto exit_restart;
1190 }
1191
1192 /*
1193 * Loads F/W from flash
1194 */
1195 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1196
1197 qla8044_process_start_seq(vha);
1198
1199exit_restart:
1200 return ret_val;
1201}
1202
1203/*
1204 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1205 * initialized.
1206 *
1207 * @ha : Pointer to adapter structure
1208 *
1209 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1210 */
1211static int
1212qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1213{
1214 uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1215 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1216 struct qla_hw_data *ha = vha->hw;
1217
1218 do {
1219 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1220 if (val == PHAN_INITIALIZE_COMPLETE) {
1221 ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1222 "%s: Command Peg initialization "
1223 "complete! state=0x%x\n", __func__, val);
1224 ret_val = QLA_SUCCESS;
1225 break;
1226 }
1227 msleep(CRB_CMDPEG_CHECK_DELAY);
1228 } while (--retries);
1229
1230 return ret_val;
1231}
1232
1233static int
1234qla8044_start_firmware(struct scsi_qla_host *vha)
1235{
1236 int ret_val = QLA_SUCCESS;
1237
1238 if (qla8044_restart(vha)) {
1239 ql_log(ql_log_fatal, vha, 0xb0ad,
1240 "%s: Restart Error!!!, Need Reset!!!\n",
1241 __func__);
1242 ret_val = QLA_FUNCTION_FAILED;
1243 goto exit_start_fw;
1244 } else
1245 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1246 "%s: Restart done!\n", __func__);
1247
1248 ret_val = qla8044_check_cmd_peg_status(vha);
1249 if (ret_val) {
1250 ql_log(ql_log_fatal, vha, 0xb0b0,
1251 "%s: Peg not initialized!\n", __func__);
1252 ret_val = QLA_FUNCTION_FAILED;
1253 }
1254
1255exit_start_fw:
1256 return ret_val;
1257}
1258
1259void
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001260qla8044_clear_drv_active(struct qla_hw_data *ha)
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001261{
1262 uint32_t drv_active;
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001263 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001264
1265 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1266 drv_active &= ~(1 << (ha->portnum));
1267
1268 ql_log(ql_log_info, vha, 0xb0b1,
1269 "%s(%ld): drv_active: 0x%08x\n",
1270 __func__, vha->host_no, drv_active);
1271
1272 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1273}
1274
1275/*
1276 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1277 * @ha: pointer to adapter structure
1278 *
1279 * Note: IDC lock must be held upon entry
1280 **/
1281static int
1282qla8044_device_bootstrap(struct scsi_qla_host *vha)
1283{
1284 int rval = QLA_FUNCTION_FAILED;
1285 int i;
1286 uint32_t old_count = 0, count = 0;
1287 int need_reset = 0;
1288 uint32_t idc_ctrl;
1289 struct qla_hw_data *ha = vha->hw;
1290
1291 need_reset = qla8044_need_reset(vha);
1292
1293 if (!need_reset) {
1294 old_count = qla8044_rd_direct(vha,
1295 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1296
1297 for (i = 0; i < 10; i++) {
1298 msleep(200);
1299
1300 count = qla8044_rd_direct(vha,
1301 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1302 if (count != old_count) {
1303 rval = QLA_SUCCESS;
1304 goto dev_ready;
1305 }
1306 }
1307 qla8044_flash_lock_recovery(vha);
1308 } else {
1309 /* We are trying to perform a recovery here. */
1310 if (ha->flags.isp82xx_fw_hung)
1311 qla8044_flash_lock_recovery(vha);
1312 }
1313
1314 /* set to DEV_INITIALIZING */
1315 ql_log(ql_log_info, vha, 0xb0b2,
1316 "%s: HW State: INITIALIZING\n", __func__);
1317 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1318 QLA8XXX_DEV_INITIALIZING);
1319
1320 qla8044_idc_unlock(ha);
1321 rval = qla8044_start_firmware(vha);
1322 qla8044_idc_lock(ha);
1323
1324 if (rval != QLA_SUCCESS) {
1325 ql_log(ql_log_info, vha, 0xb0b3,
1326 "%s: HW State: FAILED\n", __func__);
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001327 qla8044_clear_drv_active(ha);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001328 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1329 QLA8XXX_DEV_FAILED);
1330 return rval;
1331 }
1332
1333 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1334 * device goes to INIT state. */
1335 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1336 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1337 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1338 (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1339 ha->fw_dumped = 0;
1340 }
1341
1342dev_ready:
1343 ql_log(ql_log_info, vha, 0xb0b4,
1344 "%s: HW State: READY\n", __func__);
1345 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1346
1347 return rval;
1348}
1349
1350/*-------------------------Reset Sequence Functions-----------------------*/
1351static void
1352qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1353{
1354 u8 *phdr;
1355
1356 if (!vha->reset_tmplt.buff) {
1357 ql_log(ql_log_fatal, vha, 0xb0b5,
1358 "%s: Error Invalid reset_seq_template\n", __func__);
1359 return;
1360 }
1361
1362 phdr = vha->reset_tmplt.buff;
1363 ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1364 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1365 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1366 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1367 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1368 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1369 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1370 *(phdr+13), *(phdr+14), *(phdr+15));
1371}
1372
1373/*
1374 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1375 *
1376 * @ha : Pointer to adapter structure
1377 *
1378 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1379 */
1380static int
1381qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1382{
1383 uint32_t sum = 0;
1384 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1385 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1386
1387 while (u16_count-- > 0)
1388 sum += *buff++;
1389
1390 while (sum >> 16)
1391 sum = (sum & 0xFFFF) + (sum >> 16);
1392
1393 /* checksum of 0 indicates a valid template */
1394 if (~sum) {
1395 return QLA_SUCCESS;
1396 } else {
1397 ql_log(ql_log_fatal, vha, 0xb0b7,
1398 "%s: Reset seq checksum failed\n", __func__);
1399 return QLA_FUNCTION_FAILED;
1400 }
1401}
1402
1403/*
1404 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1405 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1406 *
1407 * @ha : Pointer to adapter structure
1408 */
1409void
1410qla8044_read_reset_template(struct scsi_qla_host *vha)
1411{
1412 uint8_t *p_buff;
1413 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1414
1415 vha->reset_tmplt.seq_error = 0;
1416 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1417 if (vha->reset_tmplt.buff == NULL) {
1418 ql_log(ql_log_fatal, vha, 0xb0b8,
1419 "%s: Failed to allocate reset template resources\n",
1420 __func__);
1421 goto exit_read_reset_template;
1422 }
1423
1424 p_buff = vha->reset_tmplt.buff;
1425 addr = QLA8044_RESET_TEMPLATE_ADDR;
1426
1427 tmplt_hdr_def_size =
1428 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1429
1430 ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1431 "%s: Read template hdr size %d from Flash\n",
1432 __func__, tmplt_hdr_def_size);
1433
1434 /* Copy template header from flash */
1435 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1436 ql_log(ql_log_fatal, vha, 0xb0ba,
1437 "%s: Failed to read reset template\n", __func__);
1438 goto exit_read_template_error;
1439 }
1440
1441 vha->reset_tmplt.hdr =
1442 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1443
1444 /* Validate the template header size and signature */
1445 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1446 if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1447 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1448 ql_log(ql_log_fatal, vha, 0xb0bb,
1449 "%s: Template Header size invalid %d "
1450 "tmplt_hdr_def_size %d!!!\n", __func__,
1451 tmplt_hdr_size, tmplt_hdr_def_size);
1452 goto exit_read_template_error;
1453 }
1454
1455 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1456 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1457 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1458 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1459
1460 ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1461 "%s: Read rest of the template size %d\n",
1462 __func__, vha->reset_tmplt.hdr->size);
1463
1464 /* Copy rest of the template */
1465 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1466 ql_log(ql_log_fatal, vha, 0xb0bd,
1467 "%s: Failed to read reset tempelate\n", __func__);
1468 goto exit_read_template_error;
1469 }
1470
1471 /* Integrity check */
1472 if (qla8044_reset_seq_checksum_test(vha)) {
1473 ql_log(ql_log_fatal, vha, 0xb0be,
1474 "%s: Reset Seq checksum failed!\n", __func__);
1475 goto exit_read_template_error;
1476 }
1477
1478 ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1479 "%s: Reset Seq checksum passed! Get stop, "
1480 "start and init seq offsets\n", __func__);
1481
1482 /* Get STOP, START, INIT sequence offsets */
1483 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1484 vha->reset_tmplt.hdr->init_seq_offset;
1485
1486 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1487 vha->reset_tmplt.hdr->start_seq_offset;
1488
1489 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1490 vha->reset_tmplt.hdr->hdr_size;
1491
1492 qla8044_dump_reset_seq_hdr(vha);
1493
1494 goto exit_read_reset_template;
1495
1496exit_read_template_error:
1497 vfree(vha->reset_tmplt.buff);
1498
1499exit_read_reset_template:
1500 return;
1501}
1502
1503void
1504qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1505{
1506 uint32_t idc_ctrl;
1507 struct qla_hw_data *ha = vha->hw;
1508
1509 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1510 idc_ctrl |= DONTRESET_BIT0;
1511 ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1512 "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1513 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1514}
1515
1516inline void
1517qla8044_set_rst_ready(struct scsi_qla_host *vha)
1518{
1519 uint32_t drv_state;
1520 struct qla_hw_data *ha = vha->hw;
1521
1522 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1523
1524 /* For ISP8044, drv_active register has 1 bit per function,
1525 * shift 1 by func_num to set a bit for the function.*/
1526 drv_state |= (1 << ha->portnum);
1527
1528 ql_log(ql_log_info, vha, 0xb0c1,
1529 "%s(%ld): drv_state: 0x%08x\n",
1530 __func__, vha->host_no, drv_state);
1531 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1532}
1533
1534/**
1535 * qla8044_need_reset_handler - Code to start reset sequence
1536 * @ha: pointer to adapter structure
1537 *
1538 * Note: IDC lock must be held upon entry
1539 **/
1540static void
1541qla8044_need_reset_handler(struct scsi_qla_host *vha)
1542{
1543 uint32_t dev_state = 0, drv_state, drv_active;
1544 unsigned long reset_timeout, dev_init_timeout;
1545 struct qla_hw_data *ha = vha->hw;
1546
1547 ql_log(ql_log_fatal, vha, 0xb0c2,
1548 "%s: Performing ISP error recovery\n", __func__);
1549
1550 if (vha->flags.online) {
1551 qla8044_idc_unlock(ha);
1552 qla2x00_abort_isp_cleanup(vha);
1553 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1554 ha->isp_ops->nvram_config(vha);
1555 qla8044_idc_lock(ha);
1556 }
1557
Saurav Kashyap8f476112013-10-30 03:38:13 -04001558 drv_state = qla8044_rd_direct(vha,
1559 QLA8044_CRB_DRV_STATE_INDEX);
1560 drv_active = qla8044_rd_direct(vha,
1561 QLA8044_CRB_DRV_ACTIVE_INDEX);
1562
1563 ql_log(ql_log_info, vha, 0xb0c5,
1564 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1565 __func__, vha->host_no, drv_state, drv_active);
1566
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001567 if (!ha->flags.nic_core_reset_owner) {
1568 ql_dbg(ql_dbg_p3p, vha, 0xb0c3,
1569 "%s(%ld): reset acknowledged\n",
1570 __func__, vha->host_no);
1571 qla8044_set_rst_ready(vha);
1572
1573 /* Non-reset owners ACK Reset and wait for device INIT state
1574 * as part of Reset Recovery by Reset Owner
1575 */
1576 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1577
1578 do {
1579 if (time_after_eq(jiffies, dev_init_timeout)) {
1580 ql_log(ql_log_info, vha, 0xb0c4,
Atul Deshmukh145083e2014-02-26 04:14:59 -05001581 "%s: Non Reset owner: Reset Ack Timeout!\n",
1582 __func__);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001583 break;
1584 }
1585
1586 qla8044_idc_unlock(ha);
1587 msleep(1000);
1588 qla8044_idc_lock(ha);
1589
1590 dev_state = qla8044_rd_direct(vha,
1591 QLA8044_CRB_DEV_STATE_INDEX);
Saurav Kashyap8f476112013-10-30 03:38:13 -04001592 } while (((drv_state & drv_active) != drv_active) &&
1593 (dev_state == QLA8XXX_DEV_NEED_RESET));
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001594 } else {
1595 qla8044_set_rst_ready(vha);
1596
1597 /* wait for 10 seconds for reset ack from all functions */
1598 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1599
Saurav Kashyap8f476112013-10-30 03:38:13 -04001600 while ((drv_state & drv_active) != drv_active) {
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001601 if (time_after_eq(jiffies, reset_timeout)) {
1602 ql_log(ql_log_info, vha, 0xb0c6,
1603 "%s: RESET TIMEOUT!"
1604 "drv_state: 0x%08x, drv_active: 0x%08x\n",
1605 QLA2XXX_DRIVER_NAME, drv_state, drv_active);
1606 break;
1607 }
1608
1609 qla8044_idc_unlock(ha);
1610 msleep(1000);
1611 qla8044_idc_lock(ha);
1612
1613 drv_state = qla8044_rd_direct(vha,
1614 QLA8044_CRB_DRV_STATE_INDEX);
1615 drv_active = qla8044_rd_direct(vha,
1616 QLA8044_CRB_DRV_ACTIVE_INDEX);
1617 }
1618
1619 if (drv_state != drv_active) {
1620 ql_log(ql_log_info, vha, 0xb0c7,
1621 "%s(%ld): Reset_owner turning off drv_active "
1622 "of non-acking function 0x%x\n", __func__,
1623 vha->host_no, (drv_active ^ drv_state));
1624 drv_active = drv_active & drv_state;
1625 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1626 drv_active);
1627 }
1628
1629 /*
1630 * Clear RESET OWNER, will be set at next reset
1631 * by next RST_OWNER
1632 */
1633 ha->flags.nic_core_reset_owner = 0;
1634
1635 /* Start Reset Recovery */
1636 qla8044_device_bootstrap(vha);
1637 }
1638}
1639
1640static void
1641qla8044_set_drv_active(struct scsi_qla_host *vha)
1642{
1643 uint32_t drv_active;
1644 struct qla_hw_data *ha = vha->hw;
1645
1646 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1647
1648 /* For ISP8044, drv_active register has 1 bit per function,
1649 * shift 1 by func_num to set a bit for the function.*/
1650 drv_active |= (1 << ha->portnum);
1651
1652 ql_log(ql_log_info, vha, 0xb0c8,
1653 "%s(%ld): drv_active: 0x%08x\n",
1654 __func__, vha->host_no, drv_active);
1655 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1656}
1657
Giridhar Malavali4fa0c662014-04-11 16:54:11 -04001658static int
1659qla8044_check_drv_active(struct scsi_qla_host *vha)
1660{
1661 uint32_t drv_active;
1662 struct qla_hw_data *ha = vha->hw;
1663
1664 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1665 if (drv_active & (1 << ha->portnum))
1666 return QLA_SUCCESS;
1667 else
1668 return QLA_TEST_FAILED;
1669}
1670
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001671static void
1672qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1673{
1674 uint32_t idc_ctrl;
1675 struct qla_hw_data *ha = vha->hw;
1676
1677 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1678 idc_ctrl &= ~DONTRESET_BIT0;
1679 ql_log(ql_log_info, vha, 0xb0c9,
1680 "%s: idc_ctrl = %d\n", __func__,
1681 idc_ctrl);
1682 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1683}
1684
1685static int
1686qla8044_set_idc_ver(struct scsi_qla_host *vha)
1687{
1688 int idc_ver;
1689 uint32_t drv_active;
1690 int rval = QLA_SUCCESS;
1691 struct qla_hw_data *ha = vha->hw;
1692
1693 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1694 if (drv_active == (1 << ha->portnum)) {
1695 idc_ver = qla8044_rd_direct(vha,
1696 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1697 idc_ver &= (~0xFF);
1698 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1699 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1700 idc_ver);
1701 ql_log(ql_log_info, vha, 0xb0ca,
1702 "%s: IDC version updated to %d\n",
1703 __func__, idc_ver);
1704 } else {
1705 idc_ver = qla8044_rd_direct(vha,
1706 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1707 idc_ver &= 0xFF;
1708 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1709 ql_log(ql_log_info, vha, 0xb0cb,
1710 "%s: qla4xxx driver IDC version %d "
1711 "is not compatible with IDC version %d "
1712 "of other drivers!\n",
1713 __func__, QLA8044_IDC_VER_MAJ_VALUE,
1714 idc_ver);
1715 rval = QLA_FUNCTION_FAILED;
1716 goto exit_set_idc_ver;
1717 }
1718 }
1719
1720 /* Update IDC_MINOR_VERSION */
1721 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1722 idc_ver &= ~(0x03 << (ha->portnum * 2));
1723 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1724 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1725
1726exit_set_idc_ver:
1727 return rval;
1728}
1729
1730static int
1731qla8044_update_idc_reg(struct scsi_qla_host *vha)
1732{
1733 uint32_t drv_active;
1734 int rval = QLA_SUCCESS;
1735 struct qla_hw_data *ha = vha->hw;
1736
1737 if (vha->flags.init_done)
1738 goto exit_update_idc_reg;
1739
1740 qla8044_idc_lock(ha);
1741 qla8044_set_drv_active(vha);
1742
1743 drv_active = qla8044_rd_direct(vha,
1744 QLA8044_CRB_DRV_ACTIVE_INDEX);
1745
1746 /* If we are the first driver to load and
1747 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1748 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1749 qla8044_clear_idc_dontreset(vha);
1750
1751 rval = qla8044_set_idc_ver(vha);
1752 if (rval == QLA_FUNCTION_FAILED)
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001753 qla8044_clear_drv_active(ha);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001754 qla8044_idc_unlock(ha);
1755
1756exit_update_idc_reg:
1757 return rval;
1758}
1759
1760/**
1761 * qla8044_need_qsnt_handler - Code to start qsnt
1762 * @ha: pointer to adapter structure
1763 **/
1764static void
1765qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1766{
1767 unsigned long qsnt_timeout;
1768 uint32_t drv_state, drv_active, dev_state;
1769 struct qla_hw_data *ha = vha->hw;
1770
1771 if (vha->flags.online)
1772 qla2x00_quiesce_io(vha);
1773 else
1774 return;
1775
1776 qla8044_set_qsnt_ready(vha);
1777
1778 /* Wait for 30 secs for all functions to ack qsnt mode */
1779 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1780 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1781 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1782
1783 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1784 position is at bit 1 and drv active is at bit 0 */
1785 drv_active = drv_active << 1;
1786
1787 while (drv_state != drv_active) {
1788 if (time_after_eq(jiffies, qsnt_timeout)) {
1789 /* Other functions did not ack, changing state to
1790 * DEV_READY
1791 */
1792 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1793 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1794 QLA8XXX_DEV_READY);
1795 qla8044_clear_qsnt_ready(vha);
1796 ql_log(ql_log_info, vha, 0xb0cc,
1797 "Timeout waiting for quiescent ack!!!\n");
1798 return;
1799 }
1800 qla8044_idc_unlock(ha);
1801 msleep(1000);
1802 qla8044_idc_lock(ha);
1803
1804 drv_state = qla8044_rd_direct(vha,
1805 QLA8044_CRB_DRV_STATE_INDEX);
1806 drv_active = qla8044_rd_direct(vha,
1807 QLA8044_CRB_DRV_ACTIVE_INDEX);
1808 drv_active = drv_active << 1;
1809 }
1810
1811 /* All functions have Acked. Set quiescent state */
1812 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1813
1814 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1815 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1816 QLA8XXX_DEV_QUIESCENT);
1817 ql_log(ql_log_info, vha, 0xb0cd,
1818 "%s: HW State: QUIESCENT\n", __func__);
1819 }
1820}
1821
1822/*
1823 * qla8044_device_state_handler - Adapter state machine
1824 * @ha: pointer to host adapter structure.
1825 *
1826 * Note: IDC lock must be UNLOCKED upon entry
1827 **/
1828int
1829qla8044_device_state_handler(struct scsi_qla_host *vha)
1830{
1831 uint32_t dev_state;
1832 int rval = QLA_SUCCESS;
1833 unsigned long dev_init_timeout;
1834 struct qla_hw_data *ha = vha->hw;
1835
1836 rval = qla8044_update_idc_reg(vha);
1837 if (rval == QLA_FUNCTION_FAILED)
1838 goto exit_error;
1839
1840 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1841 ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1842 "Device state is 0x%x = %s\n",
1843 dev_state, dev_state < MAX_STATES ?
1844 qdev_state(dev_state) : "Unknown");
1845
1846 /* wait for 30 seconds for device to go ready */
1847 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1848
1849 qla8044_idc_lock(ha);
1850
1851 while (1) {
1852 if (time_after_eq(jiffies, dev_init_timeout)) {
Giridhar Malavali4fa0c662014-04-11 16:54:11 -04001853 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1854 ql_log(ql_log_warn, vha, 0xb0cf,
1855 "%s: Device Init Failed 0x%x = %s\n",
1856 QLA2XXX_DRIVER_NAME, dev_state,
1857 dev_state < MAX_STATES ?
1858 qdev_state(dev_state) : "Unknown");
1859 qla8044_wr_direct(vha,
1860 QLA8044_CRB_DEV_STATE_INDEX,
1861 QLA8XXX_DEV_FAILED);
1862 }
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001863 }
1864
1865 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1866 ql_log(ql_log_info, vha, 0xb0d0,
1867 "Device state is 0x%x = %s\n",
1868 dev_state, dev_state < MAX_STATES ?
1869 qdev_state(dev_state) : "Unknown");
1870
1871 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1872 switch (dev_state) {
1873 case QLA8XXX_DEV_READY:
1874 ha->flags.nic_core_reset_owner = 0;
1875 goto exit;
1876 case QLA8XXX_DEV_COLD:
1877 rval = qla8044_device_bootstrap(vha);
Sawan Chandak37460782013-10-30 03:38:26 -04001878 break;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001879 case QLA8XXX_DEV_INITIALIZING:
1880 qla8044_idc_unlock(ha);
1881 msleep(1000);
1882 qla8044_idc_lock(ha);
1883 break;
1884 case QLA8XXX_DEV_NEED_RESET:
1885 /* For ISP8044, if NEED_RESET is set by any driver,
1886 * it should be honored, irrespective of IDC_CTRL
1887 * DONTRESET_BIT0 */
1888 qla8044_need_reset_handler(vha);
1889 break;
1890 case QLA8XXX_DEV_NEED_QUIESCENT:
1891 /* idc locked/unlocked in handler */
1892 qla8044_need_qsnt_handler(vha);
1893
1894 /* Reset the init timeout after qsnt handler */
1895 dev_init_timeout = jiffies +
1896 (ha->fcoe_reset_timeout * HZ);
1897 break;
1898 case QLA8XXX_DEV_QUIESCENT:
1899 ql_log(ql_log_info, vha, 0xb0d1,
1900 "HW State: QUIESCENT\n");
1901
1902 qla8044_idc_unlock(ha);
1903 msleep(1000);
1904 qla8044_idc_lock(ha);
1905
1906 /* Reset the init timeout after qsnt handler */
1907 dev_init_timeout = jiffies +
1908 (ha->fcoe_reset_timeout * HZ);
1909 break;
1910 case QLA8XXX_DEV_FAILED:
1911 ha->flags.nic_core_reset_owner = 0;
1912 qla8044_idc_unlock(ha);
1913 qla8xxx_dev_failed_handler(vha);
1914 rval = QLA_FUNCTION_FAILED;
1915 qla8044_idc_lock(ha);
1916 goto exit;
1917 default:
1918 qla8044_idc_unlock(ha);
1919 qla8xxx_dev_failed_handler(vha);
1920 rval = QLA_FUNCTION_FAILED;
1921 qla8044_idc_lock(ha);
1922 goto exit;
1923 }
1924 }
1925exit:
1926 qla8044_idc_unlock(ha);
1927
1928exit_error:
1929 return rval;
1930}
1931
1932/**
1933 * qla4_8xxx_check_temp - Check the ISP82XX temperature.
1934 * @ha: adapter block pointer.
1935 *
1936 * Note: The caller should not hold the idc lock.
1937 **/
1938static int
1939qla8044_check_temp(struct scsi_qla_host *vha)
1940{
1941 uint32_t temp, temp_state, temp_val;
1942 int status = QLA_SUCCESS;
1943
1944 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1945 temp_state = qla82xx_get_temp_state(temp);
1946 temp_val = qla82xx_get_temp_val(temp);
1947
1948 if (temp_state == QLA82XX_TEMP_PANIC) {
1949 ql_log(ql_log_warn, vha, 0xb0d2,
1950 "Device temperature %d degrees C"
1951 " exceeds maximum allowed. Hardware has been shut"
1952 " down\n", temp_val);
1953 status = QLA_FUNCTION_FAILED;
1954 return status;
1955 } else if (temp_state == QLA82XX_TEMP_WARN) {
1956 ql_log(ql_log_warn, vha, 0xb0d3,
1957 "Device temperature %d"
1958 " degrees C exceeds operating range."
1959 " Immediate action needed.\n", temp_val);
1960 }
1961 return 0;
1962}
1963
Joe Carnuccio1ae47cf2013-08-27 01:37:36 -04001964int qla8044_read_temperature(scsi_qla_host_t *vha)
1965{
1966 uint32_t temp;
1967
1968 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1969 return qla82xx_get_temp_val(temp);
1970}
1971
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001972/**
1973 * qla8044_check_fw_alive - Check firmware health
1974 * @ha: Pointer to host adapter structure.
1975 *
1976 * Context: Interrupt
1977 **/
1978int
1979qla8044_check_fw_alive(struct scsi_qla_host *vha)
1980{
1981 uint32_t fw_heartbeat_counter;
1982 uint32_t halt_status1, halt_status2;
1983 int status = QLA_SUCCESS;
1984
1985 fw_heartbeat_counter = qla8044_rd_direct(vha,
1986 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1987
1988 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
1989 if (fw_heartbeat_counter == 0xffffffff) {
1990 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
1991 "scsi%ld: %s: Device in frozen "
1992 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
1993 vha->host_no, __func__);
1994 return status;
1995 }
1996
1997 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
1998 vha->seconds_since_last_heartbeat++;
1999 /* FW not alive after 2 seconds */
2000 if (vha->seconds_since_last_heartbeat == 2) {
2001 vha->seconds_since_last_heartbeat = 0;
2002 halt_status1 = qla8044_rd_direct(vha,
2003 QLA8044_PEG_HALT_STATUS1_INDEX);
2004 halt_status2 = qla8044_rd_direct(vha,
2005 QLA8044_PEG_HALT_STATUS2_INDEX);
2006
2007 ql_log(ql_log_info, vha, 0xb0d5,
2008 "scsi(%ld): %s, ISP8044 "
2009 "Dumping hw/fw registers:\n"
2010 " PEG_HALT_STATUS1: 0x%x, "
2011 "PEG_HALT_STATUS2: 0x%x,\n",
2012 vha->host_no, __func__, halt_status1,
2013 halt_status2);
2014 status = QLA_FUNCTION_FAILED;
2015 }
2016 } else
2017 vha->seconds_since_last_heartbeat = 0;
2018
2019 vha->fw_heartbeat_counter = fw_heartbeat_counter;
2020 return status;
2021}
2022
2023void
2024qla8044_watchdog(struct scsi_qla_host *vha)
2025{
2026 uint32_t dev_state, halt_status;
2027 int halt_status_unrecoverable = 0;
2028 struct qla_hw_data *ha = vha->hw;
2029
2030 /* don't poll if reset is going on or FW hang in quiescent state */
2031 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002032 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2033 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2034
2035 if (qla8044_check_temp(vha)) {
2036 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2037 ha->flags.isp82xx_fw_hung = 1;
2038 qla2xxx_wake_dpc(vha);
2039 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2040 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2041 ql_log(ql_log_info, vha, 0xb0d6,
2042 "%s: HW State: NEED RESET!\n",
2043 __func__);
2044 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2045 qla2xxx_wake_dpc(vha);
2046 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2047 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2048 ql_log(ql_log_info, vha, 0xb0d7,
2049 "%s: HW State: NEED QUIES detected!\n",
2050 __func__);
2051 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2052 qla2xxx_wake_dpc(vha);
2053 } else {
2054 /* Check firmware health */
2055 if (qla8044_check_fw_alive(vha)) {
2056 halt_status = qla8044_rd_direct(vha,
2057 QLA8044_PEG_HALT_STATUS1_INDEX);
2058 if (halt_status &
2059 QLA8044_HALT_STATUS_FW_RESET) {
2060 ql_log(ql_log_fatal, vha,
2061 0xb0d8, "%s: Firmware "
2062 "error detected device "
2063 "is being reset\n",
2064 __func__);
2065 } else if (halt_status &
2066 QLA8044_HALT_STATUS_UNRECOVERABLE) {
2067 halt_status_unrecoverable = 1;
2068 }
2069
2070 /* Since we cannot change dev_state in interrupt
2071 * context, set appropriate DPC flag then wakeup
2072 * DPC */
2073 if (halt_status_unrecoverable) {
2074 set_bit(ISP_UNRECOVERABLE,
2075 &vha->dpc_flags);
2076 } else {
2077 if (dev_state ==
2078 QLA8XXX_DEV_QUIESCENT) {
2079 set_bit(FCOE_CTX_RESET_NEEDED,
2080 &vha->dpc_flags);
2081 ql_log(ql_log_info, vha, 0xb0d9,
2082 "%s: FW CONTEXT Reset "
2083 "needed!\n", __func__);
2084 } else {
2085 ql_log(ql_log_info, vha,
2086 0xb0da, "%s: "
2087 "detect abort needed\n",
2088 __func__);
2089 set_bit(ISP_ABORT_NEEDED,
2090 &vha->dpc_flags);
2091 qla82xx_clear_pending_mbx(vha);
2092 }
2093 }
2094 ha->flags.isp82xx_fw_hung = 1;
2095 ql_log(ql_log_warn, vha, 0xb10a,
2096 "Firmware hung.\n");
2097 qla2xxx_wake_dpc(vha);
2098 }
2099 }
2100
2101 }
2102}
2103
2104static int
2105qla8044_minidump_process_control(struct scsi_qla_host *vha,
2106 struct qla8044_minidump_entry_hdr *entry_hdr)
2107{
2108 struct qla8044_minidump_entry_crb *crb_entry;
2109 uint32_t read_value, opcode, poll_time, addr, index;
2110 uint32_t crb_addr, rval = QLA_SUCCESS;
2111 unsigned long wtime;
2112 struct qla8044_minidump_template_hdr *tmplt_hdr;
2113 int i;
2114 struct qla_hw_data *ha = vha->hw;
2115
2116 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2117 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2118 ha->md_tmplt_hdr;
2119 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2120
2121 crb_addr = crb_entry->addr;
2122 for (i = 0; i < crb_entry->op_count; i++) {
2123 opcode = crb_entry->crb_ctrl.opcode;
2124
2125 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2126 qla8044_wr_reg_indirect(vha, crb_addr,
2127 crb_entry->value_1);
2128 opcode &= ~QLA82XX_DBG_OPCODE_WR;
2129 }
2130
2131 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2132 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2133 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2134 opcode &= ~QLA82XX_DBG_OPCODE_RW;
2135 }
2136
2137 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2138 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2139 read_value &= crb_entry->value_2;
2140 opcode &= ~QLA82XX_DBG_OPCODE_AND;
2141 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2142 read_value |= crb_entry->value_3;
2143 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2144 }
2145 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2146 }
2147 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2148 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2149 read_value |= crb_entry->value_3;
2150 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2151 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2152 }
2153 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2154 poll_time = crb_entry->crb_strd.poll_timeout;
2155 wtime = jiffies + poll_time;
2156 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2157
2158 do {
2159 if ((read_value & crb_entry->value_2) ==
2160 crb_entry->value_1) {
2161 break;
2162 } else if (time_after_eq(jiffies, wtime)) {
2163 /* capturing dump failed */
2164 rval = QLA_FUNCTION_FAILED;
2165 break;
2166 } else {
2167 qla8044_rd_reg_indirect(vha,
2168 crb_addr, &read_value);
2169 }
2170 } while (1);
2171 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2172 }
2173
2174 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2175 if (crb_entry->crb_strd.state_index_a) {
2176 index = crb_entry->crb_strd.state_index_a;
2177 addr = tmplt_hdr->saved_state_array[index];
2178 } else {
2179 addr = crb_addr;
2180 }
2181
2182 qla8044_rd_reg_indirect(vha, addr, &read_value);
2183 index = crb_entry->crb_ctrl.state_index_v;
2184 tmplt_hdr->saved_state_array[index] = read_value;
2185 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2186 }
2187
2188 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2189 if (crb_entry->crb_strd.state_index_a) {
2190 index = crb_entry->crb_strd.state_index_a;
2191 addr = tmplt_hdr->saved_state_array[index];
2192 } else {
2193 addr = crb_addr;
2194 }
2195
2196 if (crb_entry->crb_ctrl.state_index_v) {
2197 index = crb_entry->crb_ctrl.state_index_v;
2198 read_value =
2199 tmplt_hdr->saved_state_array[index];
2200 } else {
2201 read_value = crb_entry->value_1;
2202 }
2203
2204 qla8044_wr_reg_indirect(vha, addr, read_value);
2205 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2206 }
2207
2208 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2209 index = crb_entry->crb_ctrl.state_index_v;
2210 read_value = tmplt_hdr->saved_state_array[index];
2211 read_value <<= crb_entry->crb_ctrl.shl;
2212 read_value >>= crb_entry->crb_ctrl.shr;
2213 if (crb_entry->value_2)
2214 read_value &= crb_entry->value_2;
2215 read_value |= crb_entry->value_3;
2216 read_value += crb_entry->value_1;
2217 tmplt_hdr->saved_state_array[index] = read_value;
2218 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2219 }
2220 crb_addr += crb_entry->crb_strd.addr_stride;
2221 }
2222 return rval;
2223}
2224
2225static void
2226qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2227 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2228{
2229 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2230 struct qla8044_minidump_entry_crb *crb_hdr;
2231 uint32_t *data_ptr = *d_ptr;
2232
2233 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2234 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2235 r_addr = crb_hdr->addr;
2236 r_stride = crb_hdr->crb_strd.addr_stride;
2237 loop_cnt = crb_hdr->op_count;
2238
2239 for (i = 0; i < loop_cnt; i++) {
2240 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2241 *data_ptr++ = r_addr;
2242 *data_ptr++ = r_value;
2243 r_addr += r_stride;
2244 }
2245 *d_ptr = data_ptr;
2246}
2247
2248static int
2249qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2250 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2251{
2252 uint32_t r_addr, r_value, r_data;
2253 uint32_t i, j, loop_cnt;
2254 struct qla8044_minidump_entry_rdmem *m_hdr;
2255 unsigned long flags;
2256 uint32_t *data_ptr = *d_ptr;
2257 struct qla_hw_data *ha = vha->hw;
2258
2259 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2260 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2261 r_addr = m_hdr->read_addr;
2262 loop_cnt = m_hdr->read_data_size/16;
2263
2264 ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2265 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2266 __func__, r_addr, m_hdr->read_data_size);
2267
2268 if (r_addr & 0xf) {
2269 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
Masanari Iida8faaaea2014-01-07 21:58:06 +09002270 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002271 __func__, r_addr);
2272 return QLA_FUNCTION_FAILED;
2273 }
2274
2275 if (m_hdr->read_data_size % 16) {
2276 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2277 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2278 __func__, m_hdr->read_data_size);
2279 return QLA_FUNCTION_FAILED;
2280 }
2281
2282 ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2283 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2284 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2285
2286 write_lock_irqsave(&ha->hw_lock, flags);
2287 for (i = 0; i < loop_cnt; i++) {
2288 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2289 r_value = 0;
2290 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2291 r_value = MIU_TA_CTL_ENABLE;
2292 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2293 r_value = MIU_TA_CTL_START_ENABLE;
2294 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2295
2296 for (j = 0; j < MAX_CTL_CHECK; j++) {
2297 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2298 &r_value);
2299 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2300 break;
2301 }
2302
2303 if (j >= MAX_CTL_CHECK) {
2304 printk_ratelimited(KERN_ERR
2305 "%s: failed to read through agent\n", __func__);
2306 write_unlock_irqrestore(&ha->hw_lock, flags);
2307 return QLA_SUCCESS;
2308 }
2309
2310 for (j = 0; j < 4; j++) {
2311 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2312 &r_data);
2313 *data_ptr++ = r_data;
2314 }
2315
2316 r_addr += 16;
2317 }
2318 write_unlock_irqrestore(&ha->hw_lock, flags);
2319
2320 ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2321 "Leaving fn: %s datacount: 0x%x\n",
2322 __func__, (loop_cnt * 16));
2323
2324 *d_ptr = data_ptr;
2325 return QLA_SUCCESS;
2326}
2327
2328/* ISP83xx flash read for _RDROM _BOARD */
2329static uint32_t
2330qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2331 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2332{
2333 uint32_t fl_addr, u32_count, rval;
2334 struct qla8044_minidump_entry_rdrom *rom_hdr;
2335 uint32_t *data_ptr = *d_ptr;
2336
2337 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2338 fl_addr = rom_hdr->read_addr;
2339 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2340
2341 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2342 __func__, fl_addr, u32_count);
2343
2344 rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2345 (u8 *)(data_ptr), u32_count);
2346
2347 if (rval != QLA_SUCCESS) {
2348 ql_log(ql_log_fatal, vha, 0xb0f6,
2349 "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2350 return QLA_FUNCTION_FAILED;
2351 } else {
2352 data_ptr += u32_count;
2353 *d_ptr = data_ptr;
2354 return QLA_SUCCESS;
2355 }
2356}
2357
2358static void
2359qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2360 struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2361{
2362 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2363
2364 ql_log(ql_log_info, vha, 0xb0f7,
2365 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2366 vha->host_no, index, entry_hdr->entry_type,
2367 entry_hdr->d_ctrl.entry_capture_mask);
2368}
2369
2370static int
2371qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2372 struct qla8044_minidump_entry_hdr *entry_hdr,
2373 uint32_t **d_ptr)
2374{
2375 uint32_t addr, r_addr, c_addr, t_r_addr;
2376 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2377 unsigned long p_wait, w_time, p_mask;
2378 uint32_t c_value_w, c_value_r;
2379 struct qla8044_minidump_entry_cache *cache_hdr;
2380 int rval = QLA_FUNCTION_FAILED;
2381 uint32_t *data_ptr = *d_ptr;
2382
2383 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2384 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2385
2386 loop_count = cache_hdr->op_count;
2387 r_addr = cache_hdr->read_addr;
2388 c_addr = cache_hdr->control_addr;
2389 c_value_w = cache_hdr->cache_ctrl.write_value;
2390
2391 t_r_addr = cache_hdr->tag_reg_addr;
2392 t_value = cache_hdr->addr_ctrl.init_tag_value;
2393 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2394 p_wait = cache_hdr->cache_ctrl.poll_wait;
2395 p_mask = cache_hdr->cache_ctrl.poll_mask;
2396
2397 for (i = 0; i < loop_count; i++) {
2398 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2399 if (c_value_w)
2400 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2401
2402 if (p_mask) {
2403 w_time = jiffies + p_wait;
2404 do {
2405 qla8044_rd_reg_indirect(vha, c_addr,
2406 &c_value_r);
2407 if ((c_value_r & p_mask) == 0) {
2408 break;
2409 } else if (time_after_eq(jiffies, w_time)) {
2410 /* capturing dump failed */
2411 return rval;
2412 }
2413 } while (1);
2414 }
2415
2416 addr = r_addr;
2417 for (k = 0; k < r_cnt; k++) {
2418 qla8044_rd_reg_indirect(vha, addr, &r_value);
2419 *data_ptr++ = r_value;
2420 addr += cache_hdr->read_ctrl.read_addr_stride;
2421 }
2422 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2423 }
2424 *d_ptr = data_ptr;
2425 return QLA_SUCCESS;
2426}
2427
2428static void
2429qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2430 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2431{
2432 uint32_t addr, r_addr, c_addr, t_r_addr;
2433 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2434 uint32_t c_value_w;
2435 struct qla8044_minidump_entry_cache *cache_hdr;
2436 uint32_t *data_ptr = *d_ptr;
2437
2438 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2439 loop_count = cache_hdr->op_count;
2440 r_addr = cache_hdr->read_addr;
2441 c_addr = cache_hdr->control_addr;
2442 c_value_w = cache_hdr->cache_ctrl.write_value;
2443
2444 t_r_addr = cache_hdr->tag_reg_addr;
2445 t_value = cache_hdr->addr_ctrl.init_tag_value;
2446 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2447
2448 for (i = 0; i < loop_count; i++) {
2449 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2450 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2451 addr = r_addr;
2452 for (k = 0; k < r_cnt; k++) {
2453 qla8044_rd_reg_indirect(vha, addr, &r_value);
2454 *data_ptr++ = r_value;
2455 addr += cache_hdr->read_ctrl.read_addr_stride;
2456 }
2457 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2458 }
2459 *d_ptr = data_ptr;
2460}
2461
2462static void
2463qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2464 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2465{
2466 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2467 struct qla8044_minidump_entry_rdocm *ocm_hdr;
2468 uint32_t *data_ptr = *d_ptr;
2469 struct qla_hw_data *ha = vha->hw;
2470
2471 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2472
2473 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2474 r_addr = ocm_hdr->read_addr;
2475 r_stride = ocm_hdr->read_addr_stride;
2476 loop_cnt = ocm_hdr->op_count;
2477
2478 ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2479 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2480 __func__, r_addr, r_stride, loop_cnt);
2481
2482 for (i = 0; i < loop_cnt; i++) {
2483 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2484 *data_ptr++ = r_value;
2485 r_addr += r_stride;
2486 }
2487 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2488 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2489
2490 *d_ptr = data_ptr;
2491}
2492
2493static void
2494qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2495 struct qla8044_minidump_entry_hdr *entry_hdr,
2496 uint32_t **d_ptr)
2497{
2498 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2499 struct qla8044_minidump_entry_mux *mux_hdr;
2500 uint32_t *data_ptr = *d_ptr;
2501
2502 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2503
2504 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2505 r_addr = mux_hdr->read_addr;
2506 s_addr = mux_hdr->select_addr;
2507 s_stride = mux_hdr->select_value_stride;
2508 s_value = mux_hdr->select_value;
2509 loop_cnt = mux_hdr->op_count;
2510
2511 for (i = 0; i < loop_cnt; i++) {
2512 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2513 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2514 *data_ptr++ = s_value;
2515 *data_ptr++ = r_value;
2516 s_value += s_stride;
2517 }
2518 *d_ptr = data_ptr;
2519}
2520
2521static void
2522qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2523 struct qla8044_minidump_entry_hdr *entry_hdr,
2524 uint32_t **d_ptr)
2525{
2526 uint32_t s_addr, r_addr;
2527 uint32_t r_stride, r_value, r_cnt, qid = 0;
2528 uint32_t i, k, loop_cnt;
2529 struct qla8044_minidump_entry_queue *q_hdr;
2530 uint32_t *data_ptr = *d_ptr;
2531
2532 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2533 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2534 s_addr = q_hdr->select_addr;
2535 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2536 r_stride = q_hdr->rd_strd.read_addr_stride;
2537 loop_cnt = q_hdr->op_count;
2538
2539 for (i = 0; i < loop_cnt; i++) {
2540 qla8044_wr_reg_indirect(vha, s_addr, qid);
2541 r_addr = q_hdr->read_addr;
2542 for (k = 0; k < r_cnt; k++) {
2543 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2544 *data_ptr++ = r_value;
2545 r_addr += r_stride;
2546 }
2547 qid += q_hdr->q_strd.queue_id_stride;
2548 }
2549 *d_ptr = data_ptr;
2550}
2551
2552/* ISP83xx functions to process new minidump entries... */
2553static uint32_t
2554qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2555 struct qla8044_minidump_entry_hdr *entry_hdr,
2556 uint32_t **d_ptr)
2557{
2558 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2559 uint16_t s_stride, i;
2560 struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2561 uint32_t *data_ptr = *d_ptr;
2562
2563 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2564 s_addr = pollrd_hdr->select_addr;
2565 r_addr = pollrd_hdr->read_addr;
2566 s_value = pollrd_hdr->select_value;
2567 s_stride = pollrd_hdr->select_value_stride;
2568
2569 poll_wait = pollrd_hdr->poll_wait;
2570 poll_mask = pollrd_hdr->poll_mask;
2571
2572 for (i = 0; i < pollrd_hdr->op_count; i++) {
2573 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2574 poll_wait = pollrd_hdr->poll_wait;
2575 while (1) {
2576 qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2577 if ((r_value & poll_mask) != 0) {
2578 break;
2579 } else {
2580 usleep_range(1000, 1100);
2581 if (--poll_wait == 0) {
2582 ql_log(ql_log_fatal, vha, 0xb0fe,
2583 "%s: TIMEOUT\n", __func__);
2584 goto error;
2585 }
2586 }
2587 }
2588 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2589 *data_ptr++ = s_value;
2590 *data_ptr++ = r_value;
2591
2592 s_value += s_stride;
2593 }
2594 *d_ptr = data_ptr;
2595 return QLA_SUCCESS;
2596
2597error:
2598 return QLA_FUNCTION_FAILED;
2599}
2600
2601static void
2602qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2603 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2604{
2605 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2606 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2607 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2608 uint32_t *data_ptr = *d_ptr;
2609
2610 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2611 sel_val1 = rdmux2_hdr->select_value_1;
2612 sel_val2 = rdmux2_hdr->select_value_2;
2613 sel_addr1 = rdmux2_hdr->select_addr_1;
2614 sel_addr2 = rdmux2_hdr->select_addr_2;
2615 sel_val_mask = rdmux2_hdr->select_value_mask;
2616 read_addr = rdmux2_hdr->read_addr;
2617
2618 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2619 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2620 t_sel_val = sel_val1 & sel_val_mask;
2621 *data_ptr++ = t_sel_val;
2622
2623 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2624 qla8044_rd_reg_indirect(vha, read_addr, &data);
2625
2626 *data_ptr++ = data;
2627
2628 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2629 t_sel_val = sel_val2 & sel_val_mask;
2630 *data_ptr++ = t_sel_val;
2631
2632 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2633 qla8044_rd_reg_indirect(vha, read_addr, &data);
2634
2635 *data_ptr++ = data;
2636
2637 sel_val1 += rdmux2_hdr->select_value_stride;
2638 sel_val2 += rdmux2_hdr->select_value_stride;
2639 }
2640
2641 *d_ptr = data_ptr;
2642}
2643
2644static uint32_t
2645qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2646 struct qla8044_minidump_entry_hdr *entry_hdr,
2647 uint32_t **d_ptr)
2648{
2649 uint32_t poll_wait, poll_mask, r_value, data;
2650 uint32_t addr_1, addr_2, value_1, value_2;
2651 struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2652 uint32_t *data_ptr = *d_ptr;
2653
2654 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2655 addr_1 = poll_hdr->addr_1;
2656 addr_2 = poll_hdr->addr_2;
2657 value_1 = poll_hdr->value_1;
2658 value_2 = poll_hdr->value_2;
2659 poll_mask = poll_hdr->poll_mask;
2660
2661 qla8044_wr_reg_indirect(vha, addr_1, value_1);
2662
2663 poll_wait = poll_hdr->poll_wait;
2664 while (1) {
2665 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2666
2667 if ((r_value & poll_mask) != 0) {
2668 break;
2669 } else {
2670 usleep_range(1000, 1100);
2671 if (--poll_wait == 0) {
2672 ql_log(ql_log_fatal, vha, 0xb0ff,
2673 "%s: TIMEOUT\n", __func__);
2674 goto error;
2675 }
2676 }
2677 }
2678
2679 qla8044_rd_reg_indirect(vha, addr_2, &data);
2680 data &= poll_hdr->modify_mask;
2681 qla8044_wr_reg_indirect(vha, addr_2, data);
2682 qla8044_wr_reg_indirect(vha, addr_1, value_2);
2683
2684 poll_wait = poll_hdr->poll_wait;
2685 while (1) {
2686 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2687
2688 if ((r_value & poll_mask) != 0) {
2689 break;
2690 } else {
2691 usleep_range(1000, 1100);
2692 if (--poll_wait == 0) {
2693 ql_log(ql_log_fatal, vha, 0xb100,
2694 "%s: TIMEOUT2\n", __func__);
2695 goto error;
2696 }
2697 }
2698 }
2699
2700 *data_ptr++ = addr_2;
2701 *data_ptr++ = data;
2702
2703 *d_ptr = data_ptr;
2704
2705 return QLA_SUCCESS;
2706
2707error:
2708 return QLA_FUNCTION_FAILED;
2709}
2710
2711#define ISP8044_PEX_DMA_ENGINE_INDEX 8
2712#define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2713#define ISP8044_PEX_DMA_NUM_OFFSET 0x10000
2714#define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
2715#define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
2716#define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
2717
2718#define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
2719#define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
2720
2721static int
2722qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2723{
2724 struct qla_hw_data *ha = vha->hw;
2725 int rval = QLA_SUCCESS;
2726 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2727 uint64_t dma_base_addr = 0;
2728 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2729
2730 tmplt_hdr = ha->md_tmplt_hdr;
2731 dma_eng_num =
2732 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2733 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2734 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2735
2736 /* Read the pex-dma's command-status-and-control register. */
2737 rval = qla8044_rd_reg_indirect(vha,
2738 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2739 &cmd_sts_and_cntrl);
2740 if (rval)
2741 return QLA_FUNCTION_FAILED;
2742
2743 /* Check if requested pex-dma engine is available. */
2744 if (cmd_sts_and_cntrl & BIT_31)
2745 return QLA_SUCCESS;
2746
2747 return QLA_FUNCTION_FAILED;
2748}
2749
2750static int
2751qla8044_start_pex_dma(struct scsi_qla_host *vha,
2752 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2753{
2754 struct qla_hw_data *ha = vha->hw;
2755 int rval = QLA_SUCCESS, wait = 0;
2756 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2757 uint64_t dma_base_addr = 0;
2758 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2759
2760 tmplt_hdr = ha->md_tmplt_hdr;
2761 dma_eng_num =
2762 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2763 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2764 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2765
2766 rval = qla8044_wr_reg_indirect(vha,
2767 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2768 m_hdr->desc_card_addr);
2769 if (rval)
2770 goto error_exit;
2771
2772 rval = qla8044_wr_reg_indirect(vha,
2773 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2774 if (rval)
2775 goto error_exit;
2776
2777 rval = qla8044_wr_reg_indirect(vha,
2778 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2779 m_hdr->start_dma_cmd);
2780 if (rval)
2781 goto error_exit;
2782
2783 /* Wait for dma operation to complete. */
2784 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2785 rval = qla8044_rd_reg_indirect(vha,
2786 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2787 &cmd_sts_and_cntrl);
2788 if (rval)
2789 goto error_exit;
2790
2791 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2792 break;
2793
2794 udelay(10);
2795 }
2796
2797 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2798 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2799 rval = QLA_FUNCTION_FAILED;
2800 goto error_exit;
2801 }
2802
2803error_exit:
2804 return rval;
2805}
2806
2807static int
2808qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2809 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2810{
2811 struct qla_hw_data *ha = vha->hw;
2812 int rval = QLA_SUCCESS;
2813 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2814 uint32_t chunk_size, read_size;
2815 uint8_t *data_ptr = (uint8_t *)*d_ptr;
2816 void *rdmem_buffer = NULL;
2817 dma_addr_t rdmem_dma;
2818 struct qla8044_pex_dma_descriptor dma_desc;
2819
2820 rval = qla8044_check_dma_engine_state(vha);
2821 if (rval != QLA_SUCCESS) {
2822 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2823 "DMA engine not available. Fallback to rdmem-read.\n");
2824 return QLA_FUNCTION_FAILED;
2825 }
2826
2827 m_hdr = (void *)entry_hdr;
2828
2829 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2830 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2831 if (!rdmem_buffer) {
2832 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2833 "Unable to allocate rdmem dma buffer\n");
2834 return QLA_FUNCTION_FAILED;
2835 }
2836
2837 /* Prepare pex-dma descriptor to be written to MS memory. */
2838 /* dma-desc-cmd layout:
2839 * 0-3: dma-desc-cmd 0-3
2840 * 4-7: pcid function number
2841 * 8-15: dma-desc-cmd 8-15
2842 * dma_bus_addr: dma buffer address
2843 * cmd.read_data_size: amount of data-chunk to be read.
2844 */
2845 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2846 dma_desc.cmd.dma_desc_cmd |=
2847 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2848
2849 dma_desc.dma_bus_addr = rdmem_dma;
2850 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2851 read_size = 0;
2852
2853 /*
2854 * Perform rdmem operation using pex-dma.
2855 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2856 */
2857 while (read_size < m_hdr->read_data_size) {
2858 if (m_hdr->read_data_size - read_size <
2859 ISP8044_PEX_DMA_READ_SIZE) {
2860 chunk_size = (m_hdr->read_data_size - read_size);
2861 dma_desc.cmd.read_data_size = chunk_size;
2862 }
2863
2864 dma_desc.src_addr = m_hdr->read_addr + read_size;
2865
2866 /* Prepare: Write pex-dma descriptor to MS memory. */
2867 rval = qla8044_ms_mem_write_128b(vha,
2868 m_hdr->desc_card_addr, (void *)&dma_desc,
2869 (sizeof(struct qla8044_pex_dma_descriptor)/16));
2870 if (rval) {
2871 ql_log(ql_log_warn, vha, 0xb14a,
2872 "%s: Error writing rdmem-dma-init to MS !!!\n",
2873 __func__);
2874 goto error_exit;
2875 }
2876 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2877 "%s: Dma-descriptor: Instruct for rdmem dma "
2878 "(chunk_size 0x%x).\n", __func__, chunk_size);
2879
2880 /* Execute: Start pex-dma operation. */
2881 rval = qla8044_start_pex_dma(vha, m_hdr);
2882 if (rval)
2883 goto error_exit;
2884
2885 memcpy(data_ptr, rdmem_buffer, chunk_size);
2886 data_ptr += chunk_size;
2887 read_size += chunk_size;
2888 }
2889
2890 *d_ptr = (void *)data_ptr;
2891
2892error_exit:
2893 if (rdmem_buffer)
2894 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2895 rdmem_buffer, rdmem_dma);
2896
2897 return rval;
2898}
2899
2900/*
2901 *
2902 * qla8044_collect_md_data - Retrieve firmware minidump data.
2903 * @ha: pointer to adapter structure
2904 **/
2905int
2906qla8044_collect_md_data(struct scsi_qla_host *vha)
2907{
2908 int num_entry_hdr = 0;
2909 struct qla8044_minidump_entry_hdr *entry_hdr;
2910 struct qla8044_minidump_template_hdr *tmplt_hdr;
2911 uint32_t *data_ptr;
2912 uint32_t data_collected = 0, f_capture_mask;
2913 int i, rval = QLA_FUNCTION_FAILED;
2914 uint64_t now;
2915 uint32_t timestamp, idc_control;
2916 struct qla_hw_data *ha = vha->hw;
2917
2918 if (!ha->md_dump) {
2919 ql_log(ql_log_info, vha, 0xb101,
2920 "%s(%ld) No buffer to dump\n",
2921 __func__, vha->host_no);
2922 return rval;
2923 }
2924
2925 if (ha->fw_dumped) {
2926 ql_log(ql_log_warn, vha, 0xb10d,
2927 "Firmware has been previously dumped (%p) "
2928 "-- ignoring request.\n", ha->fw_dump);
2929 goto md_failed;
2930 }
2931
2932 ha->fw_dumped = 0;
2933
2934 if (!ha->md_tmplt_hdr || !ha->md_dump) {
2935 ql_log(ql_log_warn, vha, 0xb10e,
2936 "Memory not allocated for minidump capture\n");
2937 goto md_failed;
2938 }
2939
2940 qla8044_idc_lock(ha);
2941 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
2942 if (idc_control & GRACEFUL_RESET_BIT1) {
2943 ql_log(ql_log_warn, vha, 0xb112,
2944 "Forced reset from application, "
2945 "ignore minidump capture\n");
2946 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
2947 (idc_control & ~GRACEFUL_RESET_BIT1));
2948 qla8044_idc_unlock(ha);
2949
2950 goto md_failed;
2951 }
2952 qla8044_idc_unlock(ha);
2953
2954 if (qla82xx_validate_template_chksum(vha)) {
2955 ql_log(ql_log_info, vha, 0xb109,
2956 "Template checksum validation error\n");
2957 goto md_failed;
2958 }
2959
2960 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2961 ha->md_tmplt_hdr;
2962 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
2963 num_entry_hdr = tmplt_hdr->num_of_entries;
2964
2965 ql_dbg(ql_dbg_p3p, vha, 0xb11a,
2966 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
2967
2968 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
2969
2970 /* Validate whether required debug level is set */
2971 if ((f_capture_mask & 0x3) != 0x3) {
2972 ql_log(ql_log_warn, vha, 0xb10f,
2973 "Minimum required capture mask[0x%x] level not set\n",
2974 f_capture_mask);
2975
2976 }
2977 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
2978 ql_log(ql_log_info, vha, 0xb102,
2979 "[%s]: starting data ptr: %p\n",
2980 __func__, data_ptr);
2981 ql_log(ql_log_info, vha, 0xb10b,
2982 "[%s]: no of entry headers in Template: 0x%x\n",
2983 __func__, num_entry_hdr);
2984 ql_log(ql_log_info, vha, 0xb10c,
2985 "[%s]: Total_data_size 0x%x, %d obtained\n",
2986 __func__, ha->md_dump_size, ha->md_dump_size);
2987
2988 /* Update current timestamp before taking dump */
2989 now = get_jiffies_64();
2990 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2991 tmplt_hdr->driver_timestamp = timestamp;
2992
2993 entry_hdr = (struct qla8044_minidump_entry_hdr *)
2994 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
2995 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
2996 tmplt_hdr->ocm_window_reg[ha->portnum];
2997
2998 /* Walk through the entry headers - validate/perform required action */
2999 for (i = 0; i < num_entry_hdr; i++) {
3000 if (data_collected > ha->md_dump_size) {
3001 ql_log(ql_log_info, vha, 0xb103,
3002 "Data collected: [0x%x], "
3003 "Total Dump size: [0x%x]\n",
3004 data_collected, ha->md_dump_size);
3005 return rval;
3006 }
3007
3008 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3009 ql2xmdcapmask)) {
3010 entry_hdr->d_ctrl.driver_flags |=
3011 QLA82XX_DBG_SKIPPED_FLAG;
3012 goto skip_nxt_entry;
3013 }
3014
3015 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3016 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3017 data_collected,
3018 (ha->md_dump_size - data_collected));
3019
3020 /* Decode the entry type and take required action to capture
3021 * debug data
3022 */
3023 switch (entry_hdr->entry_type) {
3024 case QLA82XX_RDEND:
3025 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3026 break;
3027 case QLA82XX_CNTRL:
3028 rval = qla8044_minidump_process_control(vha,
3029 entry_hdr);
3030 if (rval != QLA_SUCCESS) {
3031 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3032 goto md_failed;
3033 }
3034 break;
3035 case QLA82XX_RDCRB:
3036 qla8044_minidump_process_rdcrb(vha,
3037 entry_hdr, &data_ptr);
3038 break;
3039 case QLA82XX_RDMEM:
3040 rval = qla8044_minidump_pex_dma_read(vha,
3041 entry_hdr, &data_ptr);
3042 if (rval != QLA_SUCCESS) {
3043 rval = qla8044_minidump_process_rdmem(vha,
3044 entry_hdr, &data_ptr);
3045 if (rval != QLA_SUCCESS) {
3046 qla8044_mark_entry_skipped(vha,
3047 entry_hdr, i);
3048 goto md_failed;
3049 }
3050 }
3051 break;
3052 case QLA82XX_BOARD:
3053 case QLA82XX_RDROM:
3054 rval = qla8044_minidump_process_rdrom(vha,
3055 entry_hdr, &data_ptr);
3056 if (rval != QLA_SUCCESS) {
3057 qla8044_mark_entry_skipped(vha,
3058 entry_hdr, i);
3059 }
3060 break;
3061 case QLA82XX_L2DTG:
3062 case QLA82XX_L2ITG:
3063 case QLA82XX_L2DAT:
3064 case QLA82XX_L2INS:
3065 rval = qla8044_minidump_process_l2tag(vha,
3066 entry_hdr, &data_ptr);
3067 if (rval != QLA_SUCCESS) {
3068 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3069 goto md_failed;
3070 }
3071 break;
3072 case QLA8044_L1DTG:
3073 case QLA8044_L1ITG:
3074 case QLA82XX_L1DAT:
3075 case QLA82XX_L1INS:
3076 qla8044_minidump_process_l1cache(vha,
3077 entry_hdr, &data_ptr);
3078 break;
3079 case QLA82XX_RDOCM:
3080 qla8044_minidump_process_rdocm(vha,
3081 entry_hdr, &data_ptr);
3082 break;
3083 case QLA82XX_RDMUX:
3084 qla8044_minidump_process_rdmux(vha,
3085 entry_hdr, &data_ptr);
3086 break;
3087 case QLA82XX_QUEUE:
3088 qla8044_minidump_process_queue(vha,
3089 entry_hdr, &data_ptr);
3090 break;
3091 case QLA8044_POLLRD:
3092 rval = qla8044_minidump_process_pollrd(vha,
3093 entry_hdr, &data_ptr);
3094 if (rval != QLA_SUCCESS)
3095 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3096 break;
3097 case QLA8044_RDMUX2:
3098 qla8044_minidump_process_rdmux2(vha,
3099 entry_hdr, &data_ptr);
3100 break;
3101 case QLA8044_POLLRDMWR:
3102 rval = qla8044_minidump_process_pollrdmwr(vha,
3103 entry_hdr, &data_ptr);
3104 if (rval != QLA_SUCCESS)
3105 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3106 break;
3107 case QLA82XX_RDNOP:
3108 default:
3109 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3110 break;
3111 }
3112
3113 data_collected = (uint8_t *)data_ptr -
3114 (uint8_t *)((uint8_t *)ha->md_dump);
3115skip_nxt_entry:
3116 /*
3117 * next entry in the template
3118 */
3119 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3120 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3121 }
3122
3123 if (data_collected != ha->md_dump_size) {
3124 ql_log(ql_log_info, vha, 0xb105,
3125 "Dump data mismatch: Data collected: "
3126 "[0x%x], total_data_size:[0x%x]\n",
3127 data_collected, ha->md_dump_size);
Saurav Kashyapedaa5c72014-04-11 16:54:14 -04003128 rval = QLA_FUNCTION_FAILED;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003129 goto md_failed;
3130 }
3131
3132 ql_log(ql_log_info, vha, 0xb110,
3133 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3134 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3135 ha->fw_dumped = 1;
3136 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3137
3138
3139 ql_log(ql_log_info, vha, 0xb106,
3140 "Leaving fn: %s Last entry: 0x%x\n",
3141 __func__, i);
3142md_failed:
3143 return rval;
3144}
3145
3146void
3147qla8044_get_minidump(struct scsi_qla_host *vha)
3148{
3149 struct qla_hw_data *ha = vha->hw;
3150
3151 if (!qla8044_collect_md_data(vha)) {
3152 ha->fw_dumped = 1;
Saurav Kashyapedaa5c72014-04-11 16:54:14 -04003153 ha->prev_minidump_failed = 0;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003154 } else {
3155 ql_log(ql_log_fatal, vha, 0xb0db,
3156 "%s: Unable to collect minidump\n",
3157 __func__);
Saurav Kashyapedaa5c72014-04-11 16:54:14 -04003158 ha->prev_minidump_failed = 1;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003159 }
3160}
3161
3162static int
3163qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3164{
3165 uint32_t flash_status;
3166 int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3167 int ret_val = QLA_SUCCESS;
3168
3169 while (retries--) {
3170 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3171 &flash_status);
3172 if (ret_val) {
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003173 ql_log(ql_log_warn, vha, 0xb13c,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003174 "%s: Failed to read FLASH_STATUS reg.\n",
3175 __func__);
3176 break;
3177 }
3178 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3179 QLA8044_FLASH_STATUS_READY)
3180 break;
3181 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3182 }
3183
3184 if (!retries)
3185 ret_val = QLA_FUNCTION_FAILED;
3186
3187 return ret_val;
3188}
3189
3190static int
3191qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3192 uint32_t data)
3193{
3194 int ret_val = QLA_SUCCESS;
3195 uint32_t cmd;
3196
3197 cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3198
3199 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3200 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3201 if (ret_val) {
3202 ql_log(ql_log_warn, vha, 0xb125,
3203 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3204 goto exit_func;
3205 }
3206
3207 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3208 if (ret_val) {
3209 ql_log(ql_log_warn, vha, 0xb126,
3210 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3211 goto exit_func;
3212 }
3213
3214 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3215 QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3216 if (ret_val) {
3217 ql_log(ql_log_warn, vha, 0xb127,
3218 "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3219 goto exit_func;
3220 }
3221
3222 ret_val = qla8044_poll_flash_status_reg(vha);
3223 if (ret_val)
3224 ql_log(ql_log_warn, vha, 0xb128,
3225 "%s: Error polling flash status reg.\n", __func__);
3226
3227exit_func:
3228 return ret_val;
3229}
3230
3231/*
3232 * This function assumes that the flash lock is held.
3233 */
3234static int
3235qla8044_unprotect_flash(scsi_qla_host_t *vha)
3236{
3237 int ret_val;
3238 struct qla_hw_data *ha = vha->hw;
3239
3240 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3241 if (ret_val)
3242 ql_log(ql_log_warn, vha, 0xb139,
3243 "%s: Write flash status failed.\n", __func__);
3244
3245 return ret_val;
3246}
3247
3248/*
3249 * This function assumes that the flash lock is held.
3250 */
3251static int
3252qla8044_protect_flash(scsi_qla_host_t *vha)
3253{
3254 int ret_val;
3255 struct qla_hw_data *ha = vha->hw;
3256
3257 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3258 if (ret_val)
3259 ql_log(ql_log_warn, vha, 0xb13b,
3260 "%s: Write flash status failed.\n", __func__);
3261
3262 return ret_val;
3263}
3264
3265
3266static int
3267qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3268 uint32_t sector_start_addr)
3269{
3270 uint32_t reversed_addr;
3271 int ret_val = QLA_SUCCESS;
3272
3273 ret_val = qla8044_poll_flash_status_reg(vha);
3274 if (ret_val) {
3275 ql_log(ql_log_warn, vha, 0xb12e,
3276 "%s: Poll flash status after erase failed..\n", __func__);
3277 }
3278
3279 reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3280 (sector_start_addr & 0xFF00) |
3281 ((sector_start_addr & 0xFF0000) >> 16));
3282
3283 ret_val = qla8044_wr_reg_indirect(vha,
3284 QLA8044_FLASH_WRDATA, reversed_addr);
3285 if (ret_val) {
3286 ql_log(ql_log_warn, vha, 0xb12f,
3287 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3288 }
3289 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3290 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3291 if (ret_val) {
3292 ql_log(ql_log_warn, vha, 0xb130,
3293 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3294 }
3295 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3296 QLA8044_FLASH_LAST_ERASE_MS_VAL);
3297 if (ret_val) {
3298 ql_log(ql_log_warn, vha, 0xb131,
3299 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3300 }
3301 ret_val = qla8044_poll_flash_status_reg(vha);
3302 if (ret_val) {
3303 ql_log(ql_log_warn, vha, 0xb132,
3304 "%s: Poll flash status failed.\n", __func__);
3305 }
3306
3307
3308 return ret_val;
3309}
3310
3311/*
3312 * qla8044_flash_write_u32 - Write data to flash
3313 *
3314 * @ha : Pointer to adapter structure
3315 * addr : Flash address to write to
3316 * p_data : Data to be written
3317 *
3318 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3319 *
3320 * NOTE: Lock should be held on entry
3321 */
3322static int
3323qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3324 uint32_t *p_data)
3325{
3326 int ret_val = QLA_SUCCESS;
3327
3328 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3329 0x00800000 | (addr >> 2));
3330 if (ret_val) {
3331 ql_log(ql_log_warn, vha, 0xb134,
3332 "%s: Failed write to FLASH_ADDR.\n", __func__);
3333 goto exit_func;
3334 }
3335 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3336 if (ret_val) {
3337 ql_log(ql_log_warn, vha, 0xb135,
3338 "%s: Failed write to FLASH_WRDATA.\n", __func__);
3339 goto exit_func;
3340 }
3341 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3342 if (ret_val) {
3343 ql_log(ql_log_warn, vha, 0xb136,
3344 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3345 goto exit_func;
3346 }
3347 ret_val = qla8044_poll_flash_status_reg(vha);
3348 if (ret_val) {
3349 ql_log(ql_log_warn, vha, 0xb137,
3350 "%s: Poll flash status failed.\n", __func__);
3351 }
3352
3353exit_func:
3354 return ret_val;
3355}
3356
3357static int
3358qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3359 uint32_t faddr, uint32_t dwords)
3360{
3361 int ret = QLA_FUNCTION_FAILED;
3362 uint32_t spi_val;
3363
3364 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3365 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3366 ql_dbg(ql_dbg_user, vha, 0xb123,
3367 "Got unsupported dwords = 0x%x.\n",
3368 dwords);
3369 return QLA_FUNCTION_FAILED;
3370 }
3371
3372 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3373 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3374 spi_val | QLA8044_FLASH_SPI_CTL);
3375 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3376 QLA8044_FLASH_FIRST_TEMP_VAL);
3377
3378 /* First DWORD write to FLASH_WRDATA */
3379 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3380 *dwptr++);
3381 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3382 QLA8044_FLASH_FIRST_MS_PATTERN);
3383
3384 ret = qla8044_poll_flash_status_reg(vha);
3385 if (ret) {
3386 ql_log(ql_log_warn, vha, 0xb124,
3387 "%s: Failed.\n", __func__);
3388 goto exit_func;
3389 }
3390
3391 dwords--;
3392
3393 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3394 QLA8044_FLASH_SECOND_TEMP_VAL);
3395
3396
3397 /* Second to N-1 DWORDS writes */
3398 while (dwords != 1) {
3399 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3400 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3401 QLA8044_FLASH_SECOND_MS_PATTERN);
3402 ret = qla8044_poll_flash_status_reg(vha);
3403 if (ret) {
3404 ql_log(ql_log_warn, vha, 0xb129,
3405 "%s: Failed.\n", __func__);
3406 goto exit_func;
3407 }
3408 dwords--;
3409 }
3410
3411 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3412 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3413
3414 /* Last DWORD write */
3415 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3416 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3417 QLA8044_FLASH_LAST_MS_PATTERN);
3418 ret = qla8044_poll_flash_status_reg(vha);
3419 if (ret) {
3420 ql_log(ql_log_warn, vha, 0xb12a,
3421 "%s: Failed.\n", __func__);
3422 goto exit_func;
3423 }
3424 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3425
3426 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3427 ql_log(ql_log_warn, vha, 0xb12b,
3428 "%s: Failed.\n", __func__);
3429 spi_val = 0;
3430 /* Operation failed, clear error bit. */
3431 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3432 &spi_val);
3433 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3434 spi_val | QLA8044_FLASH_SPI_CTL);
3435 }
3436exit_func:
3437 return ret;
3438}
3439
3440static int
3441qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3442 uint32_t faddr, uint32_t dwords)
3443{
3444 int ret = QLA_FUNCTION_FAILED;
3445 uint32_t liter;
3446
3447 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3448 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3449 if (ret) {
3450 ql_dbg(ql_dbg_p3p, vha, 0xb141,
3451 "%s: flash address=%x data=%x.\n", __func__,
3452 faddr, *dwptr);
3453 break;
3454 }
3455 }
3456
3457 return ret;
3458}
3459
3460int
3461qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3462 uint32_t offset, uint32_t length)
3463{
3464 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3465 int dword_count, erase_sec_count;
3466 uint32_t erase_offset;
3467 uint8_t *p_cache, *p_src;
3468
3469 erase_offset = offset;
3470
3471 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3472 if (!p_cache)
3473 return QLA_FUNCTION_FAILED;
3474
3475 memcpy(p_cache, buf, length);
3476 p_src = p_cache;
3477 dword_count = length / sizeof(uint32_t);
3478 /* Since the offset and legth are sector aligned, it will be always
3479 * multiple of burst_iter_count (64)
3480 */
3481 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3482 erase_sec_count = length / QLA8044_SECTOR_SIZE;
3483
3484 /* Suspend HBA. */
3485 scsi_block_requests(vha->host);
3486 /* Lock and enable write for whole operation. */
3487 qla8044_flash_lock(vha);
3488 qla8044_unprotect_flash(vha);
3489
3490 /* Erasing the sectors */
3491 for (i = 0; i < erase_sec_count; i++) {
3492 rval = qla8044_erase_flash_sector(vha, erase_offset);
3493 ql_dbg(ql_dbg_user, vha, 0xb138,
3494 "Done erase of sector=0x%x.\n",
3495 erase_offset);
3496 if (rval) {
3497 ql_log(ql_log_warn, vha, 0xb121,
3498 "Failed to erase the sector having address: "
3499 "0x%x.\n", erase_offset);
3500 goto out;
3501 }
3502 erase_offset += QLA8044_SECTOR_SIZE;
3503 }
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003504 ql_dbg(ql_dbg_user, vha, 0xb13f,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003505 "Got write for addr = 0x%x length=0x%x.\n",
3506 offset, length);
3507
3508 for (i = 0; i < burst_iter_count; i++) {
3509
3510 /* Go with write. */
3511 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3512 offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3513 if (rval) {
3514 /* Buffer Mode failed skip to dword mode */
3515 ql_log(ql_log_warn, vha, 0xb122,
3516 "Failed to write flash in buffer mode, "
3517 "Reverting to slow-write.\n");
3518 rval = qla8044_write_flash_dword_mode(vha,
3519 (uint32_t *)p_src, offset,
3520 QLA8044_MAX_OPTROM_BURST_DWORDS);
3521 }
3522 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3523 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3524 }
3525 ql_dbg(ql_dbg_user, vha, 0xb133,
3526 "Done writing.\n");
3527
3528out:
3529 qla8044_protect_flash(vha);
3530 qla8044_flash_unlock(vha);
3531 scsi_unblock_requests(vha->host);
3532 kfree(p_cache);
3533
3534 return rval;
3535}
3536
3537#define LEG_INT_PTR_B31 (1 << 31)
3538#define LEG_INT_PTR_B30 (1 << 30)
3539#define PF_BITS_MASK (0xF << 16)
3540/**
3541 * qla8044_intr_handler() - Process interrupts for the ISP8044
3542 * @irq:
3543 * @dev_id: SCSI driver HA context
3544 *
3545 * Called by system whenever the host adapter generates an interrupt.
3546 *
3547 * Returns handled flag.
3548 */
3549irqreturn_t
3550qla8044_intr_handler(int irq, void *dev_id)
3551{
3552 scsi_qla_host_t *vha;
3553 struct qla_hw_data *ha;
3554 struct rsp_que *rsp;
3555 struct device_reg_82xx __iomem *reg;
3556 int status = 0;
3557 unsigned long flags;
3558 unsigned long iter;
3559 uint32_t stat;
3560 uint16_t mb[4];
3561 uint32_t leg_int_ptr = 0, pf_bit;
3562
3563 rsp = (struct rsp_que *) dev_id;
3564 if (!rsp) {
3565 ql_log(ql_log_info, NULL, 0xb143,
3566 "%s(): NULL response queue pointer\n", __func__);
3567 return IRQ_NONE;
3568 }
3569 ha = rsp->hw;
3570 vha = pci_get_drvdata(ha->pdev);
3571
3572 if (unlikely(pci_channel_offline(ha->pdev)))
3573 return IRQ_HANDLED;
3574
3575 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3576
3577 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3578 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3579 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3580 "%s: Legacy Interrupt Bit 31 not set, "
3581 "spurious interrupt!\n", __func__);
3582 return IRQ_NONE;
3583 }
3584
3585 pf_bit = ha->portnum << 16;
3586 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3587 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3588 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3589 "%s: Incorrect function ID 0x%x in "
3590 "legacy interrupt register, "
3591 "ha->pf_bit = 0x%x\n", __func__,
3592 (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3593 return IRQ_NONE;
3594 }
3595
3596 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3597 * Control register and poll till Legacy Interrupt Pointer register
3598 * bit32 is 0.
3599 */
3600 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3601 do {
3602 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3603 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3604 break;
3605 } while (leg_int_ptr & (LEG_INT_PTR_B30));
3606
3607 reg = &ha->iobase->isp82;
3608 spin_lock_irqsave(&ha->hardware_lock, flags);
3609 for (iter = 1; iter--; ) {
3610
3611 if (RD_REG_DWORD(&reg->host_int)) {
3612 stat = RD_REG_DWORD(&reg->host_status);
3613 if ((stat & HSRX_RISC_INT) == 0)
3614 break;
3615
3616 switch (stat & 0xff) {
3617 case 0x1:
3618 case 0x2:
3619 case 0x10:
3620 case 0x11:
3621 qla82xx_mbx_completion(vha, MSW(stat));
3622 status |= MBX_INTERRUPT;
3623 break;
3624 case 0x12:
3625 mb[0] = MSW(stat);
3626 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3627 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3628 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3629 qla2x00_async_event(vha, rsp, mb);
3630 break;
3631 case 0x13:
3632 qla24xx_process_response_queue(vha, rsp);
3633 break;
3634 default:
3635 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3636 "Unrecognized interrupt type "
3637 "(%d).\n", stat & 0xff);
3638 break;
3639 }
3640 }
3641 WRT_REG_DWORD(&reg->host_int, 0);
3642 }
3643
3644 qla2x00_handle_mbx_completion(ha, status);
3645 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3646
3647 return IRQ_HANDLED;
3648}
3649
3650static int
3651qla8044_idc_dontreset(struct qla_hw_data *ha)
3652{
3653 uint32_t idc_ctrl;
3654
3655 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3656 return idc_ctrl & DONTRESET_BIT0;
3657}
3658
3659static void
3660qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3661{
3662 uint32_t drv_state;
3663
3664 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
3665
3666 /*
3667 * For ISP8044, drv_active register has 1 bit per function,
3668 * shift 1 by func_num to set a bit for the function.
3669 * For ISP82xx, drv_active has 4 bits per function
3670 */
3671 drv_state &= ~(1 << vha->hw->portnum);
3672
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003673 ql_dbg(ql_dbg_p3p, vha, 0xb13d,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003674 "drv_state: 0x%08x\n", drv_state);
3675 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
3676}
3677
3678int
3679qla8044_abort_isp(scsi_qla_host_t *vha)
3680{
3681 int rval;
3682 uint32_t dev_state;
3683 struct qla_hw_data *ha = vha->hw;
3684
3685 qla8044_idc_lock(ha);
3686 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3687
3688 if (ql2xdontresethba)
3689 qla8044_set_idc_dontreset(vha);
3690
3691 /* If device_state is NEED_RESET, go ahead with
3692 * Reset,irrespective of ql2xdontresethba. This is to allow a
3693 * non-reset-owner to force a reset. Non-reset-owner sets
3694 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
3695 * and then forces a Reset by setting device_state to
3696 * NEED_RESET. */
3697 if (dev_state == QLA8XXX_DEV_READY) {
3698 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
3699 * recovery */
3700 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003701 ql_dbg(ql_dbg_p3p, vha, 0xb13e,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003702 "Reset recovery disabled\n");
3703 rval = QLA_FUNCTION_FAILED;
3704 goto exit_isp_reset;
3705 }
3706
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003707 ql_dbg(ql_dbg_p3p, vha, 0xb140,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003708 "HW State: NEED RESET\n");
3709 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3710 QLA8XXX_DEV_NEED_RESET);
3711 }
3712
3713 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
3714 * and which drivers are present. Unlike ISP82XX, the function setting
3715 * NEED_RESET, may not be the Reset owner. */
3716 qla83xx_reset_ownership(vha);
3717
3718 qla8044_idc_unlock(ha);
3719 rval = qla8044_device_state_handler(vha);
3720 qla8044_idc_lock(ha);
3721 qla8044_clear_rst_ready(vha);
3722
3723exit_isp_reset:
3724 qla8044_idc_unlock(ha);
3725 if (rval == QLA_SUCCESS) {
3726 ha->flags.isp82xx_fw_hung = 0;
3727 ha->flags.nic_core_reset_hdlr_active = 0;
3728 rval = qla82xx_restart_isp(vha);
3729 }
3730
3731 return rval;
3732}
3733
Chad Dupuisa1b23c52014-02-26 04:15:12 -05003734void
3735qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
3736{
3737 struct qla_hw_data *ha = vha->hw;
3738
3739 if (!ha->allow_cna_fw_dump)
3740 return;
3741
3742 scsi_block_requests(vha->host);
3743 ha->flags.isp82xx_no_md_cap = 1;
3744 qla8044_idc_lock(ha);
3745 qla82xx_set_reset_owner(vha);
3746 qla8044_idc_unlock(ha);
3747 qla2x00_wait_for_chip_reset(vha);
3748 scsi_unblock_requests(vha->host);
3749}