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gerrit-public.fairphone.software / kernel / msm-4.19 / edd052865d029ed4e1b04ebdafbaedcd0f1bcee6 / . / arch / arm / boot / dts / imx51.dtsi
blob: d086e07db654f1c5fe7ef1585b2e4a488e7bff85 [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]15
16/ {
17 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
Sascha Hauere3b73c62013-06-25 15:51:55 +0200[diff] [blame]22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@e0000000 {
33 compatible = "fsl,imx51-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0xe0000000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a8";
70 reg = <0>;
71 clock-latency = <61036>; /* two CLK32 periods */
72 clocks = <&clks 24>;
73 clock-names = "cpu";
74 operating-points = <
75 /* kHz uV (No regulator support) */
76 160000 0
77 800000 0
78 >;
79 };
80 };
81
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]82 soc {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "simple-bus";
86 interrupt-parent = <&tzic>;
87 ranges;
88
Sascha Hauerb5af6b102012-11-12 12:56:00 +0100[diff] [blame]89 ipu: ipu@40000000 {
90 #crtc-cells = <1>;
91 compatible = "fsl,imx51-ipu";
92 reg = <0x40000000 0x20000000>;
93 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]94 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
95 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]96 resets = <&src 2>;
Sascha Hauerb5af6b102012-11-12 12:56:00 +0100[diff] [blame]97 };
98
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]99 aips@70000000 { /* AIPS1 */
100 compatible = "fsl,aips-bus", "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 reg = <0x70000000 0x10000000>;
104 ranges;
105
106 spba@70000000 {
107 compatible = "fsl,spba-bus", "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 reg = <0x70000000 0x40000>;
111 ranges;
112
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]113 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]114 compatible = "fsl,imx51-esdhc";
115 reg = <0x70004000 0x4000>;
116 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]117 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
118 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]119 status = "disabled";
120 };
121
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]122 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]123 compatible = "fsl,imx51-esdhc";
124 reg = <0x70008000 0x4000>;
125 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]126 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
127 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]128 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]129 status = "disabled";
130 };
131
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]132 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]133 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
134 reg = <0x7000c000 0x4000>;
135 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]136 clocks = <&clks 32>, <&clks 33>;
137 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]138 status = "disabled";
139 };
140
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]141 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx51-ecspi";
145 reg = <0x70010000 0x4000>;
146 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]147 clocks = <&clks 51>, <&clks 52>;
148 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]149 status = "disabled";
150 };
151
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]152 ssi2: ssi@70014000 {
153 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
154 reg = <0x70014000 0x4000>;
155 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]156 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]157 fsl,fifo-depth = <15>;
158 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
159 status = "disabled";
160 };
161
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]162 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]163 compatible = "fsl,imx51-esdhc";
164 reg = <0x70020000 0x4000>;
165 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]166 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
167 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]168 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]169 status = "disabled";
170 };
171
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]172 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]173 compatible = "fsl,imx51-esdhc";
174 reg = <0x70024000 0x4000>;
175 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]176 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
177 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]178 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]179 status = "disabled";
180 };
181 };
182
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]183 usbphy0: usbphy@0 {
184 compatible = "usb-nop-xceiv";
185 clocks = <&clks 124>;
186 clock-names = "main_clk";
187 status = "okay";
188 };
189
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]190 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]191 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
192 reg = <0x73f80000 0x0200>;
193 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]194 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]195 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]196 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]197 status = "disabled";
198 };
199
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]200 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]201 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
202 reg = <0x73f80200 0x0200>;
203 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]204 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]205 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]206 status = "disabled";
207 };
208
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]209 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]210 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
211 reg = <0x73f80400 0x0200>;
212 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]213 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]214 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]215 status = "disabled";
216 };
217
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]218 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]219 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
220 reg = <0x73f80600 0x0200>;
221 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]222 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]223 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]224 status = "disabled";
225 };
226
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]227 usbmisc: usbmisc@73f80800 {
228 #index-cells = <1>;
229 compatible = "fsl,imx51-usbmisc";
230 reg = <0x73f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]231 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]232 };
233
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]234 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]235 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]236 reg = <0x73f84000 0x4000>;
237 interrupts = <50 51>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]241 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]242 };
243
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]244 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]245 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]246 reg = <0x73f88000 0x4000>;
247 interrupts = <52 53>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]251 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]252 };
253
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]254 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]255 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]256 reg = <0x73f8c000 0x4000>;
257 interrupts = <54 55>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]261 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]262 };
263
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]264 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]265 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]266 reg = <0x73f90000 0x4000>;
267 interrupts = <56 57>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]271 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]272 };
273
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]274 kpp: kpp@73f94000 {
275 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
276 reg = <0x73f94000 0x4000>;
277 interrupts = <60>;
278 clocks = <&clks 0>;
279 status = "disabled";
280 };
281
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]282 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]283 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
284 reg = <0x73f98000 0x4000>;
285 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]286 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]287 };
288
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]289 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]290 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
291 reg = <0x73f9c000 0x4000>;
292 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]293 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]294 status = "disabled";
295 };
296
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]297 gpt: timer@73fa0000 {
298 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
299 reg = <0x73fa0000 0x4000>;
300 interrupts = <39>;
301 clocks = <&clks 36>, <&clks 41>;
302 clock-names = "ipg", "per";
303 };
304
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]305 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]306 compatible = "fsl,imx51-iomuxc";
307 reg = <0x73fa8000 0x4000>;
308
309 audmux {
310 pinctrl_audmux_1: audmuxgrp-1 {
311 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]312 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
313 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
314 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
315 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]316 >;
317 };
318 };
319
320 fec {
321 pinctrl_fec_1: fecgrp-1 {
322 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]323 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
324 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
325 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
326 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
327 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
328 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
329 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
330 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
331 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
332 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
333 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
334 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
335 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
336 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
337 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
338 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
339 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]340 >;
341 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]342
343 pinctrl_fec_2: fecgrp-2 {
344 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]345 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
346 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
347 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
348 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
349 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
350 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
351 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
352 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
353 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
354 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
355 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
356 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
357 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
358 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
359 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
360 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
361 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
362 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]363 >;
364 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]365 };
366
367 ecspi1 {
368 pinctrl_ecspi1_1: ecspi1grp-1 {
369 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]370 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
371 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
372 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]373 >;
374 };
375 };
376
Gwenhael Goavec-Meroua15ac4a2013-03-09 14:59:08 +0100[diff] [blame]377 ecspi2 {
378 pinctrl_ecspi2_1: ecspi2grp-1 {
379 fsl,pins = <
380 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
381 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
382 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
383 >;
384 };
385 };
386
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]387 esdhc1 {
388 pinctrl_esdhc1_1: esdhc1grp-1 {
389 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]390 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
391 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
392 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
393 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
394 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
395 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]396 >;
397 };
398 };
399
400 esdhc2 {
401 pinctrl_esdhc2_1: esdhc2grp-1 {
402 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]403 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
404 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
405 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
406 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
407 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
408 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]409 >;
410 };
411 };
412
413 i2c2 {
414 pinctrl_i2c2_1: i2c2grp-1 {
415 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]416 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
417 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]418 >;
419 };
Gwenhael Goavec-Merou52c9aa92013-03-09 15:04:19 +0100[diff] [blame]420
421 pinctrl_i2c2_2: i2c2grp-2 {
422 fsl,pins = <
423 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
424 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
425 >;
426 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]427 };
428
Sascha Hauerb5af6b102012-11-12 12:56:00 +0100[diff] [blame]429 ipu_disp1 {
430 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
431 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]432 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
433 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
434 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
435 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
436 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
437 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
438 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
439 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
440 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
441 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
442 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
443 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
444 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
445 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
446 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
447 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
448 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
449 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
450 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
451 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
452 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
453 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
454 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
455 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
456 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
457 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
Sascha Hauerb5af6b102012-11-12 12:56:00 +0100[diff] [blame]458 >;
459 };
460 };
461
462 ipu_disp2 {
463 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
464 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]465 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
466 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
467 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
468 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
469 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
470 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
471 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
472 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
473 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
474 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
475 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
476 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
477 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
478 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
479 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
480 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
481 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
482 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
483 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
484 MX51_PAD_DI_GP4__DI2_PIN15 0x5
Sascha Hauerb5af6b102012-11-12 12:56:00 +0100[diff] [blame]485 >;
486 };
487 };
488
Sascha Hauera9031822013-06-25 15:51:58 +0200[diff] [blame]489 kpp {
490 pinctrl_kpp_1: kppgrp-1 {
491 fsl,pins = <
492 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
493 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
494 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
495 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
496 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
497 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
498 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
499 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
500 >;
501 };
502 };
503
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]504 pata {
505 pinctrl_pata_1: patagrp-1 {
506 fsl,pins = <
507 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
508 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
509 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
510 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
511 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
512 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
513 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
514 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
515 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
516 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
517 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
518 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
519 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
520 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
521 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
522 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
523 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
524 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
525 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
526 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
527 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
528 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
529 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
530 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
531 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
532 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
533 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
534 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
535 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
536 >;
537 };
538 };
539
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]540 uart1 {
541 pinctrl_uart1_1: uart1grp-1 {
542 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]543 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
544 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
545 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
546 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]547 >;
548 };
549 };
550
551 uart2 {
552 pinctrl_uart2_1: uart2grp-1 {
553 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]554 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
555 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]556 >;
557 };
558 };
559
560 uart3 {
561 pinctrl_uart3_1: uart3grp-1 {
562 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]563 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
564 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
565 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
566 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]567 >;
568 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]569
570 pinctrl_uart3_2: uart3grp-2 {
571 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]572 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
573 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]574 >;
575 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]576 };
Sascha Haueraeaa9512013-06-25 15:52:00 +0200[diff] [blame]577
578 usbh1 {
579 pinctrl_usbh1_1: usbh1grp-1 {
580 fsl,pins = <
581 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
582 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
583 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
584 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
585 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
586 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
587 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
588 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
589 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
590 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
591 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
592 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
593 >;
594 };
595 };
596
597 usbh2 {
598 pinctrl_usbh2_1: usbh2grp-1 {
599 fsl,pins = <
600 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
601 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
602 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
603 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
604 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
605 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
606 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
607 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
608 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
609 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
610 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
611 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
612 >;
613 };
614 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]615 };
616
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]617 pwm1: pwm@73fb4000 {
618 #pwm-cells = <2>;
619 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
620 reg = <0x73fb4000 0x4000>;
621 clocks = <&clks 37>, <&clks 38>;
622 clock-names = "ipg", "per";
623 interrupts = <61>;
624 };
625
626 pwm2: pwm@73fb8000 {
627 #pwm-cells = <2>;
628 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
629 reg = <0x73fb8000 0x4000>;
630 clocks = <&clks 39>, <&clks 40>;
631 clock-names = "ipg", "per";
632 interrupts = <94>;
633 };
634
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]635 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]636 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
637 reg = <0x73fbc000 0x4000>;
638 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]639 clocks = <&clks 28>, <&clks 29>;
640 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]641 status = "disabled";
642 };
643
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]644 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]645 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
646 reg = <0x73fc0000 0x4000>;
647 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]648 clocks = <&clks 30>, <&clks 31>;
649 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]650 status = "disabled";
651 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]652
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]653 src: src@73fd0000 {
654 compatible = "fsl,imx51-src";
655 reg = <0x73fd0000 0x4000>;
656 #reset-cells = <1>;
657 };
658
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]659 clks: ccm@73fd4000{
660 compatible = "fsl,imx51-ccm";
661 reg = <0x73fd4000 0x4000>;
662 interrupts = <0 71 0x04 0 72 0x04>;
663 #clock-cells = <1>;
664 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]665 };
666
667 aips@80000000 { /* AIPS2 */
668 compatible = "fsl,aips-bus", "simple-bus";
669 #address-cells = <1>;
670 #size-cells = <1>;
671 reg = <0x80000000 0x10000000>;
672 ranges;
673
Sascha Hauer6510ea252013-06-25 15:51:51 +0200[diff] [blame]674 iim: iim@83f98000 {
675 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
676 reg = <0x83f98000 0x4000>;
677 interrupts = <69>;
678 clocks = <&clks 107>;
679 };
680
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]681 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "fsl,imx51-ecspi";
685 reg = <0x83fac000 0x4000>;
686 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]687 clocks = <&clks 53>, <&clks 54>;
688 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]689 status = "disabled";
690 };
691
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]692 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]693 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
694 reg = <0x83fb0000 0x4000>;
695 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]696 clocks = <&clks 56>, <&clks 56>;
697 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]698 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]699 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]700 };
701
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]702 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]703 #address-cells = <1>;
704 #size-cells = <0>;
705 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
706 reg = <0x83fc0000 0x4000>;
707 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]708 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]709 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]710 status = "disabled";
711 };
712
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]713 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]714 #address-cells = <1>;
715 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]716 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]717 reg = <0x83fc4000 0x4000>;
718 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]719 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]720 status = "disabled";
721 };
722
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]723 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]724 #address-cells = <1>;
725 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]726 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]727 reg = <0x83fc8000 0x4000>;
728 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]729 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]730 status = "disabled";
731 };
732
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]733 ssi1: ssi@83fcc000 {
734 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
735 reg = <0x83fcc000 0x4000>;
736 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]737 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]738 fsl,fifo-depth = <15>;
739 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
740 status = "disabled";
741 };
742
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]743 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]744 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
745 reg = <0x83fd0000 0x4000>;
746 status = "disabled";
747 };
748
Alexander Shiyanedd05282013-07-13 08:30:57 +0400[diff] [blame^]749 weim: weim@83fda000 {
750 #address-cells = <2>;
751 #size-cells = <1>;
752 compatible = "fsl,imx51-weim";
753 reg = <0x83fda000 0x1000>;
754 clocks = <&clks 57>;
755 ranges = <
756 0 0 0xb0000000 0x08000000
757 1 0 0xb8000000 0x08000000
758 2 0 0xc0000000 0x08000000
759 3 0 0xc8000000 0x04000000
760 4 0 0xcc000000 0x02000000
761 5 0 0xce000000 0x02000000
762 >;
763 status = "disabled";
764 };
765
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]766 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]767 compatible = "fsl,imx51-nand";
768 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
769 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]770 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]771 status = "disabled";
772 };
773
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]774 pata: pata@83fe0000 {
775 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
776 reg = <0x83fe0000 0x4000>;
777 interrupts = <70>;
778 clocks = <&clks 161>;
779 status = "disabled";
780 };
781
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]782 ssi3: ssi@83fe8000 {
783 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
784 reg = <0x83fe8000 0x4000>;
785 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]786 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]787 fsl,fifo-depth = <15>;
788 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
789 status = "disabled";
790 };
791
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]792 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]793 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
794 reg = <0x83fec000 0x4000>;
795 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]796 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
797 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]798 status = "disabled";
799 };
800 };
801 };
802};