blob: c924d81f7978f2b01ee391afa38e3461357ab0b1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/video/asiliantfb.c
3 * frame buffer driver for Asiliant 69000 chip
4 * Copyright (C) 2001-2003 Saito.K & Jeanne
5 *
6 * from driver/video/chipsfb.c and,
7 *
8 * drivers/video/asiliantfb.c -- frame buffer device for
9 * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
10 * Author: apc@agelectronics.co.uk
11 * Copyright (C) 2000 AG Electronics
12 * Note: the data sheets don't seem to be available from Asiliant.
13 * They are available by searching developer.intel.com, but are not otherwise
14 * linked to.
15 *
16 * This driver should be portable with minimal effort to the 69000 display
17 * chip, and to the twin-display mode of the 69030.
18 * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
19 *
20 * Derived from the CT65550 driver chipsfb.c:
21 * Copyright (C) 1998 Paul Mackerras
22 * ...which was derived from the Powermac "chips" driver:
23 * Copyright (C) 1997 Fabio Riccardi.
24 * And from the frame buffer device for Open Firmware-initialized devices:
25 * Copyright (C) 1997 Geert Uytterhoeven.
26 *
27 * This file is subject to the terms and conditions of the GNU General Public
28 * License. See the file COPYING in the main directory of this archive for
29 * more details.
30 */
31
32#include <linux/config.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/errno.h>
36#include <linux/string.h>
37#include <linux/mm.h>
38#include <linux/tty.h>
39#include <linux/slab.h>
40#include <linux/vmalloc.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/fb.h>
44#include <linux/init.h>
45#include <linux/pci.h>
46#include <asm/io.h>
47
48/* Built in clock of the 69030 */
49static const unsigned Fref = 14318180;
50
51#define mmio_base (p->screen_base + 0x400000)
52
53#define mm_write_ind(num, val, ap, dp) do { \
54 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
55} while (0)
56
57static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
58{
59 mm_write_ind(reg, data, 0x7ac, 0x7ad);
60}
61#define write_xr(num, val) mm_write_xr(p, num, val)
62
63static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
64{
65 mm_write_ind(reg, data, 0x7a0, 0x7a1);
66}
67#define write_fr(num, val) mm_write_fr(p, num, val)
68
69static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
70{
71 mm_write_ind(reg, data, 0x7a8, 0x7a9);
72}
73#define write_cr(num, val) mm_write_cr(p, num, val)
74
75static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
76{
77 mm_write_ind(reg, data, 0x79c, 0x79d);
78}
79#define write_gr(num, val) mm_write_gr(p, num, val)
80
81static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
82{
83 mm_write_ind(reg, data, 0x788, 0x789);
84}
85#define write_sr(num, val) mm_write_sr(p, num, val)
86
87static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
88{
89 readb(mmio_base + 0x7b4);
90 mm_write_ind(reg, data, 0x780, 0x780);
91}
92#define write_ar(num, val) mm_write_ar(p, num, val)
93
94static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
95static int asiliantfb_check_var(struct fb_var_screeninfo *var,
96 struct fb_info *info);
97static int asiliantfb_set_par(struct fb_info *info);
98static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
99 u_int transp, struct fb_info *info);
100
101static struct fb_ops asiliantfb_ops = {
102 .owner = THIS_MODULE,
103 .fb_check_var = asiliantfb_check_var,
104 .fb_set_par = asiliantfb_set_par,
105 .fb_setcolreg = asiliantfb_setcolreg,
106 .fb_fillrect = cfb_fillrect,
107 .fb_copyarea = cfb_copyarea,
108 .fb_imageblit = cfb_imageblit,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109};
110
111/* Calculate the ratios for the dot clocks without using a single long long
112 * value */
113static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
114{
115 unsigned pixclock = *ppixclock;
116 unsigned Ftarget = 1000000 * (1000000 / pixclock);
117 unsigned n;
118 unsigned best_error = 0xffffffff;
119 unsigned best_m = 0xffffffff,
120 best_n = 0xffffffff;
121 unsigned ratio;
122 unsigned remainder;
123 unsigned char divisor = 0;
124
125 /* Calculate the frequency required. This is hard enough. */
126 ratio = 1000000 / pixclock;
127 remainder = 1000000 % pixclock;
128 Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
129
130 while (Ftarget < 100000000) {
131 divisor += 0x10;
132 Ftarget <<= 1;
133 }
134
135 ratio = Ftarget / Fref;
136 remainder = Ftarget % Fref;
137
138 /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
139 * together with 3 <= n <= 257. */
140 for (n = 3; n <= 257; n++) {
141 unsigned m = n * ratio + (n * remainder) / Fref;
142
143 /* 3 <= m <= 257 */
144 if (m >= 3 && m <= 257) {
145 unsigned new_error = ((Ftarget * n) - (Fref * m)) >= 0 ?
146 ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
147 if (new_error < best_error) {
148 best_n = n;
149 best_m = m;
150 best_error = new_error;
151 }
152 }
153 /* But if VLD = 4, then 4m <= 1028 */
154 else if (m <= 1028) {
155 /* remember there are still only 8-bits of precision in m, so
156 * avoid over-optimistic error calculations */
157 unsigned new_error = ((Ftarget * n) - (Fref * (m & ~3))) >= 0 ?
158 ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
159 if (new_error < best_error) {
160 best_n = n;
161 best_m = m;
162 best_error = new_error;
163 }
164 }
165 }
166 if (best_m > 257)
167 best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
168 else
169 divisor |= 4; /* or set VCO loop divide to 1 */
170 *dclk2_m = best_m - 2;
171 *dclk2_n = best_n - 2;
172 *dclk2_div = divisor;
173 *ppixclock = pixclock;
174 return;
175}
176
177static void asiliant_set_timing(struct fb_info *p)
178{
179 unsigned hd = p->var.xres / 8;
180 unsigned hs = (p->var.xres + p->var.right_margin) / 8;
181 unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
182 unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
183 unsigned vd = p->var.yres;
184 unsigned vs = p->var.yres + p->var.lower_margin;
185 unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
186 unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
187 unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
188
189 if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
190 write_fr(0x01, 0x02); /* LCD */
191 } else {
192 write_fr(0x01, 0x01); /* CRT */
193 }
194
195 write_cr(0x11, (ve - 1) & 0x0f);
196 write_cr(0x00, (ht - 5) & 0xff);
197 write_cr(0x01, hd - 1);
198 write_cr(0x02, hd);
199 write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
200 write_cr(0x04, hs);
201 write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
202 write_cr(0x3c, (ht - 1) & 0xc0);
203 write_cr(0x06, (vt - 2) & 0xff);
204 write_cr(0x30, (vt - 2) >> 8);
205 write_cr(0x07, 0x00);
206 write_cr(0x08, 0x00);
207 write_cr(0x09, 0x00);
208 write_cr(0x10, (vs - 1) & 0xff);
209 write_cr(0x32, ((vs - 1) >> 8) & 0xf);
210 write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
211 write_cr(0x12, (vd - 1) & 0xff);
212 write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
213 write_cr(0x13, wd & 0xff);
214 write_cr(0x41, (wd & 0xf00) >> 8);
215 write_cr(0x15, (vs - 1) & 0xff);
216 write_cr(0x33, ((vs - 1) >> 8) & 0xf);
217 write_cr(0x38, ((ht - 5) & 0x100) >> 8);
218 write_cr(0x16, (vt - 1) & 0xff);
219 write_cr(0x18, 0x00);
220
221 if (p->var.xres == 640) {
222 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
223 } else {
224 writeb(0x07, mmio_base + 0x784); /* set misc output reg */
225 }
226}
227
228static int asiliantfb_check_var(struct fb_var_screeninfo *var,
229 struct fb_info *p)
230{
231 unsigned long Ftarget, ratio, remainder;
232
233 ratio = 1000000 / var->pixclock;
234 remainder = 1000000 % var->pixclock;
235 Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
236
237 /* First check the constraint that the maximum post-VCO divisor is 32,
238 * and the maximum Fvco is 220MHz */
239 if (Ftarget > 220000000 || Ftarget < 3125000) {
240 printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
241 return -ENXIO;
242 }
243 var->xres_virtual = var->xres;
244 var->yres_virtual = var->yres;
245
246 if (var->bits_per_pixel == 24) {
247 var->red.offset = 16;
248 var->green.offset = 8;
249 var->blue.offset = 0;
250 var->red.length = var->blue.length = var->green.length = 8;
251 } else if (var->bits_per_pixel == 16) {
252 switch (var->red.offset) {
253 case 11:
254 var->green.length = 6;
255 break;
256 case 10:
257 var->green.length = 5;
258 break;
259 default:
260 return -EINVAL;
261 }
262 var->green.offset = 5;
263 var->blue.offset = 0;
264 var->red.length = var->blue.length = 5;
265 } else if (var->bits_per_pixel == 8) {
266 var->red.offset = var->green.offset = var->blue.offset = 0;
267 var->red.length = var->green.length = var->blue.length = 8;
268 }
269 return 0;
270}
271
272static int asiliantfb_set_par(struct fb_info *p)
273{
274 u8 dclk2_m; /* Holds m-2 value for register */
275 u8 dclk2_n; /* Holds n-2 value for register */
276 u8 dclk2_div; /* Holds divisor bitmask */
277
278 /* Set pixclock */
279 asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
280
281 /* Set color depth */
282 if (p->var.bits_per_pixel == 24) {
283 write_xr(0x81, 0x16); /* 24 bit packed color mode */
284 write_xr(0x82, 0x00); /* Disable palettes */
285 write_xr(0x20, 0x20); /* 24 bit blitter mode */
286 } else if (p->var.bits_per_pixel == 16) {
287 if (p->var.red.offset == 11)
288 write_xr(0x81, 0x15); /* 16 bit color mode */
289 else
290 write_xr(0x81, 0x14); /* 15 bit color mode */
291 write_xr(0x82, 0x00); /* Disable palettes */
292 write_xr(0x20, 0x10); /* 16 bit blitter mode */
293 } else if (p->var.bits_per_pixel == 8) {
294 write_xr(0x0a, 0x02); /* Linear */
295 write_xr(0x81, 0x12); /* 8 bit color mode */
296 write_xr(0x82, 0x00); /* Graphics gamma enable */
297 write_xr(0x20, 0x00); /* 8 bit blitter mode */
298 }
299 p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
300 p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
301 write_xr(0xc4, dclk2_m);
302 write_xr(0xc5, dclk2_n);
303 write_xr(0xc7, dclk2_div);
304 /* Set up the CR registers */
305 asiliant_set_timing(p);
306 return 0;
307}
308
309static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
310 u_int transp, struct fb_info *p)
311{
312 if (regno > 255)
313 return 1;
314 red >>= 8;
315 green >>= 8;
316 blue >>= 8;
317
318 /* Set hardware palete */
319 writeb(regno, mmio_base + 0x790);
320 udelay(1);
321 writeb(red, mmio_base + 0x791);
322 writeb(green, mmio_base + 0x791);
323 writeb(blue, mmio_base + 0x791);
324
Antonino A. Daplasee713052006-02-24 13:04:20 -0800325 if (regno < 16) {
326 switch(p->var.red.offset) {
327 case 10: /* RGB 555 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 ((u32 *)(p->pseudo_palette))[regno] =
329 ((red & 0xf8) << 7) |
330 ((green & 0xf8) << 2) |
331 ((blue & 0xf8) >> 3);
Antonino A. Daplasee713052006-02-24 13:04:20 -0800332 break;
333 case 11: /* RGB 565 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 ((u32 *)(p->pseudo_palette))[regno] =
335 ((red & 0xf8) << 8) |
336 ((green & 0xfc) << 3) |
337 ((blue & 0xf8) >> 3);
Antonino A. Daplasee713052006-02-24 13:04:20 -0800338 break;
339 case 16: /* RGB 888 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 ((u32 *)(p->pseudo_palette))[regno] =
341 (red << 16) |
342 (green << 8) |
343 (blue);
Antonino A. Daplasee713052006-02-24 13:04:20 -0800344 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 }
Antonino A. Daplasee713052006-02-24 13:04:20 -0800347
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 return 0;
349}
350
351struct chips_init_reg {
352 unsigned char addr;
353 unsigned char data;
354};
355
356#define N_ELTS(x) (sizeof(x) / sizeof(x[0]))
357
358static struct chips_init_reg chips_init_sr[] =
359{
360 {0x00, 0x03}, /* Reset register */
361 {0x01, 0x01}, /* Clocking mode */
362 {0x02, 0x0f}, /* Plane mask */
363 {0x04, 0x0e} /* Memory mode */
364};
365
366static struct chips_init_reg chips_init_gr[] =
367{
368 {0x03, 0x00}, /* Data rotate */
369 {0x05, 0x00}, /* Graphics mode */
370 {0x06, 0x01}, /* Miscellaneous */
371 {0x08, 0x00} /* Bit mask */
372};
373
374static struct chips_init_reg chips_init_ar[] =
375{
376 {0x10, 0x01}, /* Mode control */
377 {0x11, 0x00}, /* Overscan */
378 {0x12, 0x0f}, /* Memory plane enable */
379 {0x13, 0x00} /* Horizontal pixel panning */
380};
381
382static struct chips_init_reg chips_init_cr[] =
383{
384 {0x0c, 0x00}, /* Start address high */
385 {0x0d, 0x00}, /* Start address low */
386 {0x40, 0x00}, /* Extended Start Address */
387 {0x41, 0x00}, /* Extended Start Address */
388 {0x14, 0x00}, /* Underline location */
389 {0x17, 0xe3}, /* CRT mode control */
390 {0x70, 0x00} /* Interlace control */
391};
392
393
394static struct chips_init_reg chips_init_fr[] =
395{
396 {0x01, 0x02},
397 {0x03, 0x08},
398 {0x08, 0xcc},
399 {0x0a, 0x08},
400 {0x18, 0x00},
401 {0x1e, 0x80},
402 {0x40, 0x83},
403 {0x41, 0x00},
404 {0x48, 0x13},
405 {0x4d, 0x60},
406 {0x4e, 0x0f},
407
408 {0x0b, 0x01},
409
410 {0x21, 0x51},
411 {0x22, 0x1d},
412 {0x23, 0x5f},
413 {0x20, 0x4f},
414 {0x34, 0x00},
415 {0x24, 0x51},
416 {0x25, 0x00},
417 {0x27, 0x0b},
418 {0x26, 0x00},
419 {0x37, 0x80},
420 {0x33, 0x0b},
421 {0x35, 0x11},
422 {0x36, 0x02},
423 {0x31, 0xea},
424 {0x32, 0x0c},
425 {0x30, 0xdf},
426 {0x10, 0x0c},
427 {0x11, 0xe0},
428 {0x12, 0x50},
429 {0x13, 0x00},
430 {0x16, 0x03},
431 {0x17, 0xbd},
432 {0x1a, 0x00},
433};
434
435
436static struct chips_init_reg chips_init_xr[] =
437{
438 {0xce, 0x00}, /* set default memory clock */
439 {0xcc, 200 }, /* MCLK ratio M */
440 {0xcd, 18 }, /* MCLK ratio N */
441 {0xce, 0x90}, /* MCLK divisor = 2 */
442
443 {0xc4, 209 },
444 {0xc5, 118 },
445 {0xc7, 32 },
446 {0xcf, 0x06},
447 {0x09, 0x01}, /* IO Control - CRT controller extensions */
448 {0x0a, 0x02}, /* Frame buffer mapping */
449 {0x0b, 0x01}, /* PCI burst write */
450 {0x40, 0x03}, /* Memory access control */
451 {0x80, 0x82}, /* Pixel pipeline configuration 0 */
452 {0x81, 0x12}, /* Pixel pipeline configuration 1 */
453 {0x82, 0x08}, /* Pixel pipeline configuration 2 */
454
455 {0xd0, 0x0f},
456 {0xd1, 0x01},
457};
458
459static void __devinit chips_hw_init(struct fb_info *p)
460{
461 int i;
462
463 for (i = 0; i < N_ELTS(chips_init_xr); ++i)
464 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
465 write_xr(0x81, 0x12);
466 write_xr(0x82, 0x08);
467 write_xr(0x20, 0x00);
468 for (i = 0; i < N_ELTS(chips_init_sr); ++i)
469 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
470 for (i = 0; i < N_ELTS(chips_init_gr); ++i)
471 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
472 for (i = 0; i < N_ELTS(chips_init_ar); ++i)
473 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
474 /* Enable video output in attribute index register */
475 writeb(0x20, mmio_base + 0x780);
476 for (i = 0; i < N_ELTS(chips_init_cr); ++i)
477 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
478 for (i = 0; i < N_ELTS(chips_init_fr); ++i)
479 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
480}
481
482static struct fb_fix_screeninfo asiliantfb_fix __devinitdata = {
483 .id = "Asiliant 69000",
484 .type = FB_TYPE_PACKED_PIXELS,
485 .visual = FB_VISUAL_PSEUDOCOLOR,
486 .accel = FB_ACCEL_NONE,
487 .line_length = 640,
488 .smem_len = 0x200000, /* 2MB */
489};
490
491static struct fb_var_screeninfo asiliantfb_var __devinitdata = {
492 .xres = 640,
493 .yres = 480,
494 .xres_virtual = 640,
495 .yres_virtual = 480,
496 .bits_per_pixel = 8,
497 .red = { .length = 8 },
498 .green = { .length = 8 },
499 .blue = { .length = 8 },
500 .height = -1,
501 .width = -1,
502 .vmode = FB_VMODE_NONINTERLACED,
503 .pixclock = 39722,
504 .left_margin = 48,
505 .right_margin = 16,
506 .upper_margin = 33,
507 .lower_margin = 10,
508 .hsync_len = 96,
509 .vsync_len = 2,
510};
511
512static void __devinit init_asiliant(struct fb_info *p, unsigned long addr)
513{
514 p->fix = asiliantfb_fix;
515 p->fix.smem_start = addr;
516 p->var = asiliantfb_var;
517 p->fbops = &asiliantfb_ops;
518 p->flags = FBINFO_DEFAULT;
519
520 fb_alloc_cmap(&p->cmap, 256, 0);
521
522 if (register_framebuffer(p) < 0) {
523 printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
524 return;
525 }
526
527 printk(KERN_INFO "fb%d: Asiliant 69000 frame buffer (%dK RAM detected)\n",
528 p->node, p->fix.smem_len / 1024);
529
530 writeb(0xff, mmio_base + 0x78c);
531 chips_hw_init(p);
532}
533
534static int __devinit
535asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
536{
537 unsigned long addr, size;
538 struct fb_info *p;
539
540 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
541 return -ENODEV;
542 addr = pci_resource_start(dp, 0);
543 size = pci_resource_len(dp, 0);
544 if (addr == 0)
545 return -ENODEV;
546 if (!request_mem_region(addr, size, "asiliantfb"))
547 return -EBUSY;
548
Antonino A. Daplas2a9f6172006-01-09 20:53:05 -0800549 p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 if (!p) {
551 release_mem_region(addr, size);
552 return -ENOMEM;
553 }
554 p->pseudo_palette = p->par;
555 p->par = NULL;
556
557 p->screen_base = ioremap(addr, 0x800000);
558 if (p->screen_base == NULL) {
559 release_mem_region(addr, size);
560 framebuffer_release(p);
561 return -ENOMEM;
562 }
563
564 pci_write_config_dword(dp, 4, 0x02800083);
565 writeb(3, p->screen_base + 0x400784);
566
567 init_asiliant(p, addr);
568
569 pci_set_drvdata(dp, p);
570 return 0;
571}
572
573static void __devexit asiliantfb_remove(struct pci_dev *dp)
574{
575 struct fb_info *p = pci_get_drvdata(dp);
576
577 unregister_framebuffer(p);
578 iounmap(p->screen_base);
579 release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
580 pci_set_drvdata(dp, NULL);
581 framebuffer_release(p);
582}
583
584static struct pci_device_id asiliantfb_pci_tbl[] __devinitdata = {
585 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
586 { 0 }
587};
588
589MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
590
591static struct pci_driver asiliantfb_driver = {
592 .name = "asiliantfb",
593 .id_table = asiliantfb_pci_tbl,
594 .probe = asiliantfb_pci_init,
595 .remove = __devexit_p(asiliantfb_remove),
596};
597
598static int __init asiliantfb_init(void)
599{
600 if (fb_get_options("asiliantfb", NULL))
601 return -ENODEV;
602
603 return pci_register_driver(&asiliantfb_driver);
604}
605
606module_init(asiliantfb_init);
607
608static void __exit asiliantfb_exit(void)
609{
610 pci_unregister_driver(&asiliantfb_driver);
611}
612
613MODULE_LICENSE("GPL");