| Vinayak Kale | ee877b5 | 2013-04-24 10:07:00 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC |
| 3 | * |
| 4 | * Copyright (C) 2013, Applied Micro Circuits Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | / { |
| 13 | compatible = "apm,xgene-storm"; |
| 14 | interrupt-parent = <&gic>; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <2>; |
| 20 | #size-cells = <0>; |
| 21 | |
| 22 | cpu@000 { |
| 23 | device_type = "cpu"; |
| 24 | compatible = "apm,potenza", "arm,armv8"; |
| 25 | reg = <0x0 0x000>; |
| 26 | enable-method = "spin-table"; |
| 27 | cpu-release-addr = <0x1 0x0000fff8>; |
| 28 | }; |
| 29 | cpu@001 { |
| 30 | device_type = "cpu"; |
| 31 | compatible = "apm,potenza", "arm,armv8"; |
| 32 | reg = <0x0 0x001>; |
| 33 | enable-method = "spin-table"; |
| 34 | cpu-release-addr = <0x1 0x0000fff8>; |
| 35 | }; |
| 36 | cpu@100 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "apm,potenza", "arm,armv8"; |
| 39 | reg = <0x0 0x100>; |
| 40 | enable-method = "spin-table"; |
| 41 | cpu-release-addr = <0x1 0x0000fff8>; |
| 42 | }; |
| 43 | cpu@101 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "apm,potenza", "arm,armv8"; |
| 46 | reg = <0x0 0x101>; |
| 47 | enable-method = "spin-table"; |
| 48 | cpu-release-addr = <0x1 0x0000fff8>; |
| 49 | }; |
| 50 | cpu@200 { |
| 51 | device_type = "cpu"; |
| 52 | compatible = "apm,potenza", "arm,armv8"; |
| 53 | reg = <0x0 0x200>; |
| 54 | enable-method = "spin-table"; |
| 55 | cpu-release-addr = <0x1 0x0000fff8>; |
| 56 | }; |
| 57 | cpu@201 { |
| 58 | device_type = "cpu"; |
| 59 | compatible = "apm,potenza", "arm,armv8"; |
| 60 | reg = <0x0 0x201>; |
| 61 | enable-method = "spin-table"; |
| 62 | cpu-release-addr = <0x1 0x0000fff8>; |
| 63 | }; |
| 64 | cpu@300 { |
| 65 | device_type = "cpu"; |
| 66 | compatible = "apm,potenza", "arm,armv8"; |
| 67 | reg = <0x0 0x300>; |
| 68 | enable-method = "spin-table"; |
| 69 | cpu-release-addr = <0x1 0x0000fff8>; |
| 70 | }; |
| 71 | cpu@301 { |
| 72 | device_type = "cpu"; |
| 73 | compatible = "apm,potenza", "arm,armv8"; |
| 74 | reg = <0x0 0x301>; |
| 75 | enable-method = "spin-table"; |
| 76 | cpu-release-addr = <0x1 0x0000fff8>; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | gic: interrupt-controller@78010000 { |
| 81 | compatible = "arm,cortex-a15-gic"; |
| 82 | #interrupt-cells = <3>; |
| 83 | interrupt-controller; |
| 84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ |
| 85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ |
| 86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ |
| 87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ |
| 88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ |
| 89 | }; |
| 90 | |
| 91 | timer { |
| 92 | compatible = "arm,armv8-timer"; |
| 93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ |
| 94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ |
| 95 | <1 14 0xff01>, /* Virt IRQ */ |
| 96 | <1 15 0xff01>; /* Hyp IRQ */ |
| 97 | clock-frequency = <50000000>; |
| 98 | }; |
| 99 | |
| 100 | soc { |
| 101 | compatible = "simple-bus"; |
| 102 | #address-cells = <2>; |
| 103 | #size-cells = <2>; |
| 104 | ranges; |
| 105 | |
| 106 | serial0: serial@1c020000 { |
| 107 | device_type = "serial"; |
| 108 | compatible = "ns16550"; |
| 109 | reg = <0 0x1c020000 0x0 0x1000>; |
| 110 | reg-shift = <2>; |
| 111 | clock-frequency = <10000000>; /* Updated by bootloader */ |
| 112 | interrupt-parent = <&gic>; |
| 113 | interrupts = <0x0 0x4c 0x4>; |
| 114 | }; |
| 115 | }; |
| 116 | }; |