Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the SH73A0 SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | /include/ "skeleton.dtsi" |
| 12 | |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 13 | #include <dt-bindings/clock/sh73a0-clock.h> |
Geert Uytterhoeven | 3022574 | 2015-02-17 15:52:39 +0100 | [diff] [blame] | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 17 | / { |
| 18 | compatible = "renesas,sh73a0"; |
Geert Uytterhoeven | f170b97 | 2014-08-20 16:28:34 +0200 | [diff] [blame] | 19 | interrupt-parent = <&gic>; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 20 | |
| 21 | cpus { |
Simon Horman | c5795ae | 2013-01-28 09:41:40 +0900 | [diff] [blame] | 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; |
| 24 | |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 25 | cpu@0 { |
Simon Horman | c5795ae | 2013-01-28 09:41:40 +0900 | [diff] [blame] | 26 | device_type = "cpu"; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 27 | compatible = "arm,cortex-a9"; |
Simon Horman | c5795ae | 2013-01-28 09:41:40 +0900 | [diff] [blame] | 28 | reg = <0>; |
Magnus Damm | 13bd825 | 2014-08-20 22:02:19 +0900 | [diff] [blame] | 29 | clock-frequency = <1196000000>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 30 | power-domains = <&pd_a2sl>; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 31 | }; |
| 32 | cpu@1 { |
Simon Horman | c5795ae | 2013-01-28 09:41:40 +0900 | [diff] [blame] | 33 | device_type = "cpu"; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 34 | compatible = "arm,cortex-a9"; |
Simon Horman | c5795ae | 2013-01-28 09:41:40 +0900 | [diff] [blame] | 35 | reg = <1>; |
Magnus Damm | 13bd825 | 2014-08-20 22:02:19 +0900 | [diff] [blame] | 36 | clock-frequency = <1196000000>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 37 | power-domains = <&pd_a2sl>; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 38 | }; |
| 39 | }; |
| 40 | |
Geert Uytterhoeven | 3022574 | 2015-02-17 15:52:39 +0100 | [diff] [blame] | 41 | timer@f0000600 { |
| 42 | compatible = "arm,cortex-a9-twd-timer"; |
| 43 | reg = <0xf0000600 0x20>; |
| 44 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 45 | clocks = <&twd_clk>; |
| 46 | }; |
| 47 | |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 48 | gic: interrupt-controller@f0001000 { |
| 49 | compatible = "arm,cortex-a9-gic"; |
| 50 | #interrupt-cells = <3>; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 51 | interrupt-controller; |
| 52 | reg = <0xf0001000 0x1000>, |
| 53 | <0xf0000100 0x100>; |
| 54 | }; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 55 | |
Geert Uytterhoeven | 29828c8 | 2015-01-14 12:13:02 +0100 | [diff] [blame] | 56 | sbsc2: memory-controller@fb400000 { |
| 57 | compatible = "renesas,sbsc-sh73a0"; |
| 58 | reg = <0xfb400000 0x400>; |
| 59 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 61 | interrupt-names = "sec", "temp"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 62 | power-domains = <&pd_a4bc1>; |
Geert Uytterhoeven | 29828c8 | 2015-01-14 12:13:02 +0100 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | sbsc1: memory-controller@fe400000 { |
| 66 | compatible = "renesas,sbsc-sh73a0"; |
| 67 | reg = <0xfe400000 0x400>; |
| 68 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 70 | interrupt-names = "sec", "temp"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 71 | power-domains = <&pd_a4bc0>; |
Geert Uytterhoeven | 29828c8 | 2015-01-14 12:13:02 +0100 | [diff] [blame] | 72 | }; |
| 73 | |
Magnus Damm | 4c90483 | 2013-07-24 12:45:03 +0900 | [diff] [blame] | 74 | pmu { |
| 75 | compatible = "arm,cortex-a9-pmu"; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 76 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <0 56 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | 4c90483 | 2013-07-24 12:45:03 +0900 | [diff] [blame] | 78 | }; |
| 79 | |
Ulrich Hecht | 6a5336a | 2014-09-08 09:57:06 +0900 | [diff] [blame] | 80 | cmt1: timer@e6138000 { |
| 81 | compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; |
| 82 | reg = <0xe6138000 0x200>; |
| 83 | interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 84 | clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |
| 85 | clock-names = "fck"; |
| 86 | power-domains = <&pd_c5>; |
Ulrich Hecht | 6a5336a | 2014-09-08 09:57:06 +0900 | [diff] [blame] | 87 | |
| 88 | renesas,channels-mask = <0x3f>; |
| 89 | |
| 90 | status = "disabled"; |
| 91 | }; |
| 92 | |
Geert Uytterhoeven | 4239bae | 2015-04-27 14:55:30 +0200 | [diff] [blame] | 93 | irqpin0: interrupt-controller@e6900000 { |
Magnus Damm | 8bb4444 | 2013-11-28 08:14:57 +0900 | [diff] [blame] | 94 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 95 | #interrupt-cells = <2>; |
| 96 | interrupt-controller; |
| 97 | reg = <0xe6900000 4>, |
| 98 | <0xe6900010 4>, |
| 99 | <0xe6900020 1>, |
| 100 | <0xe6900040 1>, |
| 101 | <0xe6900060 1>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 102 | interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH |
| 103 | 0 2 IRQ_TYPE_LEVEL_HIGH |
| 104 | 0 3 IRQ_TYPE_LEVEL_HIGH |
| 105 | 0 4 IRQ_TYPE_LEVEL_HIGH |
| 106 | 0 5 IRQ_TYPE_LEVEL_HIGH |
| 107 | 0 6 IRQ_TYPE_LEVEL_HIGH |
| 108 | 0 7 IRQ_TYPE_LEVEL_HIGH |
| 109 | 0 8 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 56a215d | 2015-01-06 20:56:05 +0100 | [diff] [blame] | 110 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 111 | power-domains = <&pd_a4s>; |
Laurent Pinchart | 48bdf06 | 2015-01-06 20:42:04 +0100 | [diff] [blame] | 112 | control-parent; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 113 | }; |
| 114 | |
Geert Uytterhoeven | 4239bae | 2015-04-27 14:55:30 +0200 | [diff] [blame] | 115 | irqpin1: interrupt-controller@e6900004 { |
Magnus Damm | 8bb4444 | 2013-11-28 08:14:57 +0900 | [diff] [blame] | 116 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 117 | #interrupt-cells = <2>; |
| 118 | interrupt-controller; |
| 119 | reg = <0xe6900004 4>, |
| 120 | <0xe6900014 4>, |
| 121 | <0xe6900024 1>, |
| 122 | <0xe6900044 1>, |
| 123 | <0xe6900064 1>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 124 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH |
| 125 | 0 10 IRQ_TYPE_LEVEL_HIGH |
| 126 | 0 11 IRQ_TYPE_LEVEL_HIGH |
| 127 | 0 12 IRQ_TYPE_LEVEL_HIGH |
| 128 | 0 13 IRQ_TYPE_LEVEL_HIGH |
| 129 | 0 14 IRQ_TYPE_LEVEL_HIGH |
| 130 | 0 15 IRQ_TYPE_LEVEL_HIGH |
| 131 | 0 16 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 56a215d | 2015-01-06 20:56:05 +0100 | [diff] [blame] | 132 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 133 | power-domains = <&pd_a4s>; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 134 | control-parent; |
| 135 | }; |
| 136 | |
Geert Uytterhoeven | 4239bae | 2015-04-27 14:55:30 +0200 | [diff] [blame] | 137 | irqpin2: interrupt-controller@e6900008 { |
Magnus Damm | 8bb4444 | 2013-11-28 08:14:57 +0900 | [diff] [blame] | 138 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 139 | #interrupt-cells = <2>; |
| 140 | interrupt-controller; |
| 141 | reg = <0xe6900008 4>, |
| 142 | <0xe6900018 4>, |
| 143 | <0xe6900028 1>, |
| 144 | <0xe6900048 1>, |
| 145 | <0xe6900068 1>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 146 | interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH |
| 147 | 0 18 IRQ_TYPE_LEVEL_HIGH |
| 148 | 0 19 IRQ_TYPE_LEVEL_HIGH |
| 149 | 0 20 IRQ_TYPE_LEVEL_HIGH |
| 150 | 0 21 IRQ_TYPE_LEVEL_HIGH |
| 151 | 0 22 IRQ_TYPE_LEVEL_HIGH |
| 152 | 0 23 IRQ_TYPE_LEVEL_HIGH |
| 153 | 0 24 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 56a215d | 2015-01-06 20:56:05 +0100 | [diff] [blame] | 154 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 155 | power-domains = <&pd_a4s>; |
Laurent Pinchart | 48bdf06 | 2015-01-06 20:42:04 +0100 | [diff] [blame] | 156 | control-parent; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 157 | }; |
| 158 | |
Geert Uytterhoeven | 4239bae | 2015-04-27 14:55:30 +0200 | [diff] [blame] | 159 | irqpin3: interrupt-controller@e690000c { |
Magnus Damm | 8bb4444 | 2013-11-28 08:14:57 +0900 | [diff] [blame] | 160 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 161 | #interrupt-cells = <2>; |
| 162 | interrupt-controller; |
| 163 | reg = <0xe690000c 4>, |
| 164 | <0xe690001c 4>, |
| 165 | <0xe690002c 1>, |
| 166 | <0xe690004c 1>, |
| 167 | <0xe690006c 1>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 168 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH |
| 169 | 0 26 IRQ_TYPE_LEVEL_HIGH |
| 170 | 0 27 IRQ_TYPE_LEVEL_HIGH |
| 171 | 0 28 IRQ_TYPE_LEVEL_HIGH |
| 172 | 0 29 IRQ_TYPE_LEVEL_HIGH |
| 173 | 0 30 IRQ_TYPE_LEVEL_HIGH |
| 174 | 0 31 IRQ_TYPE_LEVEL_HIGH |
| 175 | 0 32 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 56a215d | 2015-01-06 20:56:05 +0100 | [diff] [blame] | 176 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 177 | power-domains = <&pd_a4s>; |
Laurent Pinchart | 48bdf06 | 2015-01-06 20:42:04 +0100 | [diff] [blame] | 178 | control-parent; |
Guennadi Liakhovetski | 558f874 | 2013-03-21 17:05:40 +0100 | [diff] [blame] | 179 | }; |
| 180 | |
Guennadi Liakhovetski | 561a1a3 | 2013-06-06 17:38:12 +0200 | [diff] [blame] | 181 | i2c0: i2c@e6820000 { |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 182 | #address-cells = <1>; |
| 183 | #size-cells = <0>; |
Geert Uytterhoeven | dd4dc87 | 2014-11-06 12:52:09 +0100 | [diff] [blame] | 184 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 185 | reg = <0xe6820000 0x425>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 186 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH |
| 187 | 0 168 IRQ_TYPE_LEVEL_HIGH |
| 188 | 0 169 IRQ_TYPE_LEVEL_HIGH |
| 189 | 0 170 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 190 | clocks = <&mstp1_clks SH73A0_CLK_IIC0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 191 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 192 | status = "disabled"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 193 | }; |
| 194 | |
Guennadi Liakhovetski | 561a1a3 | 2013-06-06 17:38:12 +0200 | [diff] [blame] | 195 | i2c1: i2c@e6822000 { |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 196 | #address-cells = <1>; |
| 197 | #size-cells = <0>; |
Geert Uytterhoeven | dd4dc87 | 2014-11-06 12:52:09 +0100 | [diff] [blame] | 198 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 199 | reg = <0xe6822000 0x425>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 200 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH |
| 201 | 0 52 IRQ_TYPE_LEVEL_HIGH |
| 202 | 0 53 IRQ_TYPE_LEVEL_HIGH |
| 203 | 0 54 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 204 | clocks = <&mstp3_clks SH73A0_CLK_IIC1>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 205 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 206 | status = "disabled"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 207 | }; |
| 208 | |
Guennadi Liakhovetski | 561a1a3 | 2013-06-06 17:38:12 +0200 | [diff] [blame] | 209 | i2c2: i2c@e6824000 { |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
Geert Uytterhoeven | dd4dc87 | 2014-11-06 12:52:09 +0100 | [diff] [blame] | 212 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 213 | reg = <0xe6824000 0x425>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 214 | interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH |
| 215 | 0 172 IRQ_TYPE_LEVEL_HIGH |
| 216 | 0 173 IRQ_TYPE_LEVEL_HIGH |
| 217 | 0 174 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 218 | clocks = <&mstp0_clks SH73A0_CLK_IIC2>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 219 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 220 | status = "disabled"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 221 | }; |
| 222 | |
Guennadi Liakhovetski | 561a1a3 | 2013-06-06 17:38:12 +0200 | [diff] [blame] | 223 | i2c3: i2c@e6826000 { |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 224 | #address-cells = <1>; |
| 225 | #size-cells = <0>; |
Geert Uytterhoeven | dd4dc87 | 2014-11-06 12:52:09 +0100 | [diff] [blame] | 226 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 227 | reg = <0xe6826000 0x425>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 228 | interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH |
| 229 | 0 184 IRQ_TYPE_LEVEL_HIGH |
| 230 | 0 185 IRQ_TYPE_LEVEL_HIGH |
| 231 | 0 186 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 232 | clocks = <&mstp4_clks SH73A0_CLK_IIC3>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 233 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 234 | status = "disabled"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 235 | }; |
| 236 | |
Guennadi Liakhovetski | 561a1a3 | 2013-06-06 17:38:12 +0200 | [diff] [blame] | 237 | i2c4: i2c@e6828000 { |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 238 | #address-cells = <1>; |
| 239 | #size-cells = <0>; |
Geert Uytterhoeven | dd4dc87 | 2014-11-06 12:52:09 +0100 | [diff] [blame] | 240 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 241 | reg = <0xe6828000 0x425>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 242 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH |
| 243 | 0 188 IRQ_TYPE_LEVEL_HIGH |
| 244 | 0 189 IRQ_TYPE_LEVEL_HIGH |
| 245 | 0 190 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 246 | clocks = <&mstp4_clks SH73A0_CLK_IIC4>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 247 | power-domains = <&pd_c5>; |
Guennadi Liakhovetski | eda3a4f | 2013-09-26 13:06:01 +0200 | [diff] [blame] | 248 | status = "disabled"; |
Simon Horman | 4860953 | 2012-11-21 22:00:15 +0900 | [diff] [blame] | 249 | }; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 250 | |
Kuninori Morimoto | 33f6be3 | 2013-10-21 19:36:22 -0700 | [diff] [blame] | 251 | mmcif: mmc@e6bd0000 { |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 252 | compatible = "renesas,sh-mmcif"; |
| 253 | reg = <0xe6bd0000 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 254 | interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH |
| 255 | 0 141 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 256 | clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 257 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 258 | reg-io-width = <4>; |
| 259 | status = "disabled"; |
| 260 | }; |
| 261 | |
Kuninori Morimoto | 33f6be3 | 2013-10-21 19:36:22 -0700 | [diff] [blame] | 262 | sdhi0: sd@ee100000 { |
Kuninori Morimoto | e8a8b8a | 2013-11-19 19:18:09 -0800 | [diff] [blame] | 263 | compatible = "renesas,sdhi-sh73a0"; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 264 | reg = <0xee100000 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 265 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH |
| 266 | 0 84 IRQ_TYPE_LEVEL_HIGH |
| 267 | 0 85 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 268 | clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 269 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | a463f731 | 2013-03-19 18:38:50 +0100 | [diff] [blame] | 270 | cap-sd-highspeed; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ |
Kuninori Morimoto | 33f6be3 | 2013-10-21 19:36:22 -0700 | [diff] [blame] | 275 | sdhi1: sd@ee120000 { |
Kuninori Morimoto | e8a8b8a | 2013-11-19 19:18:09 -0800 | [diff] [blame] | 276 | compatible = "renesas,sdhi-sh73a0"; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 277 | reg = <0xee120000 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 278 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH |
| 279 | 0 89 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 280 | clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 281 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 282 | toshiba,mmc-wrprotect-disable; |
Guennadi Liakhovetski | a463f731 | 2013-03-19 18:38:50 +0100 | [diff] [blame] | 283 | cap-sd-highspeed; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 284 | status = "disabled"; |
| 285 | }; |
| 286 | |
Kuninori Morimoto | 33f6be3 | 2013-10-21 19:36:22 -0700 | [diff] [blame] | 287 | sdhi2: sd@ee140000 { |
Kuninori Morimoto | e8a8b8a | 2013-11-19 19:18:09 -0800 | [diff] [blame] | 288 | compatible = "renesas,sdhi-sh73a0"; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 289 | reg = <0xee140000 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 290 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH |
| 291 | 0 105 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 292 | clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 293 | power-domains = <&pd_a3sp>; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 294 | toshiba,mmc-wrprotect-disable; |
Guennadi Liakhovetski | a463f731 | 2013-03-19 18:38:50 +0100 | [diff] [blame] | 295 | cap-sd-highspeed; |
Guennadi Liakhovetski | 546e5d3 | 2013-03-19 13:47:43 +0100 | [diff] [blame] | 296 | status = "disabled"; |
| 297 | }; |
Laurent Pinchart | 3f59007 | 2012-11-20 14:02:54 +0100 | [diff] [blame] | 298 | |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 299 | scifa0: serial@e6c40000 { |
| 300 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 301 | reg = <0xe6c40000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 302 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 303 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; |
| 304 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 305 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 306 | status = "disabled"; |
| 307 | }; |
| 308 | |
| 309 | scifa1: serial@e6c50000 { |
| 310 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 311 | reg = <0xe6c50000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 312 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 313 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; |
| 314 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 315 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 316 | status = "disabled"; |
| 317 | }; |
| 318 | |
| 319 | scifa2: serial@e6c60000 { |
| 320 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 321 | reg = <0xe6c60000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 322 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 323 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; |
| 324 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 325 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 326 | status = "disabled"; |
| 327 | }; |
| 328 | |
| 329 | scifa3: serial@e6c70000 { |
| 330 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 331 | reg = <0xe6c70000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 332 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 333 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; |
| 334 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 335 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 336 | status = "disabled"; |
| 337 | }; |
| 338 | |
| 339 | scifa4: serial@e6c80000 { |
| 340 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 341 | reg = <0xe6c80000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 342 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 343 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; |
| 344 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 345 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 346 | status = "disabled"; |
| 347 | }; |
| 348 | |
| 349 | scifa5: serial@e6cb0000 { |
| 350 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 351 | reg = <0xe6cb0000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 352 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 353 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; |
| 354 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 355 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 356 | status = "disabled"; |
| 357 | }; |
| 358 | |
| 359 | scifa6: serial@e6cc0000 { |
| 360 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 361 | reg = <0xe6cc0000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 362 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 363 | clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; |
| 364 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 365 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 366 | status = "disabled"; |
| 367 | }; |
| 368 | |
| 369 | scifa7: serial@e6cd0000 { |
| 370 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; |
| 371 | reg = <0xe6cd0000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 372 | interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 373 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; |
| 374 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 375 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 376 | status = "disabled"; |
| 377 | }; |
| 378 | |
Geert Uytterhoeven | dfaac7b | 2015-04-27 15:55:24 +0200 | [diff] [blame] | 379 | scifb: serial@e6c30000 { |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 380 | compatible = "renesas,scifb-sh73a0", "renesas,scifb"; |
| 381 | reg = <0xe6c30000 0x100>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 382 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | f73e1e2 | 2014-12-10 15:45:26 +0100 | [diff] [blame] | 383 | clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; |
| 384 | clock-names = "sci_ick"; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 385 | power-domains = <&pd_a3sp>; |
Simon Horman | 2131421 | 2014-07-07 09:54:51 +0200 | [diff] [blame] | 386 | status = "disabled"; |
| 387 | }; |
| 388 | |
Laurent Pinchart | 3f59007 | 2012-11-20 14:02:54 +0100 | [diff] [blame] | 389 | pfc: pfc@e6050000 { |
| 390 | compatible = "renesas,pfc-sh73a0"; |
| 391 | reg = <0xe6050000 0x8000>, |
| 392 | <0xe605801c 0x1c>; |
| 393 | gpio-controller; |
| 394 | #gpio-cells = <2>; |
Geert Uytterhoeven | 94bdc48 | 2015-08-04 15:55:16 +0200 | [diff] [blame] | 395 | gpio-ranges = |
| 396 | <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, |
| 397 | <&pfc 288 288 22>; |
Laurent Pinchart | aba76d2 | 2013-12-11 04:26:29 +0100 | [diff] [blame] | 398 | interrupts-extended = |
| 399 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, |
| 400 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, |
| 401 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, |
| 402 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, |
| 403 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, |
| 404 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, |
| 405 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, |
| 406 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 407 | power-domains = <&pd_c5>; |
| 408 | }; |
| 409 | |
| 410 | sysc: system-controller@e6180000 { |
| 411 | compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; |
| 412 | reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; |
| 413 | |
| 414 | pm-domains { |
| 415 | pd_c5: c5 { |
| 416 | #address-cells = <1>; |
| 417 | #size-cells = <0>; |
| 418 | #power-domain-cells = <0>; |
| 419 | |
| 420 | pd_c4: c4@0 { |
| 421 | reg = <0>; |
| 422 | #power-domain-cells = <0>; |
| 423 | }; |
| 424 | |
| 425 | pd_d4: d4@1 { |
| 426 | reg = <1>; |
| 427 | #power-domain-cells = <0>; |
| 428 | }; |
| 429 | |
| 430 | pd_a4bc0: a4bc0@4 { |
| 431 | reg = <4>; |
| 432 | #power-domain-cells = <0>; |
| 433 | }; |
| 434 | |
| 435 | pd_a4bc1: a4bc1@5 { |
| 436 | reg = <5>; |
| 437 | #power-domain-cells = <0>; |
| 438 | }; |
| 439 | |
| 440 | pd_a4lc0: a4lc0@6 { |
| 441 | reg = <6>; |
| 442 | #power-domain-cells = <0>; |
| 443 | }; |
| 444 | |
| 445 | pd_a4lc1: a4lc1@7 { |
| 446 | reg = <7>; |
| 447 | #power-domain-cells = <0>; |
| 448 | }; |
| 449 | |
| 450 | pd_a4mp: a4mp@8 { |
| 451 | reg = <8>; |
| 452 | #address-cells = <1>; |
| 453 | #size-cells = <0>; |
| 454 | #power-domain-cells = <0>; |
| 455 | |
| 456 | pd_a3mp: a3mp@9 { |
| 457 | reg = <9>; |
| 458 | #power-domain-cells = <0>; |
| 459 | }; |
| 460 | |
| 461 | pd_a3vc: a3vc@10 { |
| 462 | reg = <10>; |
| 463 | #power-domain-cells = <0>; |
| 464 | }; |
| 465 | }; |
| 466 | |
| 467 | pd_a4rm: a4rm@12 { |
| 468 | reg = <12>; |
| 469 | #address-cells = <1>; |
| 470 | #size-cells = <0>; |
| 471 | #power-domain-cells = <0>; |
| 472 | |
| 473 | pd_a3r: a3r@13 { |
| 474 | reg = <13>; |
| 475 | #address-cells = <1>; |
| 476 | #size-cells = <0>; |
| 477 | #power-domain-cells = <0>; |
| 478 | |
| 479 | pd_a2rv: a2rv@14 { |
| 480 | reg = <14>; |
| 481 | #address-cells = <1>; |
| 482 | #size-cells = <0>; |
| 483 | #power-domain-cells = <0>; |
| 484 | }; |
| 485 | }; |
| 486 | }; |
| 487 | |
| 488 | pd_a4s: a4s@16 { |
| 489 | reg = <16>; |
| 490 | #address-cells = <1>; |
| 491 | #size-cells = <0>; |
| 492 | #power-domain-cells = <0>; |
| 493 | |
| 494 | pd_a3sp: a3sp@17 { |
| 495 | reg = <17>; |
| 496 | #power-domain-cells = <0>; |
| 497 | }; |
| 498 | |
| 499 | pd_a3sg: a3sg@18 { |
| 500 | reg = <18>; |
| 501 | #power-domain-cells = <0>; |
| 502 | }; |
| 503 | |
| 504 | pd_a3sm: a3sm@19 { |
| 505 | reg = <19>; |
| 506 | #address-cells = <1>; |
| 507 | #size-cells = <0>; |
| 508 | #power-domain-cells = <0>; |
| 509 | |
| 510 | pd_a2sl: a2sl@20 { |
| 511 | reg = <20>; |
| 512 | #power-domain-cells = <0>; |
| 513 | }; |
| 514 | }; |
| 515 | }; |
| 516 | }; |
| 517 | }; |
Laurent Pinchart | 3f59007 | 2012-11-20 14:02:54 +0100 | [diff] [blame] | 518 | }; |
Kuninori Morimoto | 63b1303 | 2013-12-04 17:32:54 -0800 | [diff] [blame] | 519 | |
| 520 | sh_fsi2: sound@ec230000 { |
| 521 | #sound-dai-cells = <1>; |
Geert Uytterhoeven | f76452f | 2015-01-06 21:01:51 +0100 | [diff] [blame] | 522 | compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; |
Kuninori Morimoto | 63b1303 | 2013-12-04 17:32:54 -0800 | [diff] [blame] | 523 | reg = <0xec230000 0x400>; |
Kuninori Morimoto | 63b1303 | 2013-12-04 17:32:54 -0800 | [diff] [blame] | 524 | interrupts = <0 146 0x4>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 525 | power-domains = <&pd_a4mp>; |
Kuninori Morimoto | 63b1303 | 2013-12-04 17:32:54 -0800 | [diff] [blame] | 526 | status = "disabled"; |
| 527 | }; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 528 | |
Geert Uytterhoeven | 217b6e6 | 2015-02-17 15:52:36 +0100 | [diff] [blame] | 529 | bsc: bus@fec10000 { |
| 530 | compatible = "renesas,bsc-sh73a0", "renesas,bsc", |
| 531 | "simple-pm-bus"; |
| 532 | #address-cells = <1>; |
| 533 | #size-cells = <1>; |
| 534 | ranges = <0 0 0x20000000>; |
| 535 | reg = <0xfec10000 0x400>; |
| 536 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| 537 | clocks = <&zb_clk>; |
Geert Uytterhoeven | bee7a18 | 2015-02-17 16:31:38 +0100 | [diff] [blame] | 538 | power-domains = <&pd_a4s>; |
Geert Uytterhoeven | 217b6e6 | 2015-02-17 15:52:36 +0100 | [diff] [blame] | 539 | }; |
| 540 | |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 541 | clocks { |
| 542 | #address-cells = <1>; |
| 543 | #size-cells = <1>; |
| 544 | ranges; |
| 545 | |
| 546 | /* External root clocks */ |
| 547 | extalr_clk: extalr_clk { |
| 548 | compatible = "fixed-clock"; |
| 549 | #clock-cells = <0>; |
| 550 | clock-frequency = <32768>; |
| 551 | clock-output-names = "extalr"; |
| 552 | }; |
| 553 | extal1_clk: extal1_clk { |
| 554 | compatible = "fixed-clock"; |
| 555 | #clock-cells = <0>; |
| 556 | clock-frequency = <26000000>; |
| 557 | clock-output-names = "extal1"; |
| 558 | }; |
| 559 | extal2_clk: extal2_clk { |
| 560 | compatible = "fixed-clock"; |
| 561 | #clock-cells = <0>; |
| 562 | clock-output-names = "extal2"; |
| 563 | }; |
| 564 | extcki_clk: extcki_clk { |
| 565 | compatible = "fixed-clock"; |
| 566 | #clock-cells = <0>; |
| 567 | clock-output-names = "extcki"; |
| 568 | }; |
| 569 | fsiack_clk: fsiack_clk { |
| 570 | compatible = "fixed-clock"; |
| 571 | #clock-cells = <0>; |
| 572 | clock-frequency = <0>; |
| 573 | clock-output-names = "fsiack"; |
| 574 | }; |
| 575 | fsibck_clk: fsibck_clk { |
| 576 | compatible = "fixed-clock"; |
| 577 | #clock-cells = <0>; |
| 578 | clock-frequency = <0>; |
| 579 | clock-output-names = "fsibck"; |
| 580 | }; |
| 581 | |
| 582 | /* Special CPG clocks */ |
| 583 | cpg_clocks: cpg_clocks@e6150000 { |
| 584 | compatible = "renesas,sh73a0-cpg-clocks"; |
| 585 | reg = <0xe6150000 0x10000>; |
| 586 | clocks = <&extal1_clk>, <&extal2_clk>; |
| 587 | #clock-cells = <1>; |
| 588 | clock-output-names = "main", "pll0", "pll1", "pll2", |
| 589 | "pll3", "dsi0phy", "dsi1phy", |
| 590 | "zg", "m3", "b", "m1", "m2", |
| 591 | "z", "zx", "hp"; |
| 592 | }; |
| 593 | |
| 594 | /* Variable factor clocks (DIV6) */ |
| 595 | vclk1_clk: vclk1_clk@e6150008 { |
| 596 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 597 | reg = <0xe6150008 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 598 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 599 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, |
| 600 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, |
| 601 | <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 602 | #clock-cells = <0>; |
| 603 | clock-output-names = "vclk1"; |
| 604 | }; |
| 605 | vclk2_clk: vclk2_clk@e615000c { |
| 606 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 607 | reg = <0xe615000c 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 608 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 609 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, |
| 610 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, |
| 611 | <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 612 | #clock-cells = <0>; |
| 613 | clock-output-names = "vclk2"; |
| 614 | }; |
| 615 | vclk3_clk: vclk3_clk@e615001c { |
| 616 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 617 | reg = <0xe615001c 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 618 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 619 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, |
| 620 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, |
| 621 | <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 622 | #clock-cells = <0>; |
| 623 | clock-output-names = "vclk3"; |
| 624 | }; |
| 625 | zb_clk: zb_clk@e6150010 { |
| 626 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 627 | reg = <0xe6150010 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 628 | clocks = <&pll1_div2_clk>, <0>, |
| 629 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 630 | #clock-cells = <0>; |
| 631 | clock-output-names = "zb"; |
| 632 | }; |
| 633 | flctl_clk: flctl_clk@e6150014 { |
| 634 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 635 | reg = <0xe6150014 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 636 | clocks = <&pll1_div2_clk>, <0>, |
| 637 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 638 | #clock-cells = <0>; |
| 639 | clock-output-names = "flctlck"; |
| 640 | }; |
| 641 | sdhi0_clk: sdhi0_clk@e6150074 { |
| 642 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 643 | reg = <0xe6150074 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 644 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 645 | <&pll1_div13_clk>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 646 | #clock-cells = <0>; |
| 647 | clock-output-names = "sdhi0ck"; |
| 648 | }; |
| 649 | sdhi1_clk: sdhi1_clk@e6150078 { |
| 650 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 651 | reg = <0xe6150078 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 652 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 653 | <&pll1_div13_clk>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 654 | #clock-cells = <0>; |
| 655 | clock-output-names = "sdhi1ck"; |
| 656 | }; |
| 657 | sdhi2_clk: sdhi2_clk@e615007c { |
| 658 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 659 | reg = <0xe615007c 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 660 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 661 | <&pll1_div13_clk>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 662 | #clock-cells = <0>; |
| 663 | clock-output-names = "sdhi2ck"; |
| 664 | }; |
| 665 | fsia_clk: fsia_clk@e6150018 { |
| 666 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 667 | reg = <0xe6150018 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 668 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 669 | <&fsiack_clk>, <&fsiack_clk>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 670 | #clock-cells = <0>; |
| 671 | clock-output-names = "fsia"; |
| 672 | }; |
| 673 | fsib_clk: fsib_clk@e6150090 { |
| 674 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 675 | reg = <0xe6150090 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 676 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 677 | <&fsibck_clk>, <&fsibck_clk>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 678 | #clock-cells = <0>; |
| 679 | clock-output-names = "fsib"; |
| 680 | }; |
| 681 | sub_clk: sub_clk@e6150080 { |
| 682 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 683 | reg = <0xe6150080 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 684 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 685 | <&extal2_clk>, <&extal2_clk>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 686 | #clock-cells = <0>; |
| 687 | clock-output-names = "sub"; |
| 688 | }; |
| 689 | spua_clk: spua_clk@e6150084 { |
| 690 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 691 | reg = <0xe6150084 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 692 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 693 | <&extal2_clk>, <&extal2_clk>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 694 | #clock-cells = <0>; |
| 695 | clock-output-names = "spua"; |
| 696 | }; |
| 697 | spuv_clk: spuv_clk@e6150094 { |
| 698 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 699 | reg = <0xe6150094 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 700 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 701 | <&extal2_clk>, <&extal2_clk>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 702 | #clock-cells = <0>; |
| 703 | clock-output-names = "spuv"; |
| 704 | }; |
| 705 | msu_clk: msu_clk@e6150088 { |
| 706 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 707 | reg = <0xe6150088 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 708 | clocks = <&pll1_div2_clk>, <0>, |
| 709 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 710 | #clock-cells = <0>; |
| 711 | clock-output-names = "msu"; |
| 712 | }; |
| 713 | hsi_clk: hsi_clk@e615008c { |
| 714 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 715 | reg = <0xe615008c 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 716 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 717 | <&pll1_div7_clk>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 718 | #clock-cells = <0>; |
| 719 | clock-output-names = "hsi"; |
| 720 | }; |
| 721 | mfg1_clk: mfg1_clk@e6150098 { |
| 722 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 723 | reg = <0xe6150098 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 724 | clocks = <&pll1_div2_clk>, <0>, |
| 725 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 726 | #clock-cells = <0>; |
| 727 | clock-output-names = "mfg1"; |
| 728 | }; |
| 729 | mfg2_clk: mfg2_clk@e615009c { |
| 730 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 731 | reg = <0xe615009c 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 732 | clocks = <&pll1_div2_clk>, <0>, |
| 733 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 734 | #clock-cells = <0>; |
| 735 | clock-output-names = "mfg2"; |
| 736 | }; |
| 737 | dsit_clk: dsit_clk@e6150060 { |
| 738 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 739 | reg = <0xe6150060 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 740 | clocks = <&pll1_div2_clk>, <0>, |
| 741 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 742 | #clock-cells = <0>; |
| 743 | clock-output-names = "dsit"; |
| 744 | }; |
| 745 | dsi0p_clk: dsi0p_clk@e6150064 { |
| 746 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; |
| 747 | reg = <0xe6150064 4>; |
Ulrich Hecht | 09940bf | 2015-01-06 20:56:06 +0100 | [diff] [blame] | 748 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
| 749 | <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, |
| 750 | <&extcki_clk>, <0>, <0>, <0>; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 751 | #clock-cells = <0>; |
| 752 | clock-output-names = "dsi0pck"; |
| 753 | }; |
| 754 | |
| 755 | /* Fixed factor clocks */ |
| 756 | main_div2_clk: main_div2_clk { |
| 757 | compatible = "fixed-factor-clock"; |
| 758 | clocks = <&cpg_clocks SH73A0_CLK_MAIN>; |
| 759 | #clock-cells = <0>; |
| 760 | clock-div = <2>; |
| 761 | clock-mult = <1>; |
| 762 | clock-output-names = "main_div2"; |
| 763 | }; |
| 764 | pll1_div2_clk: pll1_div2_clk { |
| 765 | compatible = "fixed-factor-clock"; |
| 766 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; |
| 767 | #clock-cells = <0>; |
| 768 | clock-div = <2>; |
| 769 | clock-mult = <1>; |
| 770 | clock-output-names = "pll1_div2"; |
| 771 | }; |
| 772 | pll1_div7_clk: pll1_div7_clk { |
| 773 | compatible = "fixed-factor-clock"; |
| 774 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; |
| 775 | #clock-cells = <0>; |
| 776 | clock-div = <7>; |
| 777 | clock-mult = <1>; |
| 778 | clock-output-names = "pll1_div7"; |
| 779 | }; |
| 780 | pll1_div13_clk: pll1_div13_clk { |
| 781 | compatible = "fixed-factor-clock"; |
| 782 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; |
| 783 | #clock-cells = <0>; |
| 784 | clock-div = <13>; |
| 785 | clock-mult = <1>; |
| 786 | clock-output-names = "pll1_div13"; |
| 787 | }; |
| 788 | twd_clk: twd_clk { |
| 789 | compatible = "fixed-factor-clock"; |
| 790 | clocks = <&cpg_clocks SH73A0_CLK_Z>; |
| 791 | #clock-cells = <0>; |
| 792 | clock-div = <4>; |
| 793 | clock-mult = <1>; |
| 794 | clock-output-names = "twd"; |
| 795 | }; |
| 796 | |
| 797 | /* Gate clocks */ |
| 798 | mstp0_clks: mstp0_clks@e6150130 { |
| 799 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 800 | reg = <0xe6150130 4>, <0xe6150030 4>; |
| 801 | clocks = <&cpg_clocks SH73A0_CLK_HP>; |
| 802 | #clock-cells = <1>; |
| 803 | clock-indices = < |
| 804 | SH73A0_CLK_IIC2 |
| 805 | >; |
| 806 | clock-output-names = |
| 807 | "iic2"; |
| 808 | }; |
| 809 | mstp1_clks: mstp1_clks@e6150134 { |
| 810 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 811 | reg = <0xe6150134 4>, <0xe6150038 4>; |
| 812 | clocks = <&cpg_clocks SH73A0_CLK_B>, |
| 813 | <&cpg_clocks SH73A0_CLK_B>, |
| 814 | <&cpg_clocks SH73A0_CLK_B>, |
| 815 | <&cpg_clocks SH73A0_CLK_B>, |
| 816 | <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, |
| 817 | <&cpg_clocks SH73A0_CLK_HP>, |
| 818 | <&cpg_clocks SH73A0_CLK_ZG>, |
| 819 | <&cpg_clocks SH73A0_CLK_B>; |
| 820 | #clock-cells = <1>; |
| 821 | clock-indices = < |
| 822 | SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 |
| 823 | SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 |
| 824 | SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 |
| 825 | SH73A0_CLK_IIC0 SH73A0_CLK_SGX |
| 826 | SH73A0_CLK_LCDC0 |
| 827 | >; |
| 828 | clock-output-names = |
| 829 | "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", |
| 830 | "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; |
| 831 | }; |
| 832 | mstp2_clks: mstp2_clks@e6150138 { |
| 833 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 834 | reg = <0xe6150138 4>, <0xe6150040 4>; |
| 835 | clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, |
| 836 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, |
| 837 | <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>, |
| 838 | <&sub_clk>, <&sub_clk>; |
| 839 | #clock-cells = <1>; |
| 840 | clock-indices = < |
| 841 | SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC |
| 842 | SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5 |
| 843 | SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0 |
| 844 | SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2 |
| 845 | SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4 |
| 846 | >; |
| 847 | clock-output-names = |
| 848 | "scifa7", "sy_dmac", "mp_dmac", "scifa5", |
| 849 | "scifb", "scifa0", "scifa1", "scifa2", |
| 850 | "scifa3", "scifa4"; |
| 851 | }; |
| 852 | mstp3_clks: mstp3_clks@e615013c { |
| 853 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 854 | reg = <0xe615013c 4>, <0xe6150048 4>; |
| 855 | clocks = <&sub_clk>, <&extalr_clk>, |
| 856 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, |
| 857 | <&cpg_clocks SH73A0_CLK_HP>, |
| 858 | <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, |
| 859 | <&sdhi0_clk>, <&sdhi1_clk>, |
| 860 | <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, |
| 861 | <&main_div2_clk>, <&main_div2_clk>, |
| 862 | <&main_div2_clk>, <&main_div2_clk>, |
| 863 | <&main_div2_clk>; |
| 864 | #clock-cells = <1>; |
| 865 | clock-indices = < |
| 866 | SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 |
| 867 | SH73A0_CLK_FSI SH73A0_CLK_IRDA |
| 868 | SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL |
| 869 | SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 |
| 870 | SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 |
| 871 | SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 |
| 872 | SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 |
| 873 | SH73A0_CLK_TPU4 |
| 874 | >; |
| 875 | clock-output-names = |
| 876 | "scifa6", "cmt1", "fsi", "irda", "iic1", |
| 877 | "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", |
| 878 | "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; |
| 879 | }; |
| 880 | mstp4_clks: mstp4_clks@e6150140 { |
| 881 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 882 | reg = <0xe6150140 4>, <0xe615004c 4>; |
| 883 | clocks = <&cpg_clocks SH73A0_CLK_HP>, |
| 884 | <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; |
| 885 | #clock-cells = <1>; |
| 886 | clock-indices = < |
| 887 | SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 |
| 888 | SH73A0_CLK_KEYSC |
| 889 | >; |
| 890 | clock-output-names = |
| 891 | "iic3", "iic4", "keysc"; |
| 892 | }; |
Geert Uytterhoeven | 56a215d | 2015-01-06 20:56:05 +0100 | [diff] [blame] | 893 | mstp5_clks: mstp5_clks@e6150144 { |
| 894 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 895 | reg = <0xe6150144 4>, <0xe615003c 4>; |
| 896 | clocks = <&cpg_clocks SH73A0_CLK_HP>; |
| 897 | #clock-cells = <1>; |
| 898 | clock-indices = < |
| 899 | SH73A0_CLK_INTCA0 |
| 900 | >; |
| 901 | clock-output-names = |
| 902 | "intca0"; |
| 903 | }; |
Ulrich Hecht | 00df611 | 2014-12-10 15:45:24 +0100 | [diff] [blame] | 904 | }; |
Simon Horman | a3f22db | 2012-11-21 21:12:43 +0900 | [diff] [blame] | 905 | }; |