Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
Dhananjay Phadke | 13af7a6 | 2009-09-11 11:28:15 +0000 | [diff] [blame] | 3 | * Copyright (C) 2009 - QLogic Corporation. |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 4 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 5 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 10 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 15 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 19 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 20 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 23 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #ifndef __NETXEN_NIC_HDR_H_ |
| 27 | #define __NETXEN_NIC_HDR_H_ |
| 28 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 29 | #include <linux/kernel.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 30 | #include <linux/types.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * The basic unit of access when reading/writing control registers. |
| 34 | */ |
| 35 | |
| 36 | typedef __le32 netxen_crbword_t; /* single word in CRB space */ |
| 37 | |
| 38 | enum { |
| 39 | NETXEN_HW_H0_CH_HUB_ADR = 0x05, |
| 40 | NETXEN_HW_H1_CH_HUB_ADR = 0x0E, |
| 41 | NETXEN_HW_H2_CH_HUB_ADR = 0x03, |
| 42 | NETXEN_HW_H3_CH_HUB_ADR = 0x01, |
| 43 | NETXEN_HW_H4_CH_HUB_ADR = 0x06, |
| 44 | NETXEN_HW_H5_CH_HUB_ADR = 0x07, |
| 45 | NETXEN_HW_H6_CH_HUB_ADR = 0x08 |
| 46 | }; |
| 47 | |
| 48 | /* Hub 0 */ |
| 49 | enum { |
| 50 | NETXEN_HW_MN_CRB_AGT_ADR = 0x15, |
| 51 | NETXEN_HW_MS_CRB_AGT_ADR = 0x25 |
| 52 | }; |
| 53 | |
| 54 | /* Hub 1 */ |
| 55 | enum { |
| 56 | NETXEN_HW_PS_CRB_AGT_ADR = 0x73, |
| 57 | NETXEN_HW_SS_CRB_AGT_ADR = 0x20, |
| 58 | NETXEN_HW_RPMX3_CRB_AGT_ADR = 0x0b, |
| 59 | NETXEN_HW_QMS_CRB_AGT_ADR = 0x00, |
| 60 | NETXEN_HW_SQGS0_CRB_AGT_ADR = 0x01, |
| 61 | NETXEN_HW_SQGS1_CRB_AGT_ADR = 0x02, |
| 62 | NETXEN_HW_SQGS2_CRB_AGT_ADR = 0x03, |
| 63 | NETXEN_HW_SQGS3_CRB_AGT_ADR = 0x04, |
| 64 | NETXEN_HW_C2C0_CRB_AGT_ADR = 0x58, |
| 65 | NETXEN_HW_C2C1_CRB_AGT_ADR = 0x59, |
| 66 | NETXEN_HW_C2C2_CRB_AGT_ADR = 0x5a, |
| 67 | NETXEN_HW_RPMX2_CRB_AGT_ADR = 0x0a, |
| 68 | NETXEN_HW_RPMX4_CRB_AGT_ADR = 0x0c, |
| 69 | NETXEN_HW_RPMX7_CRB_AGT_ADR = 0x0f, |
| 70 | NETXEN_HW_RPMX9_CRB_AGT_ADR = 0x12, |
| 71 | NETXEN_HW_SMB_CRB_AGT_ADR = 0x18 |
| 72 | }; |
| 73 | |
| 74 | /* Hub 2 */ |
| 75 | enum { |
| 76 | NETXEN_HW_NIU_CRB_AGT_ADR = 0x31, |
| 77 | NETXEN_HW_I2C0_CRB_AGT_ADR = 0x19, |
| 78 | NETXEN_HW_I2C1_CRB_AGT_ADR = 0x29, |
| 79 | |
| 80 | NETXEN_HW_SN_CRB_AGT_ADR = 0x10, |
| 81 | NETXEN_HW_I2Q_CRB_AGT_ADR = 0x20, |
| 82 | NETXEN_HW_LPC_CRB_AGT_ADR = 0x22, |
| 83 | NETXEN_HW_ROMUSB_CRB_AGT_ADR = 0x21, |
| 84 | NETXEN_HW_QM_CRB_AGT_ADR = 0x66, |
| 85 | NETXEN_HW_SQG0_CRB_AGT_ADR = 0x60, |
| 86 | NETXEN_HW_SQG1_CRB_AGT_ADR = 0x61, |
| 87 | NETXEN_HW_SQG2_CRB_AGT_ADR = 0x62, |
| 88 | NETXEN_HW_SQG3_CRB_AGT_ADR = 0x63, |
| 89 | NETXEN_HW_RPMX1_CRB_AGT_ADR = 0x09, |
| 90 | NETXEN_HW_RPMX5_CRB_AGT_ADR = 0x0d, |
| 91 | NETXEN_HW_RPMX6_CRB_AGT_ADR = 0x0e, |
| 92 | NETXEN_HW_RPMX8_CRB_AGT_ADR = 0x11 |
| 93 | }; |
| 94 | |
| 95 | /* Hub 3 */ |
| 96 | enum { |
| 97 | NETXEN_HW_PH_CRB_AGT_ADR = 0x1A, |
| 98 | NETXEN_HW_SRE_CRB_AGT_ADR = 0x50, |
| 99 | NETXEN_HW_EG_CRB_AGT_ADR = 0x51, |
| 100 | NETXEN_HW_RPMX0_CRB_AGT_ADR = 0x08 |
| 101 | }; |
| 102 | |
| 103 | /* Hub 4 */ |
| 104 | enum { |
| 105 | NETXEN_HW_PEGN0_CRB_AGT_ADR = 0x40, |
| 106 | NETXEN_HW_PEGN1_CRB_AGT_ADR, |
| 107 | NETXEN_HW_PEGN2_CRB_AGT_ADR, |
| 108 | NETXEN_HW_PEGN3_CRB_AGT_ADR, |
| 109 | NETXEN_HW_PEGNI_CRB_AGT_ADR, |
| 110 | NETXEN_HW_PEGND_CRB_AGT_ADR, |
| 111 | NETXEN_HW_PEGNC_CRB_AGT_ADR, |
| 112 | NETXEN_HW_PEGR0_CRB_AGT_ADR, |
| 113 | NETXEN_HW_PEGR1_CRB_AGT_ADR, |
| 114 | NETXEN_HW_PEGR2_CRB_AGT_ADR, |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 115 | NETXEN_HW_PEGR3_CRB_AGT_ADR, |
| 116 | NETXEN_HW_PEGN4_CRB_AGT_ADR |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | /* Hub 5 */ |
| 120 | enum { |
| 121 | NETXEN_HW_PEGS0_CRB_AGT_ADR = 0x40, |
| 122 | NETXEN_HW_PEGS1_CRB_AGT_ADR, |
| 123 | NETXEN_HW_PEGS2_CRB_AGT_ADR, |
| 124 | NETXEN_HW_PEGS3_CRB_AGT_ADR, |
| 125 | NETXEN_HW_PEGSI_CRB_AGT_ADR, |
| 126 | NETXEN_HW_PEGSD_CRB_AGT_ADR, |
| 127 | NETXEN_HW_PEGSC_CRB_AGT_ADR |
| 128 | }; |
| 129 | |
| 130 | /* Hub 6 */ |
| 131 | enum { |
| 132 | NETXEN_HW_CAS0_CRB_AGT_ADR = 0x46, |
| 133 | NETXEN_HW_CAS1_CRB_AGT_ADR = 0x47, |
| 134 | NETXEN_HW_CAS2_CRB_AGT_ADR = 0x48, |
| 135 | NETXEN_HW_CAS3_CRB_AGT_ADR = 0x49, |
| 136 | NETXEN_HW_NCM_CRB_AGT_ADR = 0x16, |
| 137 | NETXEN_HW_TMR_CRB_AGT_ADR = 0x17, |
| 138 | NETXEN_HW_XDMA_CRB_AGT_ADR = 0x05, |
| 139 | NETXEN_HW_OCM0_CRB_AGT_ADR = 0x06, |
| 140 | NETXEN_HW_OCM1_CRB_AGT_ADR = 0x07 |
| 141 | }; |
| 142 | |
| 143 | /* Floaters - non existent modules */ |
| 144 | #define NETXEN_HW_EFC_RPMX0_CRB_AGT_ADR 0x67 |
| 145 | |
| 146 | /* This field defines PCI/X adr [25:20] of agents on the CRB */ |
| 147 | enum { |
| 148 | NETXEN_HW_PX_MAP_CRB_PH = 0, |
| 149 | NETXEN_HW_PX_MAP_CRB_PS, |
| 150 | NETXEN_HW_PX_MAP_CRB_MN, |
| 151 | NETXEN_HW_PX_MAP_CRB_MS, |
| 152 | NETXEN_HW_PX_MAP_CRB_PGR1, |
| 153 | NETXEN_HW_PX_MAP_CRB_SRE, |
| 154 | NETXEN_HW_PX_MAP_CRB_NIU, |
| 155 | NETXEN_HW_PX_MAP_CRB_QMN, |
| 156 | NETXEN_HW_PX_MAP_CRB_SQN0, |
| 157 | NETXEN_HW_PX_MAP_CRB_SQN1, |
| 158 | NETXEN_HW_PX_MAP_CRB_SQN2, |
| 159 | NETXEN_HW_PX_MAP_CRB_SQN3, |
| 160 | NETXEN_HW_PX_MAP_CRB_QMS, |
| 161 | NETXEN_HW_PX_MAP_CRB_SQS0, |
| 162 | NETXEN_HW_PX_MAP_CRB_SQS1, |
| 163 | NETXEN_HW_PX_MAP_CRB_SQS2, |
| 164 | NETXEN_HW_PX_MAP_CRB_SQS3, |
| 165 | NETXEN_HW_PX_MAP_CRB_PGN0, |
| 166 | NETXEN_HW_PX_MAP_CRB_PGN1, |
| 167 | NETXEN_HW_PX_MAP_CRB_PGN2, |
| 168 | NETXEN_HW_PX_MAP_CRB_PGN3, |
| 169 | NETXEN_HW_PX_MAP_CRB_PGND, |
| 170 | NETXEN_HW_PX_MAP_CRB_PGNI, |
| 171 | NETXEN_HW_PX_MAP_CRB_PGS0, |
| 172 | NETXEN_HW_PX_MAP_CRB_PGS1, |
| 173 | NETXEN_HW_PX_MAP_CRB_PGS2, |
| 174 | NETXEN_HW_PX_MAP_CRB_PGS3, |
| 175 | NETXEN_HW_PX_MAP_CRB_PGSD, |
| 176 | NETXEN_HW_PX_MAP_CRB_PGSI, |
| 177 | NETXEN_HW_PX_MAP_CRB_SN, |
| 178 | NETXEN_HW_PX_MAP_CRB_PGR2, |
| 179 | NETXEN_HW_PX_MAP_CRB_EG, |
| 180 | NETXEN_HW_PX_MAP_CRB_PH2, |
| 181 | NETXEN_HW_PX_MAP_CRB_PS2, |
| 182 | NETXEN_HW_PX_MAP_CRB_CAM, |
| 183 | NETXEN_HW_PX_MAP_CRB_CAS0, |
| 184 | NETXEN_HW_PX_MAP_CRB_CAS1, |
| 185 | NETXEN_HW_PX_MAP_CRB_CAS2, |
| 186 | NETXEN_HW_PX_MAP_CRB_C2C0, |
| 187 | NETXEN_HW_PX_MAP_CRB_C2C1, |
| 188 | NETXEN_HW_PX_MAP_CRB_TIMR, |
| 189 | NETXEN_HW_PX_MAP_CRB_PGR3, |
| 190 | NETXEN_HW_PX_MAP_CRB_RPMX1, |
| 191 | NETXEN_HW_PX_MAP_CRB_RPMX2, |
| 192 | NETXEN_HW_PX_MAP_CRB_RPMX3, |
| 193 | NETXEN_HW_PX_MAP_CRB_RPMX4, |
| 194 | NETXEN_HW_PX_MAP_CRB_RPMX5, |
| 195 | NETXEN_HW_PX_MAP_CRB_RPMX6, |
| 196 | NETXEN_HW_PX_MAP_CRB_RPMX7, |
| 197 | NETXEN_HW_PX_MAP_CRB_XDMA, |
| 198 | NETXEN_HW_PX_MAP_CRB_I2Q, |
| 199 | NETXEN_HW_PX_MAP_CRB_ROMUSB, |
| 200 | NETXEN_HW_PX_MAP_CRB_CAS3, |
| 201 | NETXEN_HW_PX_MAP_CRB_RPMX0, |
| 202 | NETXEN_HW_PX_MAP_CRB_RPMX8, |
| 203 | NETXEN_HW_PX_MAP_CRB_RPMX9, |
| 204 | NETXEN_HW_PX_MAP_CRB_OCM0, |
| 205 | NETXEN_HW_PX_MAP_CRB_OCM1, |
| 206 | NETXEN_HW_PX_MAP_CRB_SMB, |
| 207 | NETXEN_HW_PX_MAP_CRB_I2C0, |
| 208 | NETXEN_HW_PX_MAP_CRB_I2C1, |
| 209 | NETXEN_HW_PX_MAP_CRB_LPC, |
| 210 | NETXEN_HW_PX_MAP_CRB_PGNC, |
| 211 | NETXEN_HW_PX_MAP_CRB_PGR0 |
| 212 | }; |
| 213 | |
| 214 | /* This field defines CRB adr [31:20] of the agents */ |
| 215 | |
| 216 | #define NETXEN_HW_CRB_HUB_AGT_ADR_MN \ |
| 217 | ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MN_CRB_AGT_ADR) |
| 218 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PH \ |
| 219 | ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_PH_CRB_AGT_ADR) |
| 220 | #define NETXEN_HW_CRB_HUB_AGT_ADR_MS \ |
| 221 | ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MS_CRB_AGT_ADR) |
| 222 | |
| 223 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PS \ |
| 224 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_PS_CRB_AGT_ADR) |
| 225 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SS \ |
| 226 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SS_CRB_AGT_ADR) |
| 227 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3 \ |
| 228 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX3_CRB_AGT_ADR) |
| 229 | #define NETXEN_HW_CRB_HUB_AGT_ADR_QMS \ |
| 230 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_QMS_CRB_AGT_ADR) |
| 231 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQS0 \ |
| 232 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS0_CRB_AGT_ADR) |
| 233 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQS1 \ |
| 234 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS1_CRB_AGT_ADR) |
| 235 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQS2 \ |
| 236 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS2_CRB_AGT_ADR) |
| 237 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQS3 \ |
| 238 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS3_CRB_AGT_ADR) |
| 239 | #define NETXEN_HW_CRB_HUB_AGT_ADR_C2C0 \ |
| 240 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C0_CRB_AGT_ADR) |
| 241 | #define NETXEN_HW_CRB_HUB_AGT_ADR_C2C1 \ |
| 242 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C1_CRB_AGT_ADR) |
| 243 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2 \ |
| 244 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX2_CRB_AGT_ADR) |
| 245 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4 \ |
| 246 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX4_CRB_AGT_ADR) |
| 247 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7 \ |
| 248 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX7_CRB_AGT_ADR) |
| 249 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9 \ |
| 250 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX9_CRB_AGT_ADR) |
| 251 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SMB \ |
| 252 | ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SMB_CRB_AGT_ADR) |
| 253 | |
| 254 | #define NETXEN_HW_CRB_HUB_AGT_ADR_NIU \ |
| 255 | ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_NIU_CRB_AGT_ADR) |
| 256 | #define NETXEN_HW_CRB_HUB_AGT_ADR_I2C0 \ |
| 257 | ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C0_CRB_AGT_ADR) |
| 258 | #define NETXEN_HW_CRB_HUB_AGT_ADR_I2C1 \ |
| 259 | ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C1_CRB_AGT_ADR) |
| 260 | |
| 261 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SRE \ |
| 262 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SRE_CRB_AGT_ADR) |
| 263 | #define NETXEN_HW_CRB_HUB_AGT_ADR_EG \ |
| 264 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_EG_CRB_AGT_ADR) |
| 265 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0 \ |
| 266 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX0_CRB_AGT_ADR) |
| 267 | #define NETXEN_HW_CRB_HUB_AGT_ADR_QMN \ |
| 268 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_QM_CRB_AGT_ADR) |
| 269 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQN0 \ |
| 270 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG0_CRB_AGT_ADR) |
| 271 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQN1 \ |
| 272 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG1_CRB_AGT_ADR) |
| 273 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQN2 \ |
| 274 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG2_CRB_AGT_ADR) |
| 275 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SQN3 \ |
| 276 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG3_CRB_AGT_ADR) |
| 277 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1 \ |
| 278 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX1_CRB_AGT_ADR) |
| 279 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5 \ |
| 280 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX5_CRB_AGT_ADR) |
| 281 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6 \ |
| 282 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX6_CRB_AGT_ADR) |
| 283 | #define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8 \ |
| 284 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX8_CRB_AGT_ADR) |
| 285 | #define NETXEN_HW_CRB_HUB_AGT_ADR_CAS0 \ |
| 286 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS0_CRB_AGT_ADR) |
| 287 | #define NETXEN_HW_CRB_HUB_AGT_ADR_CAS1 \ |
| 288 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS1_CRB_AGT_ADR) |
| 289 | #define NETXEN_HW_CRB_HUB_AGT_ADR_CAS2 \ |
| 290 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS2_CRB_AGT_ADR) |
| 291 | #define NETXEN_HW_CRB_HUB_AGT_ADR_CAS3 \ |
| 292 | ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS3_CRB_AGT_ADR) |
| 293 | |
| 294 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGNI \ |
| 295 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNI_CRB_AGT_ADR) |
| 296 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGND \ |
| 297 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGND_CRB_AGT_ADR) |
| 298 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGN0 \ |
| 299 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN0_CRB_AGT_ADR) |
| 300 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGN1 \ |
| 301 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN1_CRB_AGT_ADR) |
| 302 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGN2 \ |
| 303 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR) |
| 304 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \ |
| 305 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 306 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGN4 \ |
| 307 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN4_CRB_AGT_ADR) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 308 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \ |
| 309 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR) |
| 310 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \ |
| 311 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR0_CRB_AGT_ADR) |
| 312 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGR1 \ |
| 313 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR1_CRB_AGT_ADR) |
| 314 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGR2 \ |
| 315 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR2_CRB_AGT_ADR) |
| 316 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGR3 \ |
| 317 | ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR3_CRB_AGT_ADR) |
| 318 | |
| 319 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGSI \ |
| 320 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSI_CRB_AGT_ADR) |
| 321 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGSD \ |
| 322 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSD_CRB_AGT_ADR) |
| 323 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGS0 \ |
| 324 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS0_CRB_AGT_ADR) |
| 325 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGS1 \ |
| 326 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS1_CRB_AGT_ADR) |
| 327 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGS2 \ |
| 328 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS2_CRB_AGT_ADR) |
| 329 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGS3 \ |
| 330 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS3_CRB_AGT_ADR) |
| 331 | #define NETXEN_HW_CRB_HUB_AGT_ADR_PGSC \ |
| 332 | ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSC_CRB_AGT_ADR) |
| 333 | |
| 334 | #define NETXEN_HW_CRB_HUB_AGT_ADR_CAM \ |
| 335 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_NCM_CRB_AGT_ADR) |
| 336 | #define NETXEN_HW_CRB_HUB_AGT_ADR_TIMR \ |
| 337 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_TMR_CRB_AGT_ADR) |
| 338 | #define NETXEN_HW_CRB_HUB_AGT_ADR_XDMA \ |
| 339 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_XDMA_CRB_AGT_ADR) |
| 340 | #define NETXEN_HW_CRB_HUB_AGT_ADR_SN \ |
| 341 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_SN_CRB_AGT_ADR) |
| 342 | #define NETXEN_HW_CRB_HUB_AGT_ADR_I2Q \ |
| 343 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_I2Q_CRB_AGT_ADR) |
| 344 | #define NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB \ |
| 345 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_ROMUSB_CRB_AGT_ADR) |
| 346 | #define NETXEN_HW_CRB_HUB_AGT_ADR_OCM0 \ |
| 347 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM0_CRB_AGT_ADR) |
| 348 | #define NETXEN_HW_CRB_HUB_AGT_ADR_OCM1 \ |
| 349 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM1_CRB_AGT_ADR) |
| 350 | #define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \ |
| 351 | ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR) |
| 352 | |
Dhananjay Phadke | d173346 | 2009-06-17 17:27:24 +0000 | [diff] [blame] | 353 | #define NETXEN_SRE_MISC (NETXEN_CRB_SRE + 0x0002c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 354 | #define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034) |
| 355 | #define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014) |
| 356 | #define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000) |
| 357 | #define NETXEN_SRE_L2RE_CTL (NETXEN_CRB_SRE + 0x05000) |
| 358 | #define NETXEN_SRE_BUF_CTL (NETXEN_CRB_SRE + 0x01000) |
| 359 | |
| 360 | #define NETXEN_DMA_BASE(U) (NETXEN_CRB_PCIX_MD + 0x20000 + ((U)<<16)) |
| 361 | #define NETXEN_DMA_COMMAND(U) (NETXEN_DMA_BASE(U) + 0x00008) |
| 362 | |
| 363 | #define NETXEN_I2Q_CLR_PCI_HI (NETXEN_CRB_I2Q + 0x00034) |
| 364 | |
| 365 | #define PEG_NETWORK_BASE(N) (NETXEN_CRB_PEG_NET_0 + (((N)&3) << 20)) |
| 366 | #define CRB_REG_EX_PC 0x3c |
| 367 | |
| 368 | #define ROMUSB_GLB (NETXEN_CRB_ROMUSB + 0x00000) |
| 369 | #define ROMUSB_ROM (NETXEN_CRB_ROMUSB + 0x10000) |
| 370 | |
| 371 | #define NETXEN_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) |
| 372 | #define NETXEN_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) |
| 373 | #define NETXEN_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) |
| 374 | #define NETXEN_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) |
| 375 | #define NETXEN_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) |
| 376 | #define NETXEN_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) |
| 377 | #define NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8) |
| 378 | |
| 379 | #define NETXEN_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n))) |
| 380 | |
| 381 | #define NETXEN_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) |
| 382 | #define NETXEN_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 383 | #define NETXEN_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 384 | #define NETXEN_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) |
| 385 | #define NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) |
| 386 | #define NETXEN_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) |
| 387 | |
| 388 | /* Lock IDs for ROM lock */ |
| 389 | #define ROM_LOCK_DRIVER 0x0d417340 |
| 390 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 391 | /****************************************************************************** |
| 392 | * |
| 393 | * Definitions specific to M25P flash |
| 394 | * |
| 395 | ******************************************************************************* |
| 396 | * Instructions |
| 397 | */ |
| 398 | #define M25P_INSTR_WREN 0x06 |
| 399 | #define M25P_INSTR_WRDI 0x04 |
| 400 | #define M25P_INSTR_RDID 0x9f |
| 401 | #define M25P_INSTR_RDSR 0x05 |
| 402 | #define M25P_INSTR_WRSR 0x01 |
| 403 | #define M25P_INSTR_READ 0x03 |
| 404 | #define M25P_INSTR_FAST_READ 0x0b |
| 405 | #define M25P_INSTR_PP 0x02 |
| 406 | #define M25P_INSTR_SE 0xd8 |
| 407 | #define M25P_INSTR_BE 0xc7 |
| 408 | #define M25P_INSTR_DP 0xb9 |
| 409 | #define M25P_INSTR_RES 0xab |
| 410 | |
| 411 | /* all are 1MB windows */ |
| 412 | |
| 413 | #define NETXEN_PCI_CRB_WINDOWSIZE 0x00100000 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 414 | #define NETXEN_PCI_CRB_WINDOW(A) \ |
| 415 | (NETXEN_PCI_CRBSPACE + (A)*NETXEN_PCI_CRB_WINDOWSIZE) |
| 416 | |
| 417 | #define NETXEN_CRB_NIU NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_NIU) |
| 418 | #define NETXEN_CRB_SRE NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SRE) |
| 419 | #define NETXEN_CRB_ROMUSB \ |
| 420 | NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB) |
| 421 | #define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q) |
Dhananjay Phadke | 8bee0a9 | 2009-10-21 19:39:01 +0000 | [diff] [blame] | 422 | #define NETXEN_CRB_I2C0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2C0) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 423 | #define NETXEN_CRB_SMB NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SMB) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 424 | #define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64) |
| 425 | |
| 426 | #define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH) |
| 427 | #define NETXEN_CRB_PCIX_HOST2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH2) |
| 428 | #define NETXEN_CRB_PEG_NET_0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN0) |
| 429 | #define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1) |
| 430 | #define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2) |
| 431 | #define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3) |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 432 | #define NETXEN_CRB_PEG_NET_4 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SQS2) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 433 | #define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND) |
| 434 | #define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI) |
| 435 | #define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 436 | #define NETXEN_CRB_QDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SN) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 437 | |
| 438 | #define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS) |
| 439 | #define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD |
| 440 | |
| 441 | #define ISR_INT_VECTOR (NETXEN_PCIX_PS_REG(PCIX_INT_VECTOR)) |
| 442 | #define ISR_INT_MASK (NETXEN_PCIX_PS_REG(PCIX_INT_MASK)) |
| 443 | #define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK)) |
| 444 | #define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS)) |
| 445 | #define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK)) |
Dhananjay Phadke | 443be79 | 2008-03-17 19:59:48 -0700 | [diff] [blame] | 446 | #define ISR_INT_TARGET_STATUS_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) |
| 447 | #define ISR_INT_TARGET_MASK_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) |
| 448 | #define ISR_INT_TARGET_STATUS_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) |
| 449 | #define ISR_INT_TARGET_MASK_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) |
| 450 | #define ISR_INT_TARGET_STATUS_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) |
| 451 | #define ISR_INT_TARGET_MASK_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 452 | #define ISR_INT_TARGET_STATUS_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) |
| 453 | #define ISR_INT_TARGET_MASK_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) |
| 454 | #define ISR_INT_TARGET_STATUS_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) |
| 455 | #define ISR_INT_TARGET_MASK_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) |
| 456 | #define ISR_INT_TARGET_STATUS_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) |
| 457 | #define ISR_INT_TARGET_MASK_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) |
| 458 | #define ISR_INT_TARGET_STATUS_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) |
| 459 | #define ISR_INT_TARGET_MASK_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 460 | |
| 461 | #define NETXEN_PCI_MAPSIZE 128 |
| 462 | #define NETXEN_PCI_DDR_NET (0x00000000UL) |
| 463 | #define NETXEN_PCI_QDR_NET (0x04000000UL) |
| 464 | #define NETXEN_PCI_DIRECT_CRB (0x04400000UL) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 465 | #define NETXEN_PCI_CAMQM (0x04800000UL) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 466 | #define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL) |
| 467 | #define NETXEN_PCI_OCM0 (0x05000000UL) |
| 468 | #define NETXEN_PCI_OCM0_MAX (0x050fffffUL) |
| 469 | #define NETXEN_PCI_OCM1 (0x05100000UL) |
| 470 | #define NETXEN_PCI_OCM1_MAX (0x051fffffUL) |
| 471 | #define NETXEN_PCI_CRBSPACE (0x06000000UL) |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 472 | #define NETXEN_PCI_128MB_SIZE (0x08000000UL) |
| 473 | #define NETXEN_PCI_32MB_SIZE (0x02000000UL) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 474 | #define NETXEN_PCI_2MB_SIZE (0x00200000UL) |
| 475 | |
| 476 | #define NETXEN_PCI_MN_2M (0) |
| 477 | #define NETXEN_PCI_MS_2M (0x80000) |
| 478 | #define NETXEN_PCI_OCM0_2M (0x000c0000UL) |
| 479 | #define NETXEN_PCI_CAMQM_2M_BASE (0x000ff800UL) |
| 480 | #define NETXEN_PCI_CAMQM_2M_END (0x04800800UL) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 481 | |
| 482 | #define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM) |
| 483 | |
| 484 | #define NETXEN_ADDR_DDR_NET (0x0000000000000000ULL) |
| 485 | #define NETXEN_ADDR_DDR_NET_MAX (0x000000000fffffffULL) |
| 486 | #define NETXEN_ADDR_OCM0 (0x0000000200000000ULL) |
| 487 | #define NETXEN_ADDR_OCM0_MAX (0x00000002000fffffULL) |
| 488 | #define NETXEN_ADDR_OCM1 (0x0000000200400000ULL) |
| 489 | #define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL) |
| 490 | #define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 491 | #define NETXEN_ADDR_QDR_NET_MAX_P2 (0x00000003003fffffULL) |
| 492 | #define NETXEN_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL) |
| 493 | |
| 494 | /* |
| 495 | * Register offsets for MN |
| 496 | */ |
| 497 | #define NETXEN_MIU_CONTROL (0x000) |
| 498 | #define NETXEN_MIU_MN_CONTROL (NETXEN_CRB_DDR_NET+NETXEN_MIU_CONTROL) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 499 | |
| 500 | /* 200ms delay in each loop */ |
| 501 | #define NETXEN_NIU_PHY_WAITLEN 200000 |
| 502 | /* 10 seconds before we give up */ |
| 503 | #define NETXEN_NIU_PHY_WAITMAX 50 |
| 504 | #define NETXEN_NIU_MAX_GBE_PORTS 4 |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 505 | #define NETXEN_NIU_MAX_XG_PORTS 2 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 506 | |
| 507 | #define NETXEN_NIU_MODE (NETXEN_CRB_NIU + 0x00000) |
| 508 | |
| 509 | #define NETXEN_NIU_XG_SINGLE_TERM (NETXEN_CRB_NIU + 0x00004) |
| 510 | #define NETXEN_NIU_XG_DRIVE_HI (NETXEN_CRB_NIU + 0x00008) |
| 511 | #define NETXEN_NIU_XG_DRIVE_LO (NETXEN_CRB_NIU + 0x0000c) |
| 512 | #define NETXEN_NIU_XG_DTX (NETXEN_CRB_NIU + 0x00010) |
| 513 | #define NETXEN_NIU_XG_DEQ (NETXEN_CRB_NIU + 0x00014) |
| 514 | #define NETXEN_NIU_XG_WORD_ALIGN (NETXEN_CRB_NIU + 0x00018) |
| 515 | #define NETXEN_NIU_XG_RESET (NETXEN_CRB_NIU + 0x0001c) |
| 516 | #define NETXEN_NIU_XG_POWER_DOWN (NETXEN_CRB_NIU + 0x00020) |
| 517 | #define NETXEN_NIU_XG_RESET_PLL (NETXEN_CRB_NIU + 0x00024) |
| 518 | #define NETXEN_NIU_XG_SERDES_LOOPBACK (NETXEN_CRB_NIU + 0x00028) |
| 519 | #define NETXEN_NIU_XG_DO_BYTE_ALIGN (NETXEN_CRB_NIU + 0x0002c) |
| 520 | #define NETXEN_NIU_XG_TX_ENABLE (NETXEN_CRB_NIU + 0x00030) |
| 521 | #define NETXEN_NIU_XG_RX_ENABLE (NETXEN_CRB_NIU + 0x00034) |
| 522 | #define NETXEN_NIU_XG_STATUS (NETXEN_CRB_NIU + 0x00038) |
| 523 | #define NETXEN_NIU_XG_PAUSE_THRESHOLD (NETXEN_CRB_NIU + 0x0003c) |
| 524 | #define NETXEN_NIU_INT_MASK (NETXEN_CRB_NIU + 0x00040) |
| 525 | #define NETXEN_NIU_ACTIVE_INT (NETXEN_CRB_NIU + 0x00044) |
| 526 | #define NETXEN_NIU_MASKABLE_INT (NETXEN_CRB_NIU + 0x00048) |
| 527 | |
| 528 | #define NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER (NETXEN_CRB_NIU + 0x0004c) |
| 529 | |
| 530 | #define NETXEN_NIU_GB_SERDES_RESET (NETXEN_CRB_NIU + 0x00050) |
| 531 | #define NETXEN_NIU_GB0_GMII_MODE (NETXEN_CRB_NIU + 0x00054) |
| 532 | #define NETXEN_NIU_GB0_MII_MODE (NETXEN_CRB_NIU + 0x00058) |
| 533 | #define NETXEN_NIU_GB1_GMII_MODE (NETXEN_CRB_NIU + 0x0005c) |
| 534 | #define NETXEN_NIU_GB1_MII_MODE (NETXEN_CRB_NIU + 0x00060) |
| 535 | #define NETXEN_NIU_GB2_GMII_MODE (NETXEN_CRB_NIU + 0x00064) |
| 536 | #define NETXEN_NIU_GB2_MII_MODE (NETXEN_CRB_NIU + 0x00068) |
| 537 | #define NETXEN_NIU_GB3_GMII_MODE (NETXEN_CRB_NIU + 0x0006c) |
| 538 | #define NETXEN_NIU_GB3_MII_MODE (NETXEN_CRB_NIU + 0x00070) |
| 539 | #define NETXEN_NIU_REMOTE_LOOPBACK (NETXEN_CRB_NIU + 0x00074) |
| 540 | #define NETXEN_NIU_GB0_HALF_DUPLEX (NETXEN_CRB_NIU + 0x00078) |
| 541 | #define NETXEN_NIU_GB1_HALF_DUPLEX (NETXEN_CRB_NIU + 0x0007c) |
| 542 | #define NETXEN_NIU_RESET_SYS_FIFOS (NETXEN_CRB_NIU + 0x00088) |
| 543 | #define NETXEN_NIU_GB_CRC_DROP (NETXEN_CRB_NIU + 0x0008c) |
| 544 | #define NETXEN_NIU_GB_DROP_WRONGADDR (NETXEN_CRB_NIU + 0x00090) |
| 545 | #define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094) |
| 546 | #define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098) |
| 547 | #define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc) |
Narender Kumar | a7483b0 | 2009-11-20 15:09:33 +0000 | [diff] [blame] | 548 | #define NETXEN_NIU_FRAME_COUNT_SELECT (NETXEN_CRB_NIU + 0x000ac) |
| 549 | #define NETXEN_NIU_FRAME_COUNT (NETXEN_CRB_NIU + 0x000b0) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 550 | #define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128) |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 551 | #define NETXEN_NIU_GB_PAUSE_CTL (NETXEN_CRB_NIU + 0x0030c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 552 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 553 | #define NETXEN_NIU_FULL_LEVEL_XG (NETXEN_CRB_NIU + 0x00450) |
| 554 | |
| 555 | #define NETXEN_NIU_XG1_RESET (NETXEN_CRB_NIU + 0x0011c) |
| 556 | #define NETXEN_NIU_XG1_POWER_DOWN (NETXEN_CRB_NIU + 0x00120) |
| 557 | #define NETXEN_NIU_XG1_RESET_PLL (NETXEN_CRB_NIU + 0x00124) |
| 558 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 559 | #define NETXEN_MAC_ADDR_CNTL_REG (NETXEN_CRB_NIU + 0x1000) |
| 560 | |
| 561 | #define NETXEN_MULTICAST_ADDR_HI_0 (NETXEN_CRB_NIU + 0x1010) |
| 562 | #define NETXEN_MULTICAST_ADDR_HI_1 (NETXEN_CRB_NIU + 0x1014) |
| 563 | #define NETXEN_MULTICAST_ADDR_HI_2 (NETXEN_CRB_NIU + 0x1018) |
| 564 | #define NETXEN_MULTICAST_ADDR_HI_3 (NETXEN_CRB_NIU + 0x101c) |
| 565 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 566 | #define NETXEN_UNICAST_ADDR_BASE (NETXEN_CRB_NIU + 0x1080) |
| 567 | #define NETXEN_MULTICAST_ADDR_BASE (NETXEN_CRB_NIU + 0x1100) |
| 568 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 569 | #define NETXEN_NIU_GB_MAC_CONFIG_0(I) \ |
| 570 | (NETXEN_CRB_NIU + 0x30000 + (I)*0x10000) |
| 571 | #define NETXEN_NIU_GB_MAC_CONFIG_1(I) \ |
| 572 | (NETXEN_CRB_NIU + 0x30004 + (I)*0x10000) |
| 573 | #define NETXEN_NIU_GB_MAC_IPG_IFG(I) \ |
| 574 | (NETXEN_CRB_NIU + 0x30008 + (I)*0x10000) |
| 575 | #define NETXEN_NIU_GB_HALF_DUPLEX_CTRL(I) \ |
| 576 | (NETXEN_CRB_NIU + 0x3000c + (I)*0x10000) |
| 577 | #define NETXEN_NIU_GB_MAX_FRAME_SIZE(I) \ |
| 578 | (NETXEN_CRB_NIU + 0x30010 + (I)*0x10000) |
| 579 | #define NETXEN_NIU_GB_TEST_REG(I) \ |
| 580 | (NETXEN_CRB_NIU + 0x3001c + (I)*0x10000) |
| 581 | #define NETXEN_NIU_GB_MII_MGMT_CONFIG(I) \ |
| 582 | (NETXEN_CRB_NIU + 0x30020 + (I)*0x10000) |
| 583 | #define NETXEN_NIU_GB_MII_MGMT_COMMAND(I) \ |
| 584 | (NETXEN_CRB_NIU + 0x30024 + (I)*0x10000) |
| 585 | #define NETXEN_NIU_GB_MII_MGMT_ADDR(I) \ |
| 586 | (NETXEN_CRB_NIU + 0x30028 + (I)*0x10000) |
| 587 | #define NETXEN_NIU_GB_MII_MGMT_CTRL(I) \ |
| 588 | (NETXEN_CRB_NIU + 0x3002c + (I)*0x10000) |
| 589 | #define NETXEN_NIU_GB_MII_MGMT_STATUS(I) \ |
| 590 | (NETXEN_CRB_NIU + 0x30030 + (I)*0x10000) |
| 591 | #define NETXEN_NIU_GB_MII_MGMT_INDICATE(I) \ |
| 592 | (NETXEN_CRB_NIU + 0x30034 + (I)*0x10000) |
| 593 | #define NETXEN_NIU_GB_INTERFACE_CTRL(I) \ |
| 594 | (NETXEN_CRB_NIU + 0x30038 + (I)*0x10000) |
| 595 | #define NETXEN_NIU_GB_INTERFACE_STATUS(I) \ |
| 596 | (NETXEN_CRB_NIU + 0x3003c + (I)*0x10000) |
| 597 | #define NETXEN_NIU_GB_STATION_ADDR_0(I) \ |
| 598 | (NETXEN_CRB_NIU + 0x30040 + (I)*0x10000) |
| 599 | #define NETXEN_NIU_GB_STATION_ADDR_1(I) \ |
| 600 | (NETXEN_CRB_NIU + 0x30044 + (I)*0x10000) |
| 601 | |
| 602 | #define NETXEN_NIU_XGE_CONFIG_0 (NETXEN_CRB_NIU + 0x70000) |
| 603 | #define NETXEN_NIU_XGE_CONFIG_1 (NETXEN_CRB_NIU + 0x70004) |
| 604 | #define NETXEN_NIU_XGE_IPG (NETXEN_CRB_NIU + 0x70008) |
| 605 | #define NETXEN_NIU_XGE_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x7000c) |
| 606 | #define NETXEN_NIU_XGE_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x70010) |
| 607 | #define NETXEN_NIU_XGE_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x70014) |
| 608 | #define NETXEN_NIU_XGE_STATUS (NETXEN_CRB_NIU + 0x70018) |
| 609 | #define NETXEN_NIU_XGE_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x7001c) |
| 610 | #define NETXEN_NIU_XGE_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x70020) |
| 611 | #define NETXEN_NIU_XGE_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x70024) |
| 612 | #define NETXEN_NIU_XGE_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x70028) |
| 613 | #define NETXEN_NIU_XGE_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x7002c) |
| 614 | #define NETXEN_NIU_XGE_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x70030) |
| 615 | #define NETXEN_NIU_XGE_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x70034) |
| 616 | #define NETXEN_NIU_XGE_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x70038) |
| 617 | #define NETXEN_NIU_XGE_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x7003c) |
| 618 | #define NETXEN_NIU_XGE_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x70040) |
| 619 | #define NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70044) |
| 620 | #define NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70048) |
| 621 | #define NETXEN_NIU_XGE_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x7004c) |
| 622 | #define NETXEN_NIU_XGE_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x70050) |
| 623 | #define NETXEN_NIU_XGE_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x70054) |
| 624 | #define NETXEN_NIU_XGE_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x70058) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 625 | #define NETXEN_NIU_XG1_CONFIG_0 (NETXEN_CRB_NIU + 0x80000) |
| 626 | #define NETXEN_NIU_XG1_CONFIG_1 (NETXEN_CRB_NIU + 0x80004) |
| 627 | #define NETXEN_NIU_XG1_IPG (NETXEN_CRB_NIU + 0x80008) |
| 628 | #define NETXEN_NIU_XG1_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x8000c) |
| 629 | #define NETXEN_NIU_XG1_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x80010) |
| 630 | #define NETXEN_NIU_XG1_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x80014) |
| 631 | #define NETXEN_NIU_XG1_STATUS (NETXEN_CRB_NIU + 0x80018) |
| 632 | #define NETXEN_NIU_XG1_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x8001c) |
| 633 | #define NETXEN_NIU_XG1_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x80020) |
| 634 | #define NETXEN_NIU_XG1_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x80024) |
| 635 | #define NETXEN_NIU_XG1_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x80028) |
| 636 | #define NETXEN_NIU_XG1_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x8002c) |
| 637 | #define NETXEN_NIU_XG1_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x80030) |
| 638 | #define NETXEN_NIU_XG1_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x80034) |
| 639 | #define NETXEN_NIU_XG1_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x80038) |
| 640 | #define NETXEN_NIU_XG1_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x8003c) |
| 641 | #define NETXEN_NIU_XG1_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x80040) |
| 642 | #define NETXEN_NIU_XG1_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80044) |
| 643 | #define NETXEN_NIU_XG1_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80048) |
| 644 | #define NETXEN_NIU_XG1_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x8004c) |
| 645 | #define NETXEN_NIU_XG1_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x80050) |
| 646 | #define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054) |
| 647 | #define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 648 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 649 | /* P3 802.3ap */ |
| 650 | #define NETXEN_NIU_AP_MAC_CONFIG_0(I) (NETXEN_CRB_NIU+0xa0000+(I)*0x10000) |
| 651 | #define NETXEN_NIU_AP_MAC_CONFIG_1(I) (NETXEN_CRB_NIU+0xa0004+(I)*0x10000) |
| 652 | #define NETXEN_NIU_AP_MAC_IPG_IFG(I) (NETXEN_CRB_NIU+0xa0008+(I)*0x10000) |
| 653 | #define NETXEN_NIU_AP_HALF_DUPLEX_CTRL(I) (NETXEN_CRB_NIU+0xa000c+(I)*0x10000) |
| 654 | #define NETXEN_NIU_AP_MAX_FRAME_SIZE(I) (NETXEN_CRB_NIU+0xa0010+(I)*0x10000) |
| 655 | #define NETXEN_NIU_AP_TEST_REG(I) (NETXEN_CRB_NIU+0xa001c+(I)*0x10000) |
| 656 | #define NETXEN_NIU_AP_MII_MGMT_CONFIG(I) (NETXEN_CRB_NIU+0xa0020+(I)*0x10000) |
| 657 | #define NETXEN_NIU_AP_MII_MGMT_COMMAND(I) (NETXEN_CRB_NIU+0xa0024+(I)*0x10000) |
| 658 | #define NETXEN_NIU_AP_MII_MGMT_ADDR(I) (NETXEN_CRB_NIU+0xa0028+(I)*0x10000) |
| 659 | #define NETXEN_NIU_AP_MII_MGMT_CTRL(I) (NETXEN_CRB_NIU+0xa002c+(I)*0x10000) |
| 660 | #define NETXEN_NIU_AP_MII_MGMT_STATUS(I) (NETXEN_CRB_NIU+0xa0030+(I)*0x10000) |
| 661 | #define NETXEN_NIU_AP_MII_MGMT_INDICATE(I) (NETXEN_CRB_NIU+0xa0034+(I)*0x10000) |
| 662 | #define NETXEN_NIU_AP_INTERFACE_CTRL(I) (NETXEN_CRB_NIU+0xa0038+(I)*0x10000) |
| 663 | #define NETXEN_NIU_AP_INTERFACE_STATUS(I) (NETXEN_CRB_NIU+0xa003c+(I)*0x10000) |
| 664 | #define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000) |
| 665 | #define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000) |
| 666 | |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 667 | |
| 668 | #define TEST_AGT_CTRL (0x00) |
| 669 | |
| 670 | #define TA_CTL_START 1 |
| 671 | #define TA_CTL_ENABLE 2 |
| 672 | #define TA_CTL_WRITE 4 |
| 673 | #define TA_CTL_BUSY 8 |
| 674 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 675 | /* |
| 676 | * Register offsets for MN |
| 677 | */ |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 678 | #define MIU_TEST_AGT_BASE (0x90) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 679 | |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 680 | #define MIU_TEST_AGT_ADDR_LO (0x04) |
| 681 | #define MIU_TEST_AGT_ADDR_HI (0x08) |
| 682 | #define MIU_TEST_AGT_WRDATA_LO (0x10) |
| 683 | #define MIU_TEST_AGT_WRDATA_HI (0x14) |
Amit Kumar Salecha | fb1f6a4 | 2009-10-16 15:50:07 +0000 | [diff] [blame] | 684 | #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20) |
| 685 | #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24) |
| 686 | #define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1))) |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 687 | #define MIU_TEST_AGT_RDDATA_LO (0x18) |
| 688 | #define MIU_TEST_AGT_RDDATA_HI (0x1c) |
Amit Kumar Salecha | fb1f6a4 | 2009-10-16 15:50:07 +0000 | [diff] [blame] | 689 | #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28) |
| 690 | #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c) |
| 691 | #define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1))) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 692 | |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 693 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 |
| 694 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 695 | |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 696 | /* |
| 697 | * Register offsets for MS |
| 698 | */ |
| 699 | #define SIU_TEST_AGT_BASE (0x60) |
| 700 | |
| 701 | #define SIU_TEST_AGT_ADDR_LO (0x04) |
| 702 | #define SIU_TEST_AGT_ADDR_HI (0x18) |
| 703 | #define SIU_TEST_AGT_WRDATA_LO (0x08) |
| 704 | #define SIU_TEST_AGT_WRDATA_HI (0x0c) |
| 705 | #define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i))) |
| 706 | #define SIU_TEST_AGT_RDDATA_LO (0x10) |
| 707 | #define SIU_TEST_AGT_RDDATA_HI (0x14) |
| 708 | #define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i))) |
| 709 | |
| 710 | #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 |
| 711 | #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 712 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 713 | /* XG Link status */ |
| 714 | #define XG_LINK_UP 0x10 |
| 715 | #define XG_LINK_DOWN 0x20 |
| 716 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 717 | #define XG_LINK_UP_P3 0x01 |
| 718 | #define XG_LINK_DOWN_P3 0x02 |
| 719 | #define XG_LINK_STATE_P3_MASK 0xf |
| 720 | #define XG_LINK_STATE_P3(pcifn,val) \ |
| 721 | (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) |
| 722 | |
Dhananjay Phadke | 24a7a45 | 2008-08-01 03:14:55 -0700 | [diff] [blame] | 723 | #define P3_LINK_SPEED_MHZ 100 |
| 724 | #define P3_LINK_SPEED_MASK 0xff |
| 725 | #define P3_LINK_SPEED_REG(pcifn) \ |
| 726 | (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) |
| 727 | #define P3_LINK_SPEED_VAL(pcifn, reg) \ |
| 728 | (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK) |
| 729 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 730 | #define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000) |
| 731 | #define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg)) |
| 732 | #define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150)) |
| 733 | #define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154)) |
| 734 | #define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158)) |
| 735 | #define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100)) |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 736 | #define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120)) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 737 | #define NETXEN_CRB_WIN_LOCK_ID (NETXEN_CAM_RAM(0x124)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 738 | |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 739 | #define NIC_CRB_BASE (NETXEN_CAM_RAM(0x200)) |
| 740 | #define NIC_CRB_BASE_2 (NETXEN_CAM_RAM(0x700)) |
| 741 | #define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X)) |
| 742 | #define NETXEN_NIC_REG_2(X) (NIC_CRB_BASE_2+(X)) |
| 743 | |
| 744 | #define NX_CDRP_CRB_OFFSET (NETXEN_NIC_REG(0x18)) |
| 745 | #define NX_ARG1_CRB_OFFSET (NETXEN_NIC_REG(0x1c)) |
| 746 | #define NX_ARG2_CRB_OFFSET (NETXEN_NIC_REG(0x20)) |
| 747 | #define NX_ARG3_CRB_OFFSET (NETXEN_NIC_REG(0x24)) |
| 748 | #define NX_SIGN_CRB_OFFSET (NETXEN_NIC_REG(0x28)) |
| 749 | |
| 750 | #define CRB_HOST_DUMMY_BUF_ADDR_HI (NETXEN_NIC_REG(0x3c)) |
| 751 | #define CRB_HOST_DUMMY_BUF_ADDR_LO (NETXEN_NIC_REG(0x40)) |
| 752 | |
| 753 | #define CRB_CMDPEG_STATE (NETXEN_NIC_REG(0x50)) |
| 754 | #define CRB_RCVPEG_STATE (NETXEN_NIC_REG(0x13c)) |
| 755 | |
| 756 | #define CRB_XG_STATE (NETXEN_NIC_REG(0x94)) |
| 757 | #define CRB_XG_STATE_P3 (NETXEN_NIC_REG(0x98)) |
| 758 | #define CRB_PF_LINK_SPEED_1 (NETXEN_NIC_REG(0xe8)) |
| 759 | #define CRB_PF_LINK_SPEED_2 (NETXEN_NIC_REG(0xec)) |
| 760 | |
| 761 | #define CRB_MPORT_MODE (NETXEN_NIC_REG(0xc4)) |
| 762 | #define CRB_DMA_SHIFT (NETXEN_NIC_REG(0xcc)) |
| 763 | #define CRB_INT_VECTOR (NETXEN_NIC_REG(0xd4)) |
| 764 | |
| 765 | #define CRB_CMD_PRODUCER_OFFSET (NETXEN_NIC_REG(0x08)) |
| 766 | #define CRB_CMD_CONSUMER_OFFSET (NETXEN_NIC_REG(0x0c)) |
| 767 | #define CRB_CMD_PRODUCER_OFFSET_1 (NETXEN_NIC_REG(0x1ac)) |
| 768 | #define CRB_CMD_CONSUMER_OFFSET_1 (NETXEN_NIC_REG(0x1b0)) |
| 769 | #define CRB_CMD_PRODUCER_OFFSET_2 (NETXEN_NIC_REG(0x1b8)) |
| 770 | #define CRB_CMD_CONSUMER_OFFSET_2 (NETXEN_NIC_REG(0x1bc)) |
| 771 | #define CRB_CMD_PRODUCER_OFFSET_3 (NETXEN_NIC_REG(0x1d0)) |
| 772 | #define CRB_CMD_CONSUMER_OFFSET_3 (NETXEN_NIC_REG(0x1d4)) |
| 773 | #define CRB_TEMP_STATE (NETXEN_NIC_REG(0x1b4)) |
| 774 | |
| 775 | #define CRB_V2P_0 (NETXEN_NIC_REG(0x290)) |
| 776 | #define CRB_V2P(port) (CRB_V2P_0+((port)*4)) |
| 777 | #define CRB_DRIVER_VERSION (NETXEN_NIC_REG(0x2a0)) |
| 778 | |
| 779 | #define CRB_SW_INT_MASK_0 (NETXEN_NIC_REG(0x1d8)) |
| 780 | #define CRB_SW_INT_MASK_1 (NETXEN_NIC_REG(0x1e0)) |
| 781 | #define CRB_SW_INT_MASK_2 (NETXEN_NIC_REG(0x1e4)) |
| 782 | #define CRB_SW_INT_MASK_3 (NETXEN_NIC_REG(0x1e8)) |
| 783 | |
| 784 | #define CRB_FW_CAPABILITIES_1 (NETXEN_CAM_RAM(0x128)) |
| 785 | #define CRB_MAC_BLOCK_START (NETXEN_CAM_RAM(0x1c0)) |
| 786 | |
| 787 | /* |
| 788 | * capabilities register, can be used to selectively enable/disable features |
| 789 | * for backward compability |
| 790 | */ |
| 791 | #define CRB_NIC_CAPABILITIES_HOST NETXEN_NIC_REG(0x1a8) |
| 792 | #define CRB_NIC_CAPABILITIES_FW NETXEN_NIC_REG(0x1dc) |
| 793 | #define CRB_NIC_MSI_MODE_HOST NETXEN_NIC_REG(0x270) |
| 794 | #define CRB_NIC_MSI_MODE_FW NETXEN_NIC_REG(0x274) |
| 795 | |
| 796 | #define INTR_SCHEME_PERPORT 0x1 |
| 797 | #define MSI_MODE_MULTIFUNC 0x1 |
| 798 | |
| 799 | /* used for ethtool tests */ |
| 800 | #define CRB_SCRATCHPAD_TEST NETXEN_NIC_REG(0x280) |
| 801 | |
| 802 | /* |
| 803 | * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address |
| 804 | * which can be read by the Phantom host to get producer/consumer indexes from |
| 805 | * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following |
| 806 | * registers will be used for the addresses of the ring's shared memory |
| 807 | * on the Phantom. |
| 808 | */ |
| 809 | |
| 810 | #define nx_get_temp_val(x) ((x) >> 16) |
| 811 | #define nx_get_temp_state(x) ((x) & 0xffff) |
| 812 | #define nx_encode_temp(val, state) (((val) << 16) | (state)) |
| 813 | |
| 814 | /* |
| 815 | * Temperature control. |
| 816 | */ |
| 817 | enum { |
| 818 | NX_TEMP_NORMAL = 0x1, /* Normal operating range */ |
| 819 | NX_TEMP_WARN, /* Sound alert, temperature getting high */ |
| 820 | NX_TEMP_PANIC /* Fatal error, hardware has shut down. */ |
| 821 | }; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 822 | |
| 823 | /* Lock IDs for PHY lock */ |
| 824 | #define PHY_LOCK_DRIVER 0x44524956 |
| 825 | |
| 826 | /* Used for PS PCI Memory access */ |
| 827 | #define PCIX_PS_OP_ADDR_LO (0x10000) |
| 828 | /* via CRB (PS side only) */ |
| 829 | #define PCIX_PS_OP_ADDR_HI (0x10004) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 830 | |
| 831 | #define PCIX_INT_VECTOR (0x10100) |
| 832 | #define PCIX_INT_MASK (0x10104) |
| 833 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 834 | #define PCIX_CRB_WINDOW (0x10210) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 835 | #define PCIX_CRB_WINDOW_F0 (0x10210) |
| 836 | #define PCIX_CRB_WINDOW_F1 (0x10230) |
| 837 | #define PCIX_CRB_WINDOW_F2 (0x10250) |
| 838 | #define PCIX_CRB_WINDOW_F3 (0x10270) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 839 | #define PCIX_CRB_WINDOW_F4 (0x102ac) |
| 840 | #define PCIX_CRB_WINDOW_F5 (0x102bc) |
| 841 | #define PCIX_CRB_WINDOW_F6 (0x102cc) |
| 842 | #define PCIX_CRB_WINDOW_F7 (0x102dc) |
| 843 | #define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \ |
| 844 | (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) :\ |
| 845 | (PCIX_CRB_WINDOW_F4 + (0x10 * ((func)-4)))) |
| 846 | |
| 847 | #define PCIX_MN_WINDOW (0x10200) |
| 848 | #define PCIX_MN_WINDOW_F0 (0x10200) |
| 849 | #define PCIX_MN_WINDOW_F1 (0x10220) |
| 850 | #define PCIX_MN_WINDOW_F2 (0x10240) |
| 851 | #define PCIX_MN_WINDOW_F3 (0x10260) |
| 852 | #define PCIX_MN_WINDOW_F4 (0x102a0) |
| 853 | #define PCIX_MN_WINDOW_F5 (0x102b0) |
| 854 | #define PCIX_MN_WINDOW_F6 (0x102c0) |
| 855 | #define PCIX_MN_WINDOW_F7 (0x102d0) |
| 856 | #define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \ |
| 857 | (PCIX_MN_WINDOW_F0 + (0x20 * (func))) :\ |
| 858 | (PCIX_MN_WINDOW_F4 + (0x10 * ((func)-4)))) |
| 859 | |
| 860 | #define PCIX_SN_WINDOW (0x10208) |
| 861 | #define PCIX_SN_WINDOW_F0 (0x10208) |
| 862 | #define PCIX_SN_WINDOW_F1 (0x10228) |
| 863 | #define PCIX_SN_WINDOW_F2 (0x10248) |
| 864 | #define PCIX_SN_WINDOW_F3 (0x10268) |
| 865 | #define PCIX_SN_WINDOW_F4 (0x102a8) |
| 866 | #define PCIX_SN_WINDOW_F5 (0x102b8) |
| 867 | #define PCIX_SN_WINDOW_F6 (0x102c8) |
| 868 | #define PCIX_SN_WINDOW_F7 (0x102d8) |
| 869 | #define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \ |
| 870 | (PCIX_SN_WINDOW_F0 + (0x20 * (func))) :\ |
| 871 | (PCIX_SN_WINDOW_F4 + (0x10 * ((func)-4)))) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 872 | |
Amit Kumar Salecha | 6abb4b8 | 2009-10-16 15:50:09 +0000 | [diff] [blame] | 873 | #define PCIX_OCM_WINDOW (0x10800) |
| 874 | #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x20 * (func)) |
| 875 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 876 | #define PCIX_TARGET_STATUS (0x10118) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 877 | #define PCIX_TARGET_STATUS_F1 (0x10160) |
| 878 | #define PCIX_TARGET_STATUS_F2 (0x10164) |
| 879 | #define PCIX_TARGET_STATUS_F3 (0x10168) |
| 880 | #define PCIX_TARGET_STATUS_F4 (0x10360) |
| 881 | #define PCIX_TARGET_STATUS_F5 (0x10364) |
| 882 | #define PCIX_TARGET_STATUS_F6 (0x10368) |
| 883 | #define PCIX_TARGET_STATUS_F7 (0x1036c) |
| 884 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 885 | #define PCIX_TARGET_MASK (0x10128) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 886 | #define PCIX_TARGET_MASK_F1 (0x10170) |
| 887 | #define PCIX_TARGET_MASK_F2 (0x10174) |
| 888 | #define PCIX_TARGET_MASK_F3 (0x10178) |
| 889 | #define PCIX_TARGET_MASK_F4 (0x10370) |
| 890 | #define PCIX_TARGET_MASK_F5 (0x10374) |
| 891 | #define PCIX_TARGET_MASK_F6 (0x10378) |
| 892 | #define PCIX_TARGET_MASK_F7 (0x1037c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 893 | |
| 894 | #define PCIX_MSI_F0 (0x13000) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 895 | #define PCIX_MSI_F1 (0x13004) |
| 896 | #define PCIX_MSI_F2 (0x13008) |
| 897 | #define PCIX_MSI_F3 (0x1300c) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 898 | #define PCIX_MSI_F4 (0x13010) |
| 899 | #define PCIX_MSI_F5 (0x13014) |
| 900 | #define PCIX_MSI_F6 (0x13018) |
| 901 | #define PCIX_MSI_F7 (0x1301c) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 902 | #define PCIX_MSI_F(i) (0x13000+((i)*4)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 903 | |
| 904 | #define PCIX_PS_MEM_SPACE (0x90000) |
| 905 | |
| 906 | #define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg)) |
| 907 | #define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg)) |
| 908 | |
| 909 | #define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg)) |
| 910 | |
| 911 | #define PCIE_MAX_DMA_XFER_SIZE (0x1404c) |
| 912 | |
| 913 | #define PCIE_DCR 0x00d8 |
| 914 | |
Dhananjay Phadke | c9517e5 | 2009-08-24 19:23:26 +0000 | [diff] [blame] | 915 | #define PCIE_SEM0_LOCK (0x1c000) |
| 916 | #define PCIE_SEM0_UNLOCK (0x1c004) |
| 917 | #define PCIE_SEM1_LOCK (0x1c008) |
| 918 | #define PCIE_SEM1_UNLOCK (0x1c00c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 919 | #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ |
| 920 | #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 921 | #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ |
| 922 | #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ |
Dhananjay Phadke | c9517e5 | 2009-08-24 19:23:26 +0000 | [diff] [blame] | 923 | #define PCIE_SEM4_LOCK (0x1c020) |
| 924 | #define PCIE_SEM4_UNLOCK (0x1c024) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 925 | #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ |
| 926 | #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ |
| 927 | #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ |
| 928 | #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ |
| 929 | #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ |
| 930 | #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ |
Dhananjay Phadke | c9517e5 | 2009-08-24 19:23:26 +0000 | [diff] [blame] | 931 | #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) |
| 932 | #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 933 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 934 | #define PCIE_SETUP_FUNCTION (0x12040) |
| 935 | #define PCIE_SETUP_FUNCTION2 (0x12048) |
Dhananjay Phadke | d71e1be | 2008-08-01 03:14:57 -0700 | [diff] [blame] | 936 | #define PCIE_MISCCFG_RC (0x1206c) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 937 | #define PCIE_TGT_SPLIT_CHICKEN (0x12080) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 938 | #define PCIE_CHICKEN3 (0x120c8) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 939 | |
Dhananjay Phadke | d71e1be | 2008-08-01 03:14:57 -0700 | [diff] [blame] | 940 | #define ISR_INT_STATE_REG (NETXEN_PCIX_PS_REG(PCIE_MISCCFG_RC)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 941 | #define PCIE_MAX_MASTER_SPLIT (0x14048) |
| 942 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 943 | #define NETXEN_PORT_MODE_NONE 0 |
| 944 | #define NETXEN_PORT_MODE_XG 1 |
| 945 | #define NETXEN_PORT_MODE_GB 2 |
| 946 | #define NETXEN_PORT_MODE_802_3_AP 3 |
| 947 | #define NETXEN_PORT_MODE_AUTO_NEG 4 |
| 948 | #define NETXEN_PORT_MODE_AUTO_NEG_1G 5 |
| 949 | #define NETXEN_PORT_MODE_AUTO_NEG_XG 6 |
| 950 | #define NETXEN_PORT_MODE_ADDR (NETXEN_CAM_RAM(0x24)) |
| 951 | #define NETXEN_WOL_PORT_MODE (NETXEN_CAM_RAM(0x198)) |
| 952 | |
Dhananjay Phadke | 4da1294 | 2009-02-24 16:38:44 -0800 | [diff] [blame] | 953 | #define NETXEN_WOL_CONFIG_NV (NETXEN_CAM_RAM(0x184)) |
| 954 | #define NETXEN_WOL_CONFIG (NETXEN_CAM_RAM(0x188)) |
| 955 | |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 956 | #define NX_PEG_TUNE_MN_PRESENT 0x1 |
| 957 | #define NX_PEG_TUNE_CAPABILITY (NETXEN_CAM_RAM(0x02c)) |
| 958 | |
Dhananjay Phadke | 83ac51f | 2009-07-26 20:07:39 +0000 | [diff] [blame] | 959 | #define NETXEN_DMA_WATCHDOG_CTRL (NETXEN_CAM_RAM(0x14)) |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 960 | #define NETXEN_PEG_ALIVE_COUNTER (NETXEN_CAM_RAM(0xb0)) |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 961 | #define NETXEN_PEG_HALT_STATUS1 (NETXEN_CAM_RAM(0xa8)) |
| 962 | #define NETXEN_PEG_HALT_STATUS2 (NETXEN_CAM_RAM(0xac)) |
| 963 | #define NX_CRB_DEV_REF_COUNT (NETXEN_CAM_RAM(0x138)) |
| 964 | #define NX_CRB_DEV_STATE (NETXEN_CAM_RAM(0x140)) |
| 965 | |
| 966 | /* Device State */ |
| 967 | #define NX_DEV_COLD 1 |
| 968 | #define NX_DEV_INITALIZING 2 |
| 969 | #define NX_DEV_READY 3 |
| 970 | #define NX_DEV_NEED_RESET 4 |
| 971 | #define NX_DEV_NEED_QUISCENT 5 |
| 972 | #define NX_DEV_FAILED 6 |
| 973 | |
| 974 | #define NX_RCODE_DRIVER_INFO 0x20000000 |
| 975 | #define NX_RCODE_DRIVER_CAN_RELOAD 0x40000000 |
| 976 | #define NX_RCODE_FATAL_ERROR 0x80000000 |
| 977 | #define NX_FWERROR_PEGNUM(code) ((code) & 0xff) |
| 978 | #define NX_FWERROR_CODE(code) ((code >> 8) & 0xfffff) |
| 979 | |
| 980 | #define FW_POLL_DELAY (2 * HZ) |
| 981 | #define FW_FAIL_THRESH 3 |
| 982 | #define FW_POLL_THRESH 10 |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 983 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 984 | #define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC))) |
Dhananjay Phadke | d71e1be | 2008-08-01 03:14:57 -0700 | [diff] [blame] | 985 | #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 986 | |
| 987 | /* |
| 988 | * PCI Interrupt Vector Values. |
| 989 | */ |
| 990 | #define PCIX_INT_VECTOR_BIT_F0 0x0080 |
| 991 | #define PCIX_INT_VECTOR_BIT_F1 0x0100 |
| 992 | #define PCIX_INT_VECTOR_BIT_F2 0x0200 |
| 993 | #define PCIX_INT_VECTOR_BIT_F3 0x0400 |
| 994 | #define PCIX_INT_VECTOR_BIT_F4 0x0800 |
| 995 | #define PCIX_INT_VECTOR_BIT_F5 0x1000 |
| 996 | #define PCIX_INT_VECTOR_BIT_F6 0x2000 |
| 997 | #define PCIX_INT_VECTOR_BIT_F7 0x4000 |
| 998 | |
| 999 | struct netxen_legacy_intr_set { |
| 1000 | uint32_t int_vec_bit; |
| 1001 | uint32_t tgt_status_reg; |
| 1002 | uint32_t tgt_mask_reg; |
| 1003 | uint32_t pci_int_reg; |
| 1004 | }; |
| 1005 | |
| 1006 | #define NX_LEGACY_INTR_CONFIG \ |
| 1007 | { \ |
| 1008 | { \ |
| 1009 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ |
| 1010 | .tgt_status_reg = ISR_INT_TARGET_STATUS, \ |
| 1011 | .tgt_mask_reg = ISR_INT_TARGET_MASK, \ |
| 1012 | .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ |
| 1013 | \ |
| 1014 | { \ |
| 1015 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ |
| 1016 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ |
| 1017 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ |
| 1018 | .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ |
| 1019 | \ |
| 1020 | { \ |
| 1021 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ |
| 1022 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ |
| 1023 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ |
| 1024 | .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ |
| 1025 | \ |
| 1026 | { \ |
| 1027 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ |
| 1028 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ |
| 1029 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ |
| 1030 | .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ |
| 1031 | \ |
| 1032 | { \ |
| 1033 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ |
| 1034 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ |
| 1035 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ |
| 1036 | .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ |
| 1037 | \ |
| 1038 | { \ |
| 1039 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ |
| 1040 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ |
| 1041 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ |
| 1042 | .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ |
| 1043 | \ |
| 1044 | { \ |
| 1045 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ |
| 1046 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ |
| 1047 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ |
| 1048 | .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ |
| 1049 | \ |
| 1050 | { \ |
| 1051 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ |
| 1052 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ |
| 1053 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ |
| 1054 | .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ |
| 1055 | } |
| 1056 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1057 | #endif /* __NETXEN_NIC_HDR_H_ */ |