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gerrit-public.fairphone.software / kernel / msm-4.19 / efeedcf2a9137c9be0b833cb76b05315fe231197 / . / arch / arm / boot / dts / am33xx.dtsi
blob: b4e3e4793b95f4f2b9dc30b8e574fd9f799e5a04 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 serial5 = &uart6;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame^]28
29 /*
30 * To consider voltage drop between PMIC and SoC,
31 * tolerance value is reduced to 2% from 4% and
32 * voltage value is increased as a precaution.
33 */
34 operating-points = <
35 /* kHz uV */
36 720000 1285000
37 600000 1225000
38 500000 1125000
39 275000 1125000
40 >;
41 voltage-tolerance = <2>; /* 2 percentage */
42 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 };
44 };
45
46 /*
47 * The soc node represents the soc top level view. It is uses for IPs
48 * that are not memory mapped in the MPU view or for the MPU itself.
49 */
50 soc {
51 compatible = "ti,omap-infra";
52 mpu {
53 compatible = "ti,omap3-mpu";
54 ti,hwmods = "mpu";
55 };
56 };
57
58 /*
59 * XXX: Use a flat representation of the AM33XX interconnect.
60 * The real AM33XX interconnect network is quite complex.Since
61 * that will not bring real advantage to represent that in DT
62 * for the moment, just use a fake OCP bus entry to represent
63 * the whole bus hierarchy.
64 */
65 ocp {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70 ti,hwmods = "l3_main";
71
72 intc: interrupt-controller@48200000 {
73 compatible = "ti,omap2-intc";
74 interrupt-controller;
75 #interrupt-cells = <1>;
76 ti,intc-size = <128>;
77 reg = <0x48200000 0x1000>;
78 };
79
80 gpio1: gpio@44e07000 {
81 compatible = "ti,omap4-gpio";
82 ti,hwmods = "gpio1";
83 gpio-controller;
84 #gpio-cells = <2>;
85 interrupt-controller;
86 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]87 reg = <0x44e07000 0x1000>;
88 interrupt-parent = <&intc>;
89 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 };
91
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]92 gpio2: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]93 compatible = "ti,omap4-gpio";
94 ti,hwmods = "gpio2";
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]99 reg = <0x4804c000 0x1000>;
100 interrupt-parent = <&intc>;
101 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]102 };
103
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]104 gpio3: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]105 compatible = "ti,omap4-gpio";
106 ti,hwmods = "gpio3";
107 gpio-controller;
108 #gpio-cells = <2>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]111 reg = <0x481ac000 0x1000>;
112 interrupt-parent = <&intc>;
113 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]114 };
115
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]116 gpio4: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]117 compatible = "ti,omap4-gpio";
118 ti,hwmods = "gpio4";
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]123 reg = <0x481ae000 0x1000>;
124 interrupt-parent = <&intc>;
125 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]126 };
127
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]128 uart1: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]129 compatible = "ti,omap3-uart";
130 ti,hwmods = "uart1";
131 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]132 reg = <0x44e09000 0x2000>;
133 interrupt-parent = <&intc>;
134 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]135 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]136 };
137
138 uart2: serial@48022000 {
139 compatible = "ti,omap3-uart";
140 ti,hwmods = "uart2";
141 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]142 reg = <0x48022000 0x2000>;
143 interrupt-parent = <&intc>;
144 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]145 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]146 };
147
148 uart3: serial@48024000 {
149 compatible = "ti,omap3-uart";
150 ti,hwmods = "uart3";
151 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 reg = <0x48024000 0x2000>;
153 interrupt-parent = <&intc>;
154 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]155 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 };
157
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]158 uart4: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]159 compatible = "ti,omap3-uart";
160 ti,hwmods = "uart4";
161 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]162 reg = <0x481a6000 0x2000>;
163 interrupt-parent = <&intc>;
164 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]165 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]166 };
167
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]168 uart5: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]169 compatible = "ti,omap3-uart";
170 ti,hwmods = "uart5";
171 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]172 reg = <0x481a8000 0x2000>;
173 interrupt-parent = <&intc>;
174 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]175 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]176 };
177
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]178 uart6: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]179 compatible = "ti,omap3-uart";
180 ti,hwmods = "uart6";
181 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]182 reg = <0x481aa000 0x2000>;
183 interrupt-parent = <&intc>;
184 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]185 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]188 i2c1: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 reg = <0x44e0b000 0x1000>;
194 interrupt-parent = <&intc>;
195 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]196 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]197 };
198
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]199 i2c2: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]200 compatible = "ti,omap4-i2c";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 reg = <0x4802a000 0x1000>;
205 interrupt-parent = <&intc>;
206 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]207 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]208 };
209
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]210 i2c3: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]211 compatible = "ti,omap4-i2c";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]215 reg = <0x4819c000 0x1000>;
216 interrupt-parent = <&intc>;
217 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]218 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]220
221 wdt2: wdt@44e35000 {
222 compatible = "ti,omap3-wdt";
223 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]224 reg = <0x44e35000 0x1000>;
225 interrupt-parent = <&intc>;
226 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]227 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]228 };
229};