Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | # |
| 2 | # For a description of the syntax of this configuration file, |
| 3 | # see Documentation/kbuild/kconfig-language.txt. |
| 4 | # |
| 5 | |
Mike Frysinger | 53f8a25 | 2007-11-15 15:48:01 +0800 | [diff] [blame] | 6 | mainmenu "Blackfin Kernel Configuration" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | |
| 8 | config MMU |
| 9 | bool |
| 10 | default n |
| 11 | |
| 12 | config FPU |
| 13 | bool |
| 14 | default n |
| 15 | |
| 16 | config RWSEM_GENERIC_SPINLOCK |
| 17 | bool |
| 18 | default y |
| 19 | |
| 20 | config RWSEM_XCHGADD_ALGORITHM |
| 21 | bool |
| 22 | default n |
| 23 | |
| 24 | config BLACKFIN |
| 25 | bool |
| 26 | default y |
Sam Ravnborg | ec7748b | 2008-02-09 10:46:40 +0100 | [diff] [blame] | 27 | select HAVE_IDE |
Mathieu Desnoyers | 42d4b83 | 2008-02-02 15:10:34 -0500 | [diff] [blame] | 28 | select HAVE_OPROFILE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 29 | |
Aubrey Li | e3defff | 2007-05-21 18:09:11 +0800 | [diff] [blame] | 30 | config ZONE_DMA |
| 31 | bool |
| 32 | default y |
| 33 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 34 | config GENERIC_FIND_NEXT_BIT |
| 35 | bool |
| 36 | default y |
| 37 | |
| 38 | config GENERIC_HWEIGHT |
| 39 | bool |
| 40 | default y |
| 41 | |
| 42 | config GENERIC_HARDIRQS |
| 43 | bool |
| 44 | default y |
| 45 | |
| 46 | config GENERIC_IRQ_PROBE |
Mike Frysinger | e4e9a7a | 2007-11-15 20:39:34 +0800 | [diff] [blame] | 47 | bool |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 48 | default y |
| 49 | |
Michael Hennerich | b2d1583 | 2007-07-24 15:46:36 +0800 | [diff] [blame] | 50 | config GENERIC_GPIO |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 51 | bool |
| 52 | default y |
| 53 | |
| 54 | config FORCE_MAX_ZONEORDER |
| 55 | int |
| 56 | default "14" |
| 57 | |
| 58 | config GENERIC_CALIBRATE_DELAY |
| 59 | bool |
| 60 | default y |
| 61 | |
Mathieu Desnoyers | 7d2284b | 2008-01-15 12:42:02 -0500 | [diff] [blame] | 62 | config HARDWARE_PM |
| 63 | def_bool y |
| 64 | depends on OPROFILE |
| 65 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 66 | source "init/Kconfig" |
| 67 | source "kernel/Kconfig.preempt" |
| 68 | |
| 69 | menu "Blackfin Processor Options" |
| 70 | |
| 71 | comment "Processor and Board Settings" |
| 72 | |
| 73 | choice |
| 74 | prompt "CPU" |
| 75 | default BF533 |
| 76 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 77 | config BF522 |
| 78 | bool "BF522" |
| 79 | help |
| 80 | BF522 Processor Support. |
| 81 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 82 | config BF523 |
| 83 | bool "BF523" |
| 84 | help |
| 85 | BF523 Processor Support. |
| 86 | |
| 87 | config BF524 |
| 88 | bool "BF524" |
| 89 | help |
| 90 | BF524 Processor Support. |
| 91 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 92 | config BF525 |
| 93 | bool "BF525" |
| 94 | help |
| 95 | BF525 Processor Support. |
| 96 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 97 | config BF526 |
| 98 | bool "BF526" |
| 99 | help |
| 100 | BF526 Processor Support. |
| 101 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 102 | config BF527 |
| 103 | bool "BF527" |
| 104 | help |
| 105 | BF527 Processor Support. |
| 106 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 107 | config BF531 |
| 108 | bool "BF531" |
| 109 | help |
| 110 | BF531 Processor Support. |
| 111 | |
| 112 | config BF532 |
| 113 | bool "BF532" |
| 114 | help |
| 115 | BF532 Processor Support. |
| 116 | |
| 117 | config BF533 |
| 118 | bool "BF533" |
| 119 | help |
| 120 | BF533 Processor Support. |
| 121 | |
| 122 | config BF534 |
| 123 | bool "BF534" |
| 124 | help |
| 125 | BF534 Processor Support. |
| 126 | |
| 127 | config BF536 |
| 128 | bool "BF536" |
| 129 | help |
| 130 | BF536 Processor Support. |
| 131 | |
| 132 | config BF537 |
| 133 | bool "BF537" |
| 134 | help |
| 135 | BF537 Processor Support. |
| 136 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 137 | config BF542 |
| 138 | bool "BF542" |
| 139 | help |
| 140 | BF542 Processor Support. |
| 141 | |
| 142 | config BF544 |
| 143 | bool "BF544" |
| 144 | help |
| 145 | BF544 Processor Support. |
| 146 | |
Mike Frysinger | 7c7fd17 | 2007-11-15 21:10:21 +0800 | [diff] [blame] | 147 | config BF547 |
| 148 | bool "BF547" |
| 149 | help |
| 150 | BF547 Processor Support. |
| 151 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 152 | config BF548 |
| 153 | bool "BF548" |
| 154 | help |
| 155 | BF548 Processor Support. |
| 156 | |
| 157 | config BF549 |
| 158 | bool "BF549" |
| 159 | help |
| 160 | BF549 Processor Support. |
| 161 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 162 | config BF561 |
| 163 | bool "BF561" |
| 164 | help |
Mike Frysinger | cd88b4d | 2008-10-09 12:03:22 +0800 | [diff] [blame] | 165 | BF561 Processor Support. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 166 | |
| 167 | endchoice |
| 168 | |
| 169 | choice |
| 170 | prompt "Silicon Rev" |
Mike Frysinger | 46ce0d9 | 2008-10-09 12:05:31 +0800 | [diff] [blame] | 171 | default BF_REV_0_1 if (BF52x || BF54x) |
| 172 | default BF_REV_0_2 if (BF534 || BF536 || BF537) |
| 173 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 174 | |
| 175 | config BF_REV_0_0 |
| 176 | bool "0.0" |
Mike Frysinger | d07f438 | 2007-11-15 15:49:17 +0800 | [diff] [blame] | 177 | depends on (BF52x || BF54x) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 178 | |
| 179 | config BF_REV_0_1 |
Mike Frysinger | d07f438 | 2007-11-15 15:49:17 +0800 | [diff] [blame] | 180 | bool "0.1" |
| 181 | depends on (BF52x || BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 182 | |
| 183 | config BF_REV_0_2 |
| 184 | bool "0.2" |
Mike Frysinger | 49f7253 | 2008-10-09 12:06:27 +0800 | [diff] [blame] | 185 | depends on (BF52x || BF537 || BF536 || BF534 || BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 186 | |
| 187 | config BF_REV_0_3 |
| 188 | bool "0.3" |
| 189 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
| 190 | |
| 191 | config BF_REV_0_4 |
| 192 | bool "0.4" |
| 193 | depends on (BF561 || BF533 || BF532 || BF531) |
| 194 | |
| 195 | config BF_REV_0_5 |
| 196 | bool "0.5" |
| 197 | depends on (BF561 || BF533 || BF532 || BF531) |
| 198 | |
Mike Frysinger | 49f7253 | 2008-10-09 12:06:27 +0800 | [diff] [blame] | 199 | config BF_REV_0_6 |
| 200 | bool "0.6" |
| 201 | depends on (BF533 || BF532 || BF531) |
| 202 | |
Jie Zhang | de3025f | 2007-06-25 18:04:12 +0800 | [diff] [blame] | 203 | config BF_REV_ANY |
| 204 | bool "any" |
| 205 | |
| 206 | config BF_REV_NONE |
| 207 | bool "none" |
| 208 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 209 | endchoice |
| 210 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 211 | config BF52x |
| 212 | bool |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 213 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 214 | default y |
| 215 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 216 | config BF53x |
| 217 | bool |
| 218 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) |
| 219 | default y |
| 220 | |
| 221 | config BF54x |
| 222 | bool |
Mike Frysinger | 7c7fd17 | 2007-11-15 21:10:21 +0800 | [diff] [blame] | 223 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 224 | default y |
| 225 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 226 | config MEM_GENERIC_BOARD |
| 227 | bool |
| 228 | depends on GENERIC_BOARD |
| 229 | default y |
| 230 | |
| 231 | config MEM_MT48LC64M4A2FB_7E |
| 232 | bool |
| 233 | depends on (BFIN533_STAMP) |
| 234 | default y |
| 235 | |
| 236 | config MEM_MT48LC16M16A2TG_75 |
| 237 | bool |
| 238 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ |
Javier Herrero | ab472a0 | 2007-10-29 16:14:44 +0800 | [diff] [blame] | 239 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
Michael Hennerich | 9db144f | 2008-07-19 17:16:07 +0800 | [diff] [blame] | 240 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 241 | default y |
| 242 | |
| 243 | config MEM_MT48LC32M8A2_75 |
| 244 | bool |
| 245 | depends on (BFIN537_STAMP || PNAV10) |
| 246 | default y |
| 247 | |
| 248 | config MEM_MT48LC8M32B2B5_7 |
| 249 | bool |
| 250 | depends on (BFIN561_BLUETECHNIX_CM) |
| 251 | default y |
| 252 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 253 | config MEM_MT48LC32M16A2TG_75 |
| 254 | bool |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 255 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 256 | default y |
| 257 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 258 | source "arch/blackfin/mach-bf527/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 259 | source "arch/blackfin/mach-bf533/Kconfig" |
| 260 | source "arch/blackfin/mach-bf561/Kconfig" |
| 261 | source "arch/blackfin/mach-bf537/Kconfig" |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 262 | source "arch/blackfin/mach-bf548/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 263 | |
| 264 | menu "Board customizations" |
| 265 | |
| 266 | config CMDLINE_BOOL |
| 267 | bool "Default bootloader kernel arguments" |
| 268 | |
| 269 | config CMDLINE |
| 270 | string "Initial kernel command string" |
| 271 | depends on CMDLINE_BOOL |
| 272 | default "console=ttyBF0,57600" |
| 273 | help |
| 274 | If you don't have a boot loader capable of passing a command line string |
| 275 | to the kernel, you may specify one here. As a minimum, you should specify |
| 276 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). |
| 277 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 278 | config BOOT_LOAD |
| 279 | hex "Kernel load address for booting" |
| 280 | default "0x1000" |
| 281 | range 0x1000 0x20000000 |
| 282 | help |
| 283 | This option allows you to set the load address of the kernel. |
| 284 | This can be useful if you are on a board which has a small amount |
| 285 | of memory or you wish to reserve some memory at the beginning of |
| 286 | the address space. |
| 287 | |
| 288 | Note that you need to keep this value above 4k (0x1000) as this |
| 289 | memory region is used to capture NULL pointer references as well |
| 290 | as some core kernel functions. |
| 291 | |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 292 | config ROM_BASE |
| 293 | hex "Kernel ROM Base" |
| 294 | default "0x20040000" |
| 295 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
| 296 | range 0x20000000 0x30000000 if (BF54x || BF561) |
| 297 | help |
| 298 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 299 | comment "Clock/PLL Setup" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 300 | |
| 301 | config CLKIN_HZ |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 302 | int "Frequency of the crystal on the board in Hz" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 303 | default "11059200" if BFIN533_STAMP |
| 304 | default "27000000" if BFIN533_EZKIT |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 305 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 306 | default "30000000" if BFIN561_EZKIT |
| 307 | default "24576000" if PNAV10 |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 308 | default "10000000" if BFIN532_IP0X |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 309 | help |
| 310 | The frequency of CLKIN crystal oscillator on the board in Hz. |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 311 | Warning: This value should match the crystal on the board. Otherwise, |
| 312 | peripherals won't work properly. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 313 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 314 | config BFIN_KERNEL_CLOCK |
| 315 | bool "Re-program Clocks while Kernel boots?" |
| 316 | default n |
| 317 | help |
| 318 | This option decides if kernel clocks are re-programed from the |
| 319 | bootloader settings. If the clocks are not set, the SDRAM settings |
| 320 | are also not changed, and the Bootloader does 100% of the hardware |
| 321 | configuration. |
| 322 | |
| 323 | config PLL_BYPASS |
Mike Frysinger | e4e9a7a | 2007-11-15 20:39:34 +0800 | [diff] [blame] | 324 | bool "Bypass PLL" |
| 325 | depends on BFIN_KERNEL_CLOCK |
| 326 | default n |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 327 | |
| 328 | config CLKIN_HALF |
| 329 | bool "Half Clock In" |
| 330 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 331 | default n |
| 332 | help |
| 333 | If this is set the clock will be divided by 2, before it goes to the PLL. |
| 334 | |
| 335 | config VCO_MULT |
| 336 | int "VCO Multiplier" |
| 337 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 338 | range 1 64 |
| 339 | default "22" if BFIN533_EZKIT |
| 340 | default "45" if BFIN533_STAMP |
Michael Hennerich | db68254 | 2008-04-24 03:18:59 +0800 | [diff] [blame] | 341 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 342 | default "22" if BFIN533_BLUETECHNIX_CM |
Michael Hennerich | 9db144f | 2008-07-19 17:16:07 +0800 | [diff] [blame] | 343 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 344 | default "20" if BFIN561_EZKIT |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 345 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 346 | help |
| 347 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. |
| 348 | PLL Frequency = (Crystal Frequency) * (this setting) |
| 349 | |
| 350 | choice |
| 351 | prompt "Core Clock Divider" |
| 352 | depends on BFIN_KERNEL_CLOCK |
| 353 | default CCLK_DIV_1 |
| 354 | help |
| 355 | This sets the frequency of the core. It can be 1, 2, 4 or 8 |
| 356 | Core Frequency = (PLL frequency) / (this setting) |
| 357 | |
| 358 | config CCLK_DIV_1 |
| 359 | bool "1" |
| 360 | |
| 361 | config CCLK_DIV_2 |
| 362 | bool "2" |
| 363 | |
| 364 | config CCLK_DIV_4 |
| 365 | bool "4" |
| 366 | |
| 367 | config CCLK_DIV_8 |
| 368 | bool "8" |
| 369 | endchoice |
| 370 | |
| 371 | config SCLK_DIV |
| 372 | int "System Clock Divider" |
| 373 | depends on BFIN_KERNEL_CLOCK |
| 374 | range 1 15 |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 375 | default 5 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 376 | help |
| 377 | This sets the frequency of the system clock (including SDRAM or DDR). |
| 378 | This can be between 1 and 15 |
| 379 | System Clock = (PLL frequency) / (this setting) |
| 380 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 381 | choice |
| 382 | prompt "DDR SDRAM Chip Type" |
| 383 | depends on BFIN_KERNEL_CLOCK |
| 384 | depends on BF54x |
| 385 | default MEM_MT46V32M16_5B |
| 386 | |
| 387 | config MEM_MT46V32M16_6T |
| 388 | bool "MT46V32M16_6T" |
| 389 | |
| 390 | config MEM_MT46V32M16_5B |
| 391 | bool "MT46V32M16_5B" |
| 392 | endchoice |
| 393 | |
Mike Frysinger | 7eb2c23 | 2008-10-08 17:39:02 +0800 | [diff] [blame] | 394 | config MAX_MEM_SIZE |
| 395 | int "Max SDRAM Memory Size in MBytes" |
| 396 | depends on !MPU |
| 397 | default 512 |
| 398 | help |
| 399 | This is the max memory size that the kernel will create CPLB |
| 400 | tables for. Your system will not be able to handle any more. |
| 401 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 402 | # |
| 403 | # Max & Min Speeds for various Chips |
| 404 | # |
| 405 | config MAX_VCO_HZ |
| 406 | int |
| 407 | default 600000000 if BF522 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 408 | default 400000000 if BF523 |
| 409 | default 400000000 if BF524 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 410 | default 600000000 if BF525 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 411 | default 400000000 if BF526 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 412 | default 600000000 if BF527 |
| 413 | default 400000000 if BF531 |
| 414 | default 400000000 if BF532 |
| 415 | default 750000000 if BF533 |
| 416 | default 500000000 if BF534 |
| 417 | default 400000000 if BF536 |
| 418 | default 600000000 if BF537 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 419 | default 533333333 if BF538 |
| 420 | default 533333333 if BF539 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 421 | default 600000000 if BF542 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 422 | default 533333333 if BF544 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 423 | default 600000000 if BF547 |
| 424 | default 600000000 if BF548 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 425 | default 533333333 if BF549 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 426 | default 600000000 if BF561 |
| 427 | |
| 428 | config MIN_VCO_HZ |
| 429 | int |
| 430 | default 50000000 |
| 431 | |
| 432 | config MAX_SCLK_HZ |
| 433 | int |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 434 | default 133333333 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 435 | |
| 436 | config MIN_SCLK_HZ |
| 437 | int |
| 438 | default 27000000 |
| 439 | |
| 440 | comment "Kernel Timer/Scheduler" |
| 441 | |
| 442 | source kernel/Kconfig.hz |
| 443 | |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 444 | config GENERIC_TIME |
| 445 | bool "Generic time" |
| 446 | default y |
| 447 | |
| 448 | config GENERIC_CLOCKEVENTS |
| 449 | bool "Generic clock events" |
| 450 | depends on GENERIC_TIME |
| 451 | default y |
| 452 | |
| 453 | config CYCLES_CLOCKSOURCE |
| 454 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" |
| 455 | depends on EXPERIMENTAL |
| 456 | depends on GENERIC_CLOCKEVENTS |
| 457 | depends on !BFIN_SCRATCH_REG_CYCLES |
| 458 | default n |
| 459 | help |
| 460 | If you say Y here, you will enable support for using the 'cycles' |
| 461 | registers as a clock source. Doing so means you will be unable to |
| 462 | safely write to the 'cycles' register during runtime. You will |
| 463 | still be able to read it (such as for performance monitoring), but |
| 464 | writing the registers will most likely crash the kernel. |
| 465 | |
| 466 | source kernel/time/Kconfig |
| 467 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 468 | comment "Misc" |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 469 | |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 470 | choice |
| 471 | prompt "Blackfin Exception Scratch Register" |
| 472 | default BFIN_SCRATCH_REG_RETN |
| 473 | help |
| 474 | Select the resource to reserve for the Exception handler: |
| 475 | - RETN: Non-Maskable Interrupt (NMI) |
| 476 | - RETE: Exception Return (JTAG/ICE) |
| 477 | - CYCLES: Performance counter |
| 478 | |
| 479 | If you are unsure, please select "RETN". |
| 480 | |
| 481 | config BFIN_SCRATCH_REG_RETN |
| 482 | bool "RETN" |
| 483 | help |
| 484 | Use the RETN register in the Blackfin exception handler |
| 485 | as a stack scratch register. This means you cannot |
| 486 | safely use NMI on the Blackfin while running Linux, but |
| 487 | you can debug the system with a JTAG ICE and use the |
| 488 | CYCLES performance registers. |
| 489 | |
| 490 | If you are unsure, please select "RETN". |
| 491 | |
| 492 | config BFIN_SCRATCH_REG_RETE |
| 493 | bool "RETE" |
| 494 | help |
| 495 | Use the RETE register in the Blackfin exception handler |
| 496 | as a stack scratch register. This means you cannot |
| 497 | safely use a JTAG ICE while debugging a Blackfin board, |
| 498 | but you can safely use the CYCLES performance registers |
| 499 | and the NMI. |
| 500 | |
| 501 | If you are unsure, please select "RETN". |
| 502 | |
| 503 | config BFIN_SCRATCH_REG_CYCLES |
| 504 | bool "CYCLES" |
| 505 | help |
| 506 | Use the CYCLES register in the Blackfin exception handler |
| 507 | as a stack scratch register. This means you cannot |
| 508 | safely use the CYCLES performance registers on a Blackfin |
| 509 | board at anytime, but you can debug the system with a JTAG |
| 510 | ICE and use the NMI. |
| 511 | |
| 512 | If you are unsure, please select "RETN". |
| 513 | |
| 514 | endchoice |
| 515 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 516 | endmenu |
| 517 | |
| 518 | |
| 519 | menu "Blackfin Kernel Optimizations" |
| 520 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 521 | comment "Memory Optimizations" |
| 522 | |
| 523 | config I_ENTRY_L1 |
| 524 | bool "Locate interrupt entry code in L1 Memory" |
| 525 | default y |
| 526 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 527 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
| 528 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 529 | |
| 530 | config EXCPT_IRQ_SYSC_L1 |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 531 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 532 | default y |
| 533 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 534 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 535 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 536 | (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 537 | |
| 538 | config DO_IRQ_L1 |
| 539 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" |
| 540 | default y |
| 541 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 542 | If enabled, the frequently called do_irq dispatcher function is linked |
| 543 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 544 | |
| 545 | config CORE_TIMER_IRQ_L1 |
| 546 | bool "Locate frequently called timer_interrupt() function in L1 Memory" |
| 547 | default y |
| 548 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 549 | If enabled, the frequently called timer_interrupt() function is linked |
| 550 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 551 | |
| 552 | config IDLE_L1 |
| 553 | bool "Locate frequently idle function in L1 Memory" |
| 554 | default y |
| 555 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 556 | If enabled, the frequently called idle function is linked |
| 557 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 558 | |
| 559 | config SCHEDULE_L1 |
| 560 | bool "Locate kernel schedule function in L1 Memory" |
| 561 | default y |
| 562 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 563 | If enabled, the frequently called kernel schedule is linked |
| 564 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 565 | |
| 566 | config ARITHMETIC_OPS_L1 |
| 567 | bool "Locate kernel owned arithmetic functions in L1 Memory" |
| 568 | default y |
| 569 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 570 | If enabled, arithmetic functions are linked |
| 571 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 572 | |
| 573 | config ACCESS_OK_L1 |
| 574 | bool "Locate access_ok function in L1 Memory" |
| 575 | default y |
| 576 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 577 | If enabled, the access_ok function is linked |
| 578 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 579 | |
| 580 | config MEMSET_L1 |
| 581 | bool "Locate memset function in L1 Memory" |
| 582 | default y |
| 583 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 584 | If enabled, the memset function is linked |
| 585 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 586 | |
| 587 | config MEMCPY_L1 |
| 588 | bool "Locate memcpy function in L1 Memory" |
| 589 | default y |
| 590 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 591 | If enabled, the memcpy function is linked |
| 592 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 593 | |
| 594 | config SYS_BFIN_SPINLOCK_L1 |
| 595 | bool "Locate sys_bfin_spinlock function in L1 Memory" |
| 596 | default y |
| 597 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 598 | If enabled, sys_bfin_spinlock function is linked |
| 599 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 600 | |
| 601 | config IP_CHECKSUM_L1 |
| 602 | bool "Locate IP Checksum function in L1 Memory" |
| 603 | default n |
| 604 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 605 | If enabled, the IP Checksum function is linked |
| 606 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 607 | |
| 608 | config CACHELINE_ALIGNED_L1 |
| 609 | bool "Locate cacheline_aligned data to L1 Data Memory" |
Michael Hennerich | 157cc5a | 2007-07-12 16:20:21 +0800 | [diff] [blame] | 610 | default y if !BF54x |
| 611 | default n if BF54x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 612 | depends on !BF531 |
| 613 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 614 | If enabled, cacheline_anligned data is linked |
| 615 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 616 | |
| 617 | config SYSCALL_TAB_L1 |
| 618 | bool "Locate Syscall Table L1 Data Memory" |
| 619 | default n |
| 620 | depends on !BF531 |
| 621 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 622 | If enabled, the Syscall LUT is linked |
| 623 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 624 | |
| 625 | config CPLB_SWITCH_TAB_L1 |
| 626 | bool "Locate CPLB Switch Tables L1 Data Memory" |
| 627 | default n |
| 628 | depends on !BF531 |
| 629 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 630 | If enabled, the CPLB Switch Tables are linked |
| 631 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 632 | |
Graf Yang | ca87b7a | 2008-10-08 17:30:01 +0800 | [diff] [blame] | 633 | config APP_STACK_L1 |
| 634 | bool "Support locating application stack in L1 Scratch Memory" |
| 635 | default y |
| 636 | help |
| 637 | If enabled the application stack can be located in L1 |
| 638 | scratch memory (less latency). |
| 639 | |
| 640 | Currently only works with FLAT binaries. |
| 641 | |
Robin Getz | 251383c | 2008-08-14 15:12:55 +0800 | [diff] [blame] | 642 | comment "Speed Optimizations" |
| 643 | config BFIN_INS_LOWOVERHEAD |
| 644 | bool "ins[bwl] low overhead, higher interrupt latency" |
| 645 | default y |
| 646 | help |
| 647 | Reads on the Blackfin are speculative. In Blackfin terms, this means |
| 648 | they can be interrupted at any time (even after they have been issued |
| 649 | on to the external bus), and re-issued after the interrupt occurs. |
| 650 | For memory - this is not a big deal, since memory does not change if |
| 651 | it sees a read. |
| 652 | |
| 653 | If a FIFO is sitting on the end of the read, it will see two reads, |
| 654 | when the core only sees one since the FIFO receives both the read |
| 655 | which is cancelled (and not delivered to the core) and the one which |
| 656 | is re-issued (which is delivered to the core). |
| 657 | |
| 658 | To solve this, interrupts are turned off before reads occur to |
| 659 | I/O space. This option controls which the overhead/latency of |
| 660 | controlling interrupts during this time |
| 661 | "n" turns interrupts off every read |
| 662 | (higher overhead, but lower interrupt latency) |
| 663 | "y" turns interrupts off every loop |
| 664 | (low overhead, but longer interrupt latency) |
| 665 | |
| 666 | default behavior is to leave this set to on (type "Y"). If you are experiencing |
| 667 | interrupt latency issues, it is safe and OK to turn this off. |
| 668 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 669 | endmenu |
| 670 | |
| 671 | |
| 672 | choice |
| 673 | prompt "Kernel executes from" |
| 674 | help |
| 675 | Choose the memory type that the kernel will be running in. |
| 676 | |
| 677 | config RAMKERNEL |
| 678 | bool "RAM" |
| 679 | help |
| 680 | The kernel will be resident in RAM when running. |
| 681 | |
| 682 | config ROMKERNEL |
| 683 | bool "ROM" |
| 684 | help |
| 685 | The kernel will be resident in FLASH/ROM when running. |
| 686 | |
| 687 | endchoice |
| 688 | |
| 689 | source "mm/Kconfig" |
| 690 | |
Mike Frysinger | 780431e | 2007-10-21 23:37:54 +0800 | [diff] [blame] | 691 | config BFIN_GPTIMERS |
| 692 | tristate "Enable Blackfin General Purpose Timers API" |
| 693 | default n |
| 694 | help |
| 695 | Enable support for the General Purpose Timers API. If you |
| 696 | are unsure, say N. |
| 697 | |
| 698 | To compile this driver as a module, choose M here: the module |
| 699 | will be called gptimers.ko. |
| 700 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 701 | config BFIN_DMA_5XX |
| 702 | bool "Enable DMA Support" |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 703 | depends on (BF52x || BF53x || BF561 || BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 704 | default y |
| 705 | help |
| 706 | DMA driver for BF5xx. |
| 707 | |
| 708 | choice |
| 709 | prompt "Uncached SDRAM region" |
| 710 | default DMA_UNCACHED_1M |
Adrian Bunk | 247537b | 2007-09-26 20:02:52 +0200 | [diff] [blame] | 711 | depends on BFIN_DMA_5XX |
Cliff Cai | 86ad793 | 2008-05-17 16:36:52 +0800 | [diff] [blame] | 712 | config DMA_UNCACHED_4M |
| 713 | bool "Enable 4M DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 714 | config DMA_UNCACHED_2M |
| 715 | bool "Enable 2M DMA region" |
| 716 | config DMA_UNCACHED_1M |
| 717 | bool "Enable 1M DMA region" |
| 718 | config DMA_UNCACHED_NONE |
| 719 | bool "Disable DMA region" |
| 720 | endchoice |
| 721 | |
| 722 | |
| 723 | comment "Cache Support" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 724 | config BFIN_ICACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 725 | bool "Enable ICACHE" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 726 | config BFIN_DCACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 727 | bool "Enable DCACHE" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 728 | config BFIN_DCACHE_BANKA |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 729 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 730 | depends on BFIN_DCACHE && !BF531 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 731 | default n |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 732 | config BFIN_ICACHE_LOCK |
| 733 | bool "Enable Instruction Cache Locking" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 734 | |
| 735 | choice |
| 736 | prompt "Policy" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 737 | depends on BFIN_DCACHE |
| 738 | default BFIN_WB |
| 739 | config BFIN_WB |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 740 | bool "Write back" |
| 741 | help |
| 742 | Write Back Policy: |
| 743 | Cached data will be written back to SDRAM only when needed. |
| 744 | This can give a nice increase in performance, but beware of |
| 745 | broken drivers that do not properly invalidate/flush their |
| 746 | cache. |
| 747 | |
| 748 | Write Through Policy: |
| 749 | Cached data will always be written back to SDRAM when the |
| 750 | cache is updated. This is a completely safe setting, but |
| 751 | performance is worse than Write Back. |
| 752 | |
| 753 | If you are unsure of the options and you want to be safe, |
| 754 | then go with Write Through. |
| 755 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 756 | config BFIN_WT |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 757 | bool "Write through" |
| 758 | help |
| 759 | Write Back Policy: |
| 760 | Cached data will be written back to SDRAM only when needed. |
| 761 | This can give a nice increase in performance, but beware of |
| 762 | broken drivers that do not properly invalidate/flush their |
| 763 | cache. |
| 764 | |
| 765 | Write Through Policy: |
| 766 | Cached data will always be written back to SDRAM when the |
| 767 | cache is updated. This is a completely safe setting, but |
| 768 | performance is worse than Write Back. |
| 769 | |
| 770 | If you are unsure of the options and you want to be safe, |
| 771 | then go with Write Through. |
| 772 | |
| 773 | endchoice |
| 774 | |
Sonic Zhang | f099f39 | 2008-10-09 14:11:57 +0800 | [diff] [blame^] | 775 | config BFIN_L2_CACHEABLE |
| 776 | bool "Cache L2 SRAM" |
| 777 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) |
| 778 | default n |
| 779 | help |
| 780 | Select to make L2 SRAM cacheable in L1 data and instruction cache. |
| 781 | |
Bernd Schmidt | b97b8a9 | 2008-01-27 18:39:16 +0800 | [diff] [blame] | 782 | config MPU |
| 783 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
| 784 | default n |
| 785 | help |
| 786 | Use the processor's MPU to protect applications from accessing |
| 787 | memory they do not own. This comes at a performance penalty |
| 788 | and is recommended only for debugging. |
| 789 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 790 | comment "Asynchonous Memory Configuration" |
| 791 | |
Mike Frysinger | ddf416b | 2007-10-10 18:06:47 +0800 | [diff] [blame] | 792 | menu "EBIU_AMGCTL Global Control" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 793 | config C_AMCKEN |
| 794 | bool "Enable CLKOUT" |
| 795 | default y |
| 796 | |
| 797 | config C_CDPRIO |
| 798 | bool "DMA has priority over core for ext. accesses" |
| 799 | default n |
| 800 | |
| 801 | config C_B0PEN |
| 802 | depends on BF561 |
| 803 | bool "Bank 0 16 bit packing enable" |
| 804 | default y |
| 805 | |
| 806 | config C_B1PEN |
| 807 | depends on BF561 |
| 808 | bool "Bank 1 16 bit packing enable" |
| 809 | default y |
| 810 | |
| 811 | config C_B2PEN |
| 812 | depends on BF561 |
| 813 | bool "Bank 2 16 bit packing enable" |
| 814 | default y |
| 815 | |
| 816 | config C_B3PEN |
| 817 | depends on BF561 |
| 818 | bool "Bank 3 16 bit packing enable" |
| 819 | default n |
| 820 | |
| 821 | choice |
| 822 | prompt"Enable Asynchonous Memory Banks" |
| 823 | default C_AMBEN_ALL |
| 824 | |
| 825 | config C_AMBEN |
| 826 | bool "Disable All Banks" |
| 827 | |
| 828 | config C_AMBEN_B0 |
| 829 | bool "Enable Bank 0" |
| 830 | |
| 831 | config C_AMBEN_B0_B1 |
| 832 | bool "Enable Bank 0 & 1" |
| 833 | |
| 834 | config C_AMBEN_B0_B1_B2 |
| 835 | bool "Enable Bank 0 & 1 & 2" |
| 836 | |
| 837 | config C_AMBEN_ALL |
| 838 | bool "Enable All Banks" |
| 839 | endchoice |
| 840 | endmenu |
| 841 | |
| 842 | menu "EBIU_AMBCTL Control" |
| 843 | config BANK_0 |
| 844 | hex "Bank 0" |
| 845 | default 0x7BB0 |
| 846 | |
| 847 | config BANK_1 |
| 848 | hex "Bank 1" |
| 849 | default 0x7BB0 |
Michael Hennerich | 197fba5 | 2008-05-07 17:03:27 +0800 | [diff] [blame] | 850 | default 0x5558 if BF54x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 851 | |
| 852 | config BANK_2 |
| 853 | hex "Bank 2" |
| 854 | default 0x7BB0 |
| 855 | |
| 856 | config BANK_3 |
| 857 | hex "Bank 3" |
| 858 | default 0x99B3 |
| 859 | endmenu |
| 860 | |
Sonic Zhang | e40540b | 2007-11-21 23:49:52 +0800 | [diff] [blame] | 861 | config EBIU_MBSCTLVAL |
| 862 | hex "EBIU Bank Select Control Register" |
| 863 | depends on BF54x |
| 864 | default 0 |
| 865 | |
| 866 | config EBIU_MODEVAL |
| 867 | hex "Flash Memory Mode Control Register" |
| 868 | depends on BF54x |
| 869 | default 1 |
| 870 | |
| 871 | config EBIU_FCTLVAL |
| 872 | hex "Flash Memory Bank Control Register" |
| 873 | depends on BF54x |
| 874 | default 6 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 875 | endmenu |
| 876 | |
| 877 | ############################################################################# |
| 878 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" |
| 879 | |
| 880 | config PCI |
| 881 | bool "PCI support" |
Adrian Bunk | a95ca3b | 2008-08-27 10:55:05 +0800 | [diff] [blame] | 882 | depends on BROKEN |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 883 | help |
| 884 | Support for PCI bus. |
| 885 | |
| 886 | source "drivers/pci/Kconfig" |
| 887 | |
| 888 | config HOTPLUG |
| 889 | bool "Support for hot-pluggable device" |
| 890 | help |
| 891 | Say Y here if you want to plug devices into your computer while |
| 892 | the system is running, and be able to use them quickly. In many |
| 893 | cases, the devices can likewise be unplugged at any time too. |
| 894 | |
| 895 | One well known example of this is PCMCIA- or PC-cards, credit-card |
| 896 | size devices such as network cards, modems or hard drives which are |
| 897 | plugged into slots found on all modern laptop computers. Another |
| 898 | example, used on modern desktops as well as laptops, is USB. |
| 899 | |
Johannes Berg | a81792f | 2008-07-08 19:00:25 +0200 | [diff] [blame] | 900 | Enable HOTPLUG and build a modular kernel. Get agent software |
| 901 | (from <http://linux-hotplug.sourceforge.net/>) and install it. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 902 | Then your kernel will automatically call out to a user mode "policy |
| 903 | agent" (/sbin/hotplug) to load modules and set up software needed |
| 904 | to use devices as you hotplug them. |
| 905 | |
| 906 | source "drivers/pcmcia/Kconfig" |
| 907 | |
| 908 | source "drivers/pci/hotplug/Kconfig" |
| 909 | |
| 910 | endmenu |
| 911 | |
| 912 | menu "Executable file formats" |
| 913 | |
| 914 | source "fs/Kconfig.binfmt" |
| 915 | |
| 916 | endmenu |
| 917 | |
| 918 | menu "Power management options" |
| 919 | source "kernel/power/Kconfig" |
| 920 | |
Johannes Berg | f4cb570 | 2007-12-08 02:14:00 +0100 | [diff] [blame] | 921 | config ARCH_SUSPEND_POSSIBLE |
| 922 | def_bool y |
| 923 | depends on !SMP |
| 924 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 925 | choice |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 926 | prompt "Standby Power Saving Mode" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 927 | depends on PM |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 928 | default PM_BFIN_SLEEP_DEEPER |
| 929 | config PM_BFIN_SLEEP_DEEPER |
| 930 | bool "Sleep Deeper" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 931 | help |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 932 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic |
| 933 | power dissipation by disabling the clock to the processor core (CCLK). |
| 934 | Furthermore, Standby sets the internal power supply voltage (VDDINT) |
| 935 | to 0.85 V to provide the greatest power savings, while preserving the |
| 936 | processor state. |
| 937 | The PLL and system clock (SCLK) continue to operate at a very low |
| 938 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, |
| 939 | the SDRAM is put into Self Refresh Mode. Typically an external event |
| 940 | such as GPIO interrupt or RTC activity wakes up the processor. |
| 941 | Various Peripherals such as UART, SPORT, PPI may not function as |
| 942 | normal during Sleep Deeper, due to the reduced SCLK frequency. |
| 943 | When in the sleep mode, system DMA access to L1 memory is not supported. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 944 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 945 | If unsure, select "Sleep Deeper". |
| 946 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 947 | config PM_BFIN_SLEEP |
| 948 | bool "Sleep" |
| 949 | help |
| 950 | Sleep Mode (High Power Savings) - The sleep mode reduces power |
| 951 | dissipation by disabling the clock to the processor core (CCLK). |
| 952 | The PLL and system clock (SCLK), however, continue to operate in |
| 953 | this mode. Typically an external event or RTC activity will wake |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 954 | up the processor. When in the sleep mode, system DMA access to L1 |
| 955 | memory is not supported. |
| 956 | |
| 957 | If unsure, select "Sleep Deeper". |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 958 | endchoice |
| 959 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 960 | config PM_WAKEUP_BY_GPIO |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 961 | bool "Allow Wakeup from Standby by GPIO" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 962 | |
| 963 | config PM_WAKEUP_GPIO_NUMBER |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 964 | int "GPIO number" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 965 | range 0 47 |
| 966 | depends on PM_WAKEUP_BY_GPIO |
| 967 | default 2 if BFIN537_STAMP |
| 968 | |
| 969 | choice |
| 970 | prompt "GPIO Polarity" |
| 971 | depends on PM_WAKEUP_BY_GPIO |
| 972 | default PM_WAKEUP_GPIO_POLAR_H |
| 973 | config PM_WAKEUP_GPIO_POLAR_H |
| 974 | bool "Active High" |
| 975 | config PM_WAKEUP_GPIO_POLAR_L |
| 976 | bool "Active Low" |
| 977 | config PM_WAKEUP_GPIO_POLAR_EDGE_F |
| 978 | bool "Falling EDGE" |
| 979 | config PM_WAKEUP_GPIO_POLAR_EDGE_R |
| 980 | bool "Rising EDGE" |
| 981 | config PM_WAKEUP_GPIO_POLAR_EDGE_B |
| 982 | bool "Both EDGE" |
| 983 | endchoice |
| 984 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 985 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
| 986 | depends on PM |
| 987 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 988 | config PM_BFIN_WAKE_PH6 |
| 989 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" |
| 990 | depends on PM && (BF52x || BF534 || BF536 || BF537) |
| 991 | default n |
| 992 | help |
| 993 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) |
| 994 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 995 | config PM_BFIN_WAKE_GP |
| 996 | bool "Allow Wake-Up from GPIOs" |
| 997 | depends on PM && BF54x |
| 998 | default n |
| 999 | help |
| 1000 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1001 | endmenu |
| 1002 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1003 | menu "CPU Frequency scaling" |
| 1004 | |
| 1005 | source "drivers/cpufreq/Kconfig" |
| 1006 | |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1007 | config CPU_VOLTAGE |
| 1008 | bool "CPU Voltage scaling" |
| 1009 | depends on EXPERIMENTAL |
| 1010 | depends on CPU_FREQ |
| 1011 | default n |
| 1012 | help |
| 1013 | Say Y here if you want CPU voltage scaling according to the CPU frequency. |
| 1014 | This option violates the PLL BYPASS recommendation in the Blackfin Processor |
| 1015 | manuals. There is a theoretical risk that during VDDINT transitions |
| 1016 | the PLL may unlock. |
| 1017 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1018 | endmenu |
| 1019 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1020 | source "net/Kconfig" |
| 1021 | |
| 1022 | source "drivers/Kconfig" |
| 1023 | |
| 1024 | source "fs/Kconfig" |
| 1025 | |
Mike Frysinger | 74ce832 | 2007-11-21 23:50:49 +0800 | [diff] [blame] | 1026 | source "arch/blackfin/Kconfig.debug" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1027 | |
| 1028 | source "security/Kconfig" |
| 1029 | |
| 1030 | source "crypto/Kconfig" |
| 1031 | |
| 1032 | source "lib/Kconfig" |