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Jongpill Lee7d44d2b2012-02-17 09:51:31 +09001/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
Changhwan Yound6d8b482010-12-03 17:15:40 +09003 * http://www.samsung.com
4 *
Jongpill Lee7d44d2b2012-02-17 09:51:31 +09005 * EXYNOS - Power management unit definition
Changhwan Yound6d8b482010-12-03 17:15:40 +09006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_REGS_PMU_H
13#define __ASM_ARCH_REGS_PMU_H __FILE__
14
15#include <mach/map.h>
16
Jaecheol Leeb77ca652011-03-10 13:21:51 +090017#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
Abhilash Kesavan7000fe82012-11-20 18:20:38 +090018#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
Changhwan Yound6d8b482010-12-03 17:15:40 +090019
Jaecheol Leeb77ca652011-03-10 13:21:51 +090020#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
Sylwester Nawrocki1d45ac42011-03-10 21:53:40 +090021
Jaecheol Leeb77ca652011-03-10 13:21:51 +090022#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
Changhwan Yound6d8b482010-12-03 17:15:40 +090023
Jaecheol Leeb77ca652011-03-10 13:21:51 +090024#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
25
26#define S5P_USE_STANDBY_WFI0 (1 << 16)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090027#define S5P_USE_STANDBY_WFE0 (1 << 24)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090028
Kukjin Kim94c7ca72012-02-11 22:15:45 +090029#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
Kukjin Kim2edb36c2012-11-15 15:48:56 +090030#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
Kyungmin Parkd2edddf2011-08-19 20:25:05 +090031
Jaecheol Leeb77ca652011-03-10 13:21:51 +090032#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
Tomasz Figad710aa32014-03-18 07:28:27 +090033#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
34#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090035
36#define S5P_INFORM0 S5P_PMUREG(0x0800)
37#define S5P_INFORM1 S5P_PMUREG(0x0804)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090038#define S5P_INFORM5 S5P_PMUREG(0x0814)
39#define S5P_INFORM6 S5P_PMUREG(0x0818)
40#define S5P_INFORM7 S5P_PMUREG(0x081C)
41
42#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
43#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
44#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
45#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
46#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
47#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
48#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
49#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
50#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
51#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
52#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
53#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
54#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
55#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
56#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
57#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
58#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
59#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
60#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
61#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
62#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
63#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
64#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090065#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
66#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
67#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
68#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
69#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
70#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
71#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090072#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
73#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
74#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
75#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
76#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
77#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
78#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090079#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
80#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
81#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
82#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
83#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
Jaecheol Leeb77ca652011-03-10 13:21:51 +090084#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
85#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
86#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
87#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
88#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
89#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
90#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
91#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
92#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
93#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
94#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
95#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
96#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
97#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
98#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
99#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
100#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
101#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
102#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
103#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
Jaecheol Leeb77ca652011-03-10 13:21:51 +0900104#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
105#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
106#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
107
Jaecheol Leeb77ca652011-03-10 13:21:51 +0900108#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
109#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
Jaecheol Leeb77ca652011-03-10 13:21:51 +0900110
111#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
112#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
113#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
114#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
115#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
116#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
117#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
118
JungHi Min911c29b2011-07-16 13:39:09 +0900119#define S5P_CORE_LOCAL_PWR_EN 0x3
Jaecheol Leeb77ca652011-03-10 13:21:51 +0900120#define S5P_INT_LOCAL_PWR_EN 0x7
121
122#define S5P_CHECK_SLEEP 0x00000BAD
Changhwan Yound6d8b482010-12-03 17:15:40 +0900123
Jongpill Lee9a942962011-09-27 07:24:58 +0900124/* Only for EXYNOS4210 */
Jongpill Lee9a942962011-09-27 07:24:58 +0900125#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
126#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
127#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
128#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
129#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
130#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
131
Inderpal Singh5ddfa842012-05-15 00:20:09 +0900132/* Only for EXYNOS4x12 */
Jongpill Lee9a942962011-09-27 07:24:58 +0900133#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
134#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
135#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
136#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
137#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
138#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
139#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
140#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
141#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
142#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
143#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
144#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
145#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
146#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
147#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
148#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
149#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
150#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
151#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
152#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
153#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
154#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
155#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
156#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
157#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
158#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
159#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
160#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
161
162#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
163#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
164#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
165#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
166#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
167#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
168#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
169#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
170#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
171#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
172
Inderpal Singh5ddfa842012-05-15 00:20:09 +0900173/* Only for EXYNOS4412 */
174#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
175#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
176#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
177#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
178#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
179#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
180
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900181/* For EXYNOS5 */
182
Abhilash Kesavan7000fe82012-11-20 18:20:38 +0900183#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900184
Jonghwan Choi7d896aa2012-06-27 09:47:35 +0900185#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
186#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
187
188#define EXYNOS5_SYS_WDTRESET (1 << 20)
189
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900190#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
191#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
192#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
193#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
194#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
195#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
196#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
197#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
198#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
199#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
200#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
201#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
202#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
203#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
204#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
205#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
206#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
207#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
208#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
209#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
210#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
211#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
212#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
213#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
214#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
215#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
216#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
217#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
218#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
219#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
220#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
221#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
222#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
223#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
224#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
225#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
226#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
227#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
228#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
229#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
230#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
231#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
232#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
233#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
234#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
235#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
236#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
237#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
238#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
239#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
240#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
241#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
242#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
243#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
244#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
245#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
246#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
247#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
248#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
249#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
250#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
251#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
252#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
253#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
254#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
255#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
256#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
257#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
258#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
259#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
260#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
261#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
262#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
263#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
264#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
265#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
266#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
267#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
268#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
269#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
270#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
271#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
272#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
273#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
274#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
275#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
276#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
277#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
278#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
279#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
280#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
281#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
282#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
283#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
284#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
285#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
286#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
287#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
288#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
289
290#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
291#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
292#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
293#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
294#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
Inderpal Singh088584612013-04-29 17:01:47 +0530295#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900296#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
297#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
298#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900299#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
300#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
301#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900302#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
303#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
304#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
305
306#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
307#define EXYNOS5_USE_SC_COUNTER (1 << 0)
308
Jongpill Lee7d44d2b2012-02-17 09:51:31 +0900309#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
310
311#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
312#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
313
314#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
315
Changhwan Yound6d8b482010-12-03 17:15:40 +0900316#endif /* __ASM_ARCH_REGS_PMU_H */