Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License as published by |
| 4 | * the Free Software Foundation; either version 2 of the License, or |
| 5 | * (at your option) any later version. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 16 | #include <dt-bindings/pinctrl/rockchip.h> |
| 17 | #include <dt-bindings/clock/rk3288-cru.h> |
| 18 | #include "skeleton.dtsi" |
| 19 | |
| 20 | / { |
| 21 | compatible = "rockchip,rk3288"; |
| 22 | |
| 23 | interrupt-parent = <&gic>; |
| 24 | |
| 25 | aliases { |
| 26 | i2c0 = &i2c0; |
| 27 | i2c1 = &i2c1; |
| 28 | i2c2 = &i2c2; |
| 29 | i2c3 = &i2c3; |
| 30 | i2c4 = &i2c4; |
| 31 | i2c5 = &i2c5; |
| 32 | serial0 = &uart0; |
| 33 | serial1 = &uart1; |
| 34 | serial2 = &uart2; |
| 35 | serial3 = &uart3; |
| 36 | serial4 = &uart4; |
| 37 | }; |
| 38 | |
| 39 | cpus { |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <0>; |
| 42 | |
| 43 | cpu@500 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a12"; |
| 46 | reg = <0x500>; |
| 47 | }; |
| 48 | cpu@501 { |
| 49 | device_type = "cpu"; |
| 50 | compatible = "arm,cortex-a12"; |
| 51 | reg = <0x501>; |
| 52 | }; |
| 53 | cpu@502 { |
| 54 | device_type = "cpu"; |
| 55 | compatible = "arm,cortex-a12"; |
| 56 | reg = <0x502>; |
| 57 | }; |
| 58 | cpu@503 { |
| 59 | device_type = "cpu"; |
| 60 | compatible = "arm,cortex-a12"; |
| 61 | reg = <0x503>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | xin24m: oscillator { |
| 66 | compatible = "fixed-clock"; |
| 67 | clock-frequency = <24000000>; |
| 68 | clock-output-names = "xin24m"; |
| 69 | #clock-cells = <0>; |
| 70 | }; |
| 71 | |
| 72 | timer { |
| 73 | compatible = "arm,armv7-timer"; |
| 74 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| 75 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| 76 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| 77 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 78 | clock-frequency = <24000000>; |
| 79 | }; |
| 80 | |
Doug Anderson | 85095bf | 2014-08-12 16:21:13 -0700 | [diff] [blame] | 81 | sdmmc: dwmmc@ff0c0000 { |
| 82 | compatible = "rockchip,rk3288-dw-mshc"; |
| 83 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
| 84 | clock-names = "biu", "ciu"; |
| 85 | fifo-depth = <0x100>; |
| 86 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 87 | reg = <0xff0c0000 0x4000>; |
| 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
Addy Ke | f1a0723 | 2014-08-19 18:21:08 +0800 | [diff] [blame^] | 91 | sdio0: dwmmc@ff0d0000 { |
| 92 | compatible = "rockchip,rk3288-dw-mshc"; |
| 93 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; |
| 94 | clock-names = "biu", "ciu"; |
| 95 | fifo-depth = <0x100>; |
| 96 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 97 | reg = <0xff0d0000 0x4000>; |
| 98 | status = "disabled"; |
| 99 | }; |
| 100 | |
| 101 | sdio1: dwmmc@ff0e0000 { |
| 102 | compatible = "rockchip,rk3288-dw-mshc"; |
| 103 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; |
| 104 | clock-names = "biu", "ciu"; |
| 105 | fifo-depth = <0x100>; |
| 106 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 107 | reg = <0xff0e0000 0x4000>; |
| 108 | status = "disabled"; |
| 109 | }; |
| 110 | |
Doug Anderson | 85095bf | 2014-08-12 16:21:13 -0700 | [diff] [blame] | 111 | emmc: dwmmc@ff0f0000 { |
| 112 | compatible = "rockchip,rk3288-dw-mshc"; |
| 113 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; |
| 114 | clock-names = "biu", "ciu"; |
| 115 | fifo-depth = <0x100>; |
| 116 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 117 | reg = <0xff0f0000 0x4000>; |
| 118 | status = "disabled"; |
| 119 | }; |
| 120 | |
Heiko Stübner | f23a617 | 2014-08-20 21:09:24 +0200 | [diff] [blame] | 121 | saradc: saradc@ff100000 { |
| 122 | compatible = "rockchip,saradc"; |
| 123 | reg = <0xff100000 0x100>; |
| 124 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 125 | #io-channel-cells = <1>; |
| 126 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; |
| 127 | clock-names = "saradc", "apb_pclk"; |
| 128 | status = "disabled"; |
| 129 | }; |
| 130 | |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 131 | i2c1: i2c@ff140000 { |
| 132 | compatible = "rockchip,rk3288-i2c"; |
| 133 | reg = <0xff140000 0x1000>; |
| 134 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; |
| 137 | clock-names = "i2c"; |
| 138 | clocks = <&cru PCLK_I2C1>; |
| 139 | pinctrl-names = "default"; |
| 140 | pinctrl-0 = <&i2c1_xfer>; |
| 141 | status = "disabled"; |
| 142 | }; |
| 143 | |
| 144 | i2c3: i2c@ff150000 { |
| 145 | compatible = "rockchip,rk3288-i2c"; |
| 146 | reg = <0xff150000 0x1000>; |
| 147 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 148 | #address-cells = <1>; |
| 149 | #size-cells = <0>; |
| 150 | clock-names = "i2c"; |
| 151 | clocks = <&cru PCLK_I2C3>; |
| 152 | pinctrl-names = "default"; |
| 153 | pinctrl-0 = <&i2c3_xfer>; |
| 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
| 157 | i2c4: i2c@ff160000 { |
| 158 | compatible = "rockchip,rk3288-i2c"; |
| 159 | reg = <0xff160000 0x1000>; |
| 160 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| 161 | #address-cells = <1>; |
| 162 | #size-cells = <0>; |
| 163 | clock-names = "i2c"; |
| 164 | clocks = <&cru PCLK_I2C4>; |
| 165 | pinctrl-names = "default"; |
| 166 | pinctrl-0 = <&i2c4_xfer>; |
| 167 | status = "disabled"; |
| 168 | }; |
| 169 | |
| 170 | i2c5: i2c@ff170000 { |
| 171 | compatible = "rockchip,rk3288-i2c"; |
| 172 | reg = <0xff170000 0x1000>; |
| 173 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 174 | #address-cells = <1>; |
| 175 | #size-cells = <0>; |
| 176 | clock-names = "i2c"; |
| 177 | clocks = <&cru PCLK_I2C5>; |
| 178 | pinctrl-names = "default"; |
| 179 | pinctrl-0 = <&i2c5_xfer>; |
| 180 | status = "disabled"; |
| 181 | }; |
| 182 | |
| 183 | uart0: serial@ff180000 { |
| 184 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; |
| 185 | reg = <0xff180000 0x100>; |
| 186 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 187 | reg-shift = <2>; |
| 188 | reg-io-width = <4>; |
| 189 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; |
| 190 | clock-names = "baudclk", "apb_pclk"; |
| 191 | pinctrl-names = "default"; |
| 192 | pinctrl-0 = <&uart0_xfer>; |
| 193 | status = "disabled"; |
| 194 | }; |
| 195 | |
| 196 | uart1: serial@ff190000 { |
| 197 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; |
| 198 | reg = <0xff190000 0x100>; |
| 199 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 200 | reg-shift = <2>; |
| 201 | reg-io-width = <4>; |
| 202 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
| 203 | clock-names = "baudclk", "apb_pclk"; |
| 204 | pinctrl-names = "default"; |
| 205 | pinctrl-0 = <&uart1_xfer>; |
| 206 | status = "disabled"; |
| 207 | }; |
| 208 | |
| 209 | uart2: serial@ff690000 { |
| 210 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; |
| 211 | reg = <0xff690000 0x100>; |
| 212 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 213 | reg-shift = <2>; |
| 214 | reg-io-width = <4>; |
| 215 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; |
| 216 | clock-names = "baudclk", "apb_pclk"; |
| 217 | pinctrl-names = "default"; |
| 218 | pinctrl-0 = <&uart2_xfer>; |
| 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
| 222 | uart3: serial@ff1b0000 { |
| 223 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; |
| 224 | reg = <0xff1b0000 0x100>; |
| 225 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | reg-shift = <2>; |
| 227 | reg-io-width = <4>; |
| 228 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; |
| 229 | clock-names = "baudclk", "apb_pclk"; |
| 230 | pinctrl-names = "default"; |
| 231 | pinctrl-0 = <&uart3_xfer>; |
| 232 | status = "disabled"; |
| 233 | }; |
| 234 | |
| 235 | uart4: serial@ff1c0000 { |
| 236 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; |
| 237 | reg = <0xff1c0000 0x100>; |
| 238 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 239 | reg-shift = <2>; |
| 240 | reg-io-width = <4>; |
| 241 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; |
| 242 | clock-names = "baudclk", "apb_pclk"; |
| 243 | pinctrl-names = "default"; |
| 244 | pinctrl-0 = <&uart4_xfer>; |
| 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
Doug Anderson | c9c32c5 | 2014-08-07 17:44:19 +0200 | [diff] [blame] | 248 | usb_host0_ehci: usb@ff500000 { |
| 249 | compatible = "generic-ehci"; |
| 250 | reg = <0xff500000 0x100>; |
| 251 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | clocks = <&cru HCLK_USBHOST0>; |
| 253 | clock-names = "usbhost"; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
| 257 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ |
| 258 | |
| 259 | usb_hsic: usb@ff5c0000 { |
| 260 | compatible = "generic-ehci"; |
| 261 | reg = <0xff5c0000 0x100>; |
| 262 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 263 | clocks = <&cru HCLK_HSIC>; |
| 264 | clock-names = "usbhost"; |
| 265 | status = "disabled"; |
| 266 | }; |
| 267 | |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 268 | i2c0: i2c@ff650000 { |
| 269 | compatible = "rockchip,rk3288-i2c"; |
| 270 | reg = <0xff650000 0x1000>; |
| 271 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
| 274 | clock-names = "i2c"; |
| 275 | clocks = <&cru PCLK_I2C0>; |
| 276 | pinctrl-names = "default"; |
| 277 | pinctrl-0 = <&i2c0_xfer>; |
| 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | i2c2: i2c@ff660000 { |
| 282 | compatible = "rockchip,rk3288-i2c"; |
| 283 | reg = <0xff660000 0x1000>; |
| 284 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 285 | #address-cells = <1>; |
| 286 | #size-cells = <0>; |
| 287 | clock-names = "i2c"; |
| 288 | clocks = <&cru PCLK_I2C2>; |
| 289 | pinctrl-names = "default"; |
| 290 | pinctrl-0 = <&i2c2_xfer>; |
| 291 | status = "disabled"; |
| 292 | }; |
| 293 | |
Doug Anderson | df542df | 2014-08-25 15:59:26 -0700 | [diff] [blame] | 294 | pwm0: pwm@ff680000 { |
| 295 | compatible = "rockchip,rk3288-pwm"; |
| 296 | reg = <0xff680000 0x10>; |
| 297 | #pwm-cells = <3>; |
| 298 | pinctrl-names = "default"; |
| 299 | pinctrl-0 = <&pwm0_pin>; |
| 300 | clocks = <&cru PCLK_PWM>; |
| 301 | clock-names = "pwm"; |
| 302 | status = "disabled"; |
| 303 | }; |
| 304 | |
| 305 | pwm1: pwm@ff680010 { |
| 306 | compatible = "rockchip,rk3288-pwm"; |
| 307 | reg = <0xff680010 0x10>; |
| 308 | #pwm-cells = <3>; |
| 309 | pinctrl-names = "default"; |
| 310 | pinctrl-0 = <&pwm1_pin>; |
| 311 | clocks = <&cru PCLK_PWM>; |
| 312 | clock-names = "pwm"; |
| 313 | status = "disabled"; |
| 314 | }; |
| 315 | |
| 316 | pwm2: pwm@ff680020 { |
| 317 | compatible = "rockchip,rk3288-pwm"; |
| 318 | reg = <0xff680020 0x10>; |
| 319 | #pwm-cells = <3>; |
| 320 | pinctrl-names = "default"; |
| 321 | pinctrl-0 = <&pwm2_pin>; |
| 322 | clocks = <&cru PCLK_PWM>; |
| 323 | clock-names = "pwm"; |
| 324 | status = "disabled"; |
| 325 | }; |
| 326 | |
| 327 | pwm3: pwm@ff680030 { |
| 328 | compatible = "rockchip,rk3288-pwm"; |
| 329 | reg = <0xff680030 0x10>; |
| 330 | #pwm-cells = <2>; |
| 331 | pinctrl-names = "default"; |
| 332 | pinctrl-0 = <&pwm3_pin>; |
| 333 | clocks = <&cru PCLK_PWM>; |
| 334 | clock-names = "pwm"; |
| 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 338 | pmu: power-management@ff730000 { |
| 339 | compatible = "rockchip,rk3288-pmu", "syscon"; |
| 340 | reg = <0xff730000 0x100>; |
| 341 | }; |
| 342 | |
| 343 | sgrf: syscon@ff740000 { |
| 344 | compatible = "rockchip,rk3288-sgrf", "syscon"; |
| 345 | reg = <0xff740000 0x1000>; |
| 346 | }; |
| 347 | |
| 348 | cru: clock-controller@ff760000 { |
| 349 | compatible = "rockchip,rk3288-cru"; |
| 350 | reg = <0xff760000 0x1000>; |
| 351 | rockchip,grf = <&grf>; |
| 352 | #clock-cells = <1>; |
| 353 | #reset-cells = <1>; |
| 354 | }; |
| 355 | |
| 356 | grf: syscon@ff770000 { |
| 357 | compatible = "rockchip,rk3288-grf", "syscon"; |
| 358 | reg = <0xff770000 0x1000>; |
| 359 | }; |
| 360 | |
| 361 | wdt: watchdog@ff800000 { |
| 362 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; |
| 363 | reg = <0xff800000 0x100>; |
| 364 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 365 | status = "disabled"; |
| 366 | }; |
| 367 | |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 368 | gic: interrupt-controller@ffc01000 { |
| 369 | compatible = "arm,gic-400"; |
| 370 | interrupt-controller; |
| 371 | #interrupt-cells = <3>; |
| 372 | #address-cells = <0>; |
| 373 | |
| 374 | reg = <0xffc01000 0x1000>, |
| 375 | <0xffc02000 0x1000>, |
| 376 | <0xffc04000 0x2000>, |
| 377 | <0xffc06000 0x2000>; |
| 378 | interrupts = <GIC_PPI 9 0xf04>; |
| 379 | }; |
| 380 | |
| 381 | pinctrl: pinctrl { |
| 382 | compatible = "rockchip,rk3288-pinctrl"; |
| 383 | rockchip,grf = <&grf>; |
| 384 | rockchip,pmu = <&pmu>; |
| 385 | #address-cells = <1>; |
| 386 | #size-cells = <1>; |
| 387 | ranges; |
| 388 | |
| 389 | gpio0: gpio0@ff750000 { |
| 390 | compatible = "rockchip,gpio-bank"; |
| 391 | reg = <0xff750000 0x100>; |
| 392 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 393 | clocks = <&cru PCLK_GPIO0>; |
| 394 | |
| 395 | gpio-controller; |
| 396 | #gpio-cells = <2>; |
| 397 | |
| 398 | interrupt-controller; |
| 399 | #interrupt-cells = <2>; |
| 400 | }; |
| 401 | |
| 402 | gpio1: gpio1@ff780000 { |
| 403 | compatible = "rockchip,gpio-bank"; |
| 404 | reg = <0xff780000 0x100>; |
| 405 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 406 | clocks = <&cru PCLK_GPIO1>; |
| 407 | |
| 408 | gpio-controller; |
| 409 | #gpio-cells = <2>; |
| 410 | |
| 411 | interrupt-controller; |
| 412 | #interrupt-cells = <2>; |
| 413 | }; |
| 414 | |
| 415 | gpio2: gpio2@ff790000 { |
| 416 | compatible = "rockchip,gpio-bank"; |
| 417 | reg = <0xff790000 0x100>; |
| 418 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 419 | clocks = <&cru PCLK_GPIO2>; |
| 420 | |
| 421 | gpio-controller; |
| 422 | #gpio-cells = <2>; |
| 423 | |
| 424 | interrupt-controller; |
| 425 | #interrupt-cells = <2>; |
| 426 | }; |
| 427 | |
| 428 | gpio3: gpio3@ff7a0000 { |
| 429 | compatible = "rockchip,gpio-bank"; |
| 430 | reg = <0xff7a0000 0x100>; |
| 431 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 432 | clocks = <&cru PCLK_GPIO3>; |
| 433 | |
| 434 | gpio-controller; |
| 435 | #gpio-cells = <2>; |
| 436 | |
| 437 | interrupt-controller; |
| 438 | #interrupt-cells = <2>; |
| 439 | }; |
| 440 | |
| 441 | gpio4: gpio4@ff7b0000 { |
| 442 | compatible = "rockchip,gpio-bank"; |
| 443 | reg = <0xff7b0000 0x100>; |
| 444 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 445 | clocks = <&cru PCLK_GPIO4>; |
| 446 | |
| 447 | gpio-controller; |
| 448 | #gpio-cells = <2>; |
| 449 | |
| 450 | interrupt-controller; |
| 451 | #interrupt-cells = <2>; |
| 452 | }; |
| 453 | |
| 454 | gpio5: gpio5@ff7c0000 { |
| 455 | compatible = "rockchip,gpio-bank"; |
| 456 | reg = <0xff7c0000 0x100>; |
| 457 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 458 | clocks = <&cru PCLK_GPIO5>; |
| 459 | |
| 460 | gpio-controller; |
| 461 | #gpio-cells = <2>; |
| 462 | |
| 463 | interrupt-controller; |
| 464 | #interrupt-cells = <2>; |
| 465 | }; |
| 466 | |
| 467 | gpio6: gpio6@ff7d0000 { |
| 468 | compatible = "rockchip,gpio-bank"; |
| 469 | reg = <0xff7d0000 0x100>; |
| 470 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| 471 | clocks = <&cru PCLK_GPIO6>; |
| 472 | |
| 473 | gpio-controller; |
| 474 | #gpio-cells = <2>; |
| 475 | |
| 476 | interrupt-controller; |
| 477 | #interrupt-cells = <2>; |
| 478 | }; |
| 479 | |
| 480 | gpio7: gpio7@ff7e0000 { |
| 481 | compatible = "rockchip,gpio-bank"; |
| 482 | reg = <0xff7e0000 0x100>; |
| 483 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 484 | clocks = <&cru PCLK_GPIO7>; |
| 485 | |
| 486 | gpio-controller; |
| 487 | #gpio-cells = <2>; |
| 488 | |
| 489 | interrupt-controller; |
| 490 | #interrupt-cells = <2>; |
| 491 | }; |
| 492 | |
| 493 | gpio8: gpio8@ff7f0000 { |
| 494 | compatible = "rockchip,gpio-bank"; |
| 495 | reg = <0xff7f0000 0x100>; |
| 496 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 497 | clocks = <&cru PCLK_GPIO8>; |
| 498 | |
| 499 | gpio-controller; |
| 500 | #gpio-cells = <2>; |
| 501 | |
| 502 | interrupt-controller; |
| 503 | #interrupt-cells = <2>; |
| 504 | }; |
| 505 | |
| 506 | pcfg_pull_up: pcfg-pull-up { |
| 507 | bias-pull-up; |
| 508 | }; |
| 509 | |
| 510 | pcfg_pull_down: pcfg-pull-down { |
| 511 | bias-pull-down; |
| 512 | }; |
| 513 | |
| 514 | pcfg_pull_none: pcfg-pull-none { |
| 515 | bias-disable; |
| 516 | }; |
| 517 | |
| 518 | i2c0 { |
| 519 | i2c0_xfer: i2c0-xfer { |
| 520 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, |
| 521 | <0 16 RK_FUNC_1 &pcfg_pull_none>; |
| 522 | }; |
| 523 | }; |
| 524 | |
| 525 | i2c1 { |
| 526 | i2c1_xfer: i2c1-xfer { |
| 527 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, |
| 528 | <8 5 RK_FUNC_1 &pcfg_pull_none>; |
| 529 | }; |
| 530 | }; |
| 531 | |
| 532 | i2c2 { |
| 533 | i2c2_xfer: i2c2-xfer { |
| 534 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, |
| 535 | <6 10 RK_FUNC_1 &pcfg_pull_none>; |
| 536 | }; |
| 537 | }; |
| 538 | |
| 539 | i2c3 { |
| 540 | i2c3_xfer: i2c3-xfer { |
| 541 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, |
| 542 | <2 17 RK_FUNC_1 &pcfg_pull_none>; |
| 543 | }; |
| 544 | }; |
| 545 | |
| 546 | i2c4 { |
| 547 | i2c4_xfer: i2c4-xfer { |
| 548 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, |
| 549 | <7 18 RK_FUNC_1 &pcfg_pull_none>; |
| 550 | }; |
| 551 | }; |
| 552 | |
| 553 | i2c5 { |
| 554 | i2c5_xfer: i2c5-xfer { |
| 555 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, |
| 556 | <7 20 RK_FUNC_1 &pcfg_pull_none>; |
| 557 | }; |
| 558 | }; |
| 559 | |
| 560 | sdmmc { |
| 561 | sdmmc_clk: sdmmc-clk { |
| 562 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; |
| 563 | }; |
| 564 | |
| 565 | sdmmc_cmd: sdmmc-cmd { |
| 566 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; |
| 567 | }; |
| 568 | |
| 569 | sdmmc_cd: sdmcc-cd { |
| 570 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; |
| 571 | }; |
| 572 | |
| 573 | sdmmc_bus1: sdmmc-bus1 { |
| 574 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; |
| 575 | }; |
| 576 | |
| 577 | sdmmc_bus4: sdmmc-bus4 { |
| 578 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, |
| 579 | <6 17 RK_FUNC_1 &pcfg_pull_up>, |
| 580 | <6 18 RK_FUNC_1 &pcfg_pull_up>, |
| 581 | <6 19 RK_FUNC_1 &pcfg_pull_up>; |
| 582 | }; |
| 583 | }; |
| 584 | |
Addy Ke | f1a0723 | 2014-08-19 18:21:08 +0800 | [diff] [blame^] | 585 | sdio0 { |
| 586 | sdio0_bus1: sdio0-bus1 { |
| 587 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; |
| 588 | }; |
| 589 | |
| 590 | sdio0_bus4: sdio0-bus4 { |
| 591 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, |
| 592 | <4 21 RK_FUNC_1 &pcfg_pull_up>, |
| 593 | <4 22 RK_FUNC_1 &pcfg_pull_up>, |
| 594 | <4 23 RK_FUNC_1 &pcfg_pull_up>; |
| 595 | }; |
| 596 | |
| 597 | sdio0_cmd: sdio0-cmd { |
| 598 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; |
| 599 | }; |
| 600 | |
| 601 | sdio0_clk: sdio0-clk { |
| 602 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; |
| 603 | }; |
| 604 | |
| 605 | sdio0_cd: sdio0-cd { |
| 606 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; |
| 607 | }; |
| 608 | |
| 609 | sdio0_wp: sdio0-wp { |
| 610 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; |
| 611 | }; |
| 612 | |
| 613 | sdio0_pwr: sdio0-pwr { |
| 614 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; |
| 615 | }; |
| 616 | |
| 617 | sdio0_bkpwr: sdio0-bkpwr { |
| 618 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; |
| 619 | }; |
| 620 | |
| 621 | sdio0_int: sdio0-int { |
| 622 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; |
| 623 | }; |
| 624 | }; |
| 625 | |
| 626 | sdio1 { |
| 627 | sdio1_bus1: sdio1-bus1 { |
| 628 | rockchip,pins = <3 24 4 &pcfg_pull_up>; |
| 629 | }; |
| 630 | |
| 631 | sdio1_bus4: sdio1-bus4 { |
| 632 | rockchip,pins = <3 24 4 &pcfg_pull_up>, |
| 633 | <3 25 4 &pcfg_pull_up>, |
| 634 | <3 26 4 &pcfg_pull_up>, |
| 635 | <3 27 4 &pcfg_pull_up>; |
| 636 | }; |
| 637 | |
| 638 | sdio1_cd: sdio1-cd { |
| 639 | rockchip,pins = <3 28 4 &pcfg_pull_up>; |
| 640 | }; |
| 641 | |
| 642 | sdio1_wp: sdio1-wp { |
| 643 | rockchip,pins = <3 29 4 &pcfg_pull_up>; |
| 644 | }; |
| 645 | |
| 646 | sdio1_bkpwr: sdio1-bkpwr { |
| 647 | rockchip,pins = <3 30 4 &pcfg_pull_up>; |
| 648 | }; |
| 649 | |
| 650 | sdio1_int: sdio1-int { |
| 651 | rockchip,pins = <3 31 4 &pcfg_pull_up>; |
| 652 | }; |
| 653 | |
| 654 | sdio1_cmd: sdio1-cmd { |
| 655 | rockchip,pins = <4 6 4 &pcfg_pull_up>; |
| 656 | }; |
| 657 | |
| 658 | sdio1_clk: sdio1-clk { |
| 659 | rockchip,pins = <4 7 4 &pcfg_pull_none>; |
| 660 | }; |
| 661 | |
| 662 | sdio1_pwr: sdio1-pwr { |
| 663 | rockchip,pins = <4 9 4 &pcfg_pull_up>; |
| 664 | }; |
| 665 | }; |
| 666 | |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 667 | emmc { |
| 668 | emmc_clk: emmc-clk { |
| 669 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; |
| 670 | }; |
| 671 | |
| 672 | emmc_cmd: emmc-cmd { |
| 673 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; |
| 674 | }; |
| 675 | |
| 676 | emmc_pwr: emmc-pwr { |
| 677 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; |
| 678 | }; |
| 679 | |
| 680 | emmc_bus1: emmc-bus1 { |
| 681 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; |
| 682 | }; |
| 683 | |
| 684 | emmc_bus4: emmc-bus4 { |
| 685 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, |
| 686 | <3 1 RK_FUNC_2 &pcfg_pull_up>, |
| 687 | <3 2 RK_FUNC_2 &pcfg_pull_up>, |
| 688 | <3 3 RK_FUNC_2 &pcfg_pull_up>; |
| 689 | }; |
| 690 | |
| 691 | emmc_bus8: emmc-bus8 { |
| 692 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, |
| 693 | <3 1 RK_FUNC_2 &pcfg_pull_up>, |
| 694 | <3 2 RK_FUNC_2 &pcfg_pull_up>, |
| 695 | <3 3 RK_FUNC_2 &pcfg_pull_up>, |
| 696 | <3 4 RK_FUNC_2 &pcfg_pull_up>, |
| 697 | <3 5 RK_FUNC_2 &pcfg_pull_up>, |
| 698 | <3 6 RK_FUNC_2 &pcfg_pull_up>, |
| 699 | <3 7 RK_FUNC_2 &pcfg_pull_up>; |
| 700 | }; |
| 701 | }; |
| 702 | |
| 703 | uart0 { |
| 704 | uart0_xfer: uart0-xfer { |
| 705 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, |
| 706 | <4 17 RK_FUNC_1 &pcfg_pull_none>; |
| 707 | }; |
| 708 | |
| 709 | uart0_cts: uart0-cts { |
| 710 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; |
| 711 | }; |
| 712 | |
| 713 | uart0_rts: uart0-rts { |
| 714 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; |
| 715 | }; |
| 716 | }; |
| 717 | |
| 718 | uart1 { |
| 719 | uart1_xfer: uart1-xfer { |
| 720 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, |
| 721 | <5 9 RK_FUNC_1 &pcfg_pull_none>; |
| 722 | }; |
| 723 | |
| 724 | uart1_cts: uart1-cts { |
| 725 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; |
| 726 | }; |
| 727 | |
| 728 | uart1_rts: uart1-rts { |
| 729 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; |
| 730 | }; |
| 731 | }; |
| 732 | |
| 733 | uart2 { |
| 734 | uart2_xfer: uart2-xfer { |
| 735 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, |
| 736 | <7 23 RK_FUNC_1 &pcfg_pull_none>; |
| 737 | }; |
| 738 | /* no rts / cts for uart2 */ |
| 739 | }; |
| 740 | |
| 741 | uart3 { |
| 742 | uart3_xfer: uart3-xfer { |
| 743 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, |
| 744 | <7 8 RK_FUNC_1 &pcfg_pull_none>; |
| 745 | }; |
| 746 | |
| 747 | uart3_cts: uart3-cts { |
| 748 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; |
| 749 | }; |
| 750 | |
| 751 | uart3_rts: uart3-rts { |
| 752 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; |
| 753 | }; |
| 754 | }; |
| 755 | |
| 756 | uart4 { |
| 757 | uart4_xfer: uart4-xfer { |
| 758 | rockchip,pins = <5 12 3 &pcfg_pull_up>, |
| 759 | <5 13 3 &pcfg_pull_none>; |
| 760 | }; |
| 761 | |
| 762 | uart4_cts: uart4-cts { |
| 763 | rockchip,pins = <5 14 3 &pcfg_pull_none>; |
| 764 | }; |
| 765 | |
| 766 | uart4_rts: uart4-rts { |
| 767 | rockchip,pins = <5 15 3 &pcfg_pull_none>; |
| 768 | }; |
| 769 | }; |
Doug Anderson | df542df | 2014-08-25 15:59:26 -0700 | [diff] [blame] | 770 | |
| 771 | pwm0 { |
| 772 | pwm0_pin: pwm0-pin { |
| 773 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; |
| 774 | }; |
| 775 | }; |
| 776 | |
| 777 | pwm1 { |
| 778 | pwm1_pin: pwm1-pin { |
| 779 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; |
| 780 | }; |
| 781 | }; |
| 782 | |
| 783 | pwm2 { |
| 784 | pwm2_pin: pwm2-pin { |
| 785 | rockchip,pins = <7 22 3 &pcfg_pull_none>; |
| 786 | }; |
| 787 | }; |
| 788 | |
| 789 | pwm3 { |
| 790 | pwm3_pin: pwm3-pin { |
| 791 | rockchip,pins = <7 23 3 &pcfg_pull_none>; |
| 792 | }; |
| 793 | }; |
Heiko Stuebner | 2ab557b | 2014-07-15 20:16:19 +0200 | [diff] [blame] | 794 | }; |
| 795 | }; |