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Ian Munsief204e0b2014-10-08 19:55:02 +11001/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _CXL_H_
11#define _CXL_H_
12
13#include <linux/interrupt.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/types.h>
17#include <linux/cdev.h>
18#include <linux/pid.h>
19#include <linux/io.h>
20#include <linux/pci.h>
Michael Neuling05203362015-05-27 16:07:17 +100021#include <linux/fs.h>
Ian Munsief204e0b2014-10-08 19:55:02 +110022#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/reg.h>
Michael Neulingec249dd2015-05-27 16:07:16 +100025#include <misc/cxl-base.h>
Ian Munsief204e0b2014-10-08 19:55:02 +110026
Philippe Bergheaudb8102532016-06-23 15:03:53 +020027#include <misc/cxl.h>
Ian Munsief204e0b2014-10-08 19:55:02 +110028#include <uapi/misc/cxl.h>
29
30extern uint cxl_verbose;
31
32#define CXL_TIMEOUT 5
33
34/*
35 * Bump version each time a user API change is made, whether it is
36 * backwards compatible ot not.
37 */
Philippe Bergheaudb8102532016-06-23 15:03:53 +020038#define CXL_API_VERSION 3
Ian Munsief204e0b2014-10-08 19:55:02 +110039#define CXL_API_VERSION_COMPATIBLE 1
40
41/*
42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
43 *
44 * At the end of the day, I'm not married to using typedef here, but it might
45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
47 *
48 * I'm quite happy if these are changed back to #defines before upstreaming, it
49 * should be little more than a regexp search+replace operation in this file.
50 */
51typedef struct {
52 const int x;
53} cxl_p1_reg_t;
54typedef struct {
55 const int x;
56} cxl_p1n_reg_t;
57typedef struct {
58 const int x;
59} cxl_p2n_reg_t;
60#define cxl_reg_off(reg) \
61 (reg.x)
62
63/* Memory maps. Ref CXL Appendix A */
64
65/* PSL Privilege 1 Memory Map */
Christophe Lombardf24be422017-04-12 16:34:07 +020066/* Configuration and Control area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +110067static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
70static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
71static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
72/* Downloading */
73static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
74static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
75
Christophe Lombardabd1d992017-04-07 16:11:58 +020076/* PSL Lookaside Buffer Management Area - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +110077static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
78static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
79static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
80static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
81static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
82static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
83
84/* 0x00C0:7EFF Implementation dependent area */
Christophe Lombardabd1d992017-04-07 16:11:58 +020085/* PSL registers - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +110086static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
87static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
Philippe Bergheaud390fd592015-08-28 09:37:36 +020088static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
Ian Munsief204e0b2014-10-08 19:55:02 +110089static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
90static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
Philippe Bergheaud390fd592015-08-28 09:37:36 +020091static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
Ian Munsief204e0b2014-10-08 19:55:02 +110092static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
93static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
94static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
Frederic Barrat6d382612016-05-24 03:39:18 +100096/* XSL registers (Mellanox CX4) */
97static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
98static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
99static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
100static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
Christophe Lombardf24be422017-04-12 16:34:07 +0200101/* PSL registers - CAIA 2 */
102static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
103static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
104static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
105static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};
106static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
107static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
108static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
109static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
110static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
111static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
112static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
113static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
114static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
115static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
116static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
117static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
118
Ian Munsief204e0b2014-10-08 19:55:02 +1100119/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
120/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
121
122/* PSL Slice Privilege 1 Memory Map */
Christophe Lombardf24be422017-04-12 16:34:07 +0200123/* Configuration Area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100124static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
125static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
126static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
127static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
128static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
129static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
Christophe Lombardabd1d992017-04-07 16:11:58 +0200130/* Memory Management and Lookaside Buffer Management - CAIA 1*/
Ian Munsief204e0b2014-10-08 19:55:02 +1100131static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
Christophe Lombardf24be422017-04-12 16:34:07 +0200132/* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100133static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
Christophe Lombardf24be422017-04-12 16:34:07 +0200134/* Pointer Area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100135static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
136static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
137static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
Christophe Lombardf24be422017-04-12 16:34:07 +0200138/* Control Area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100139static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
140static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
141static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
142static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
Christophe Lombardf24be422017-04-12 16:34:07 +0200143/* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100144static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
145static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
Christophe Lombardabd1d992017-04-07 16:11:58 +0200146/* 0xC0:FF Implementation Dependent Area - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100147static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
148static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
149static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
150static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
151
152/* PSL Slice Privilege 2 Memory Map */
Christophe Lombardf24be422017-04-12 16:34:07 +0200153/* Configuration and Control Area - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100154static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
155static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
Christophe Lombardabd1d992017-04-07 16:11:58 +0200156/* Configuration and Control Area - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100157static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
158static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
159static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
160static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
Christophe Lombardabd1d992017-04-07 16:11:58 +0200161/* Configuration and Control Area - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100162static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
Christophe Lombardabd1d992017-04-07 16:11:58 +0200163/* Segment Lookaside Buffer Management - CAIA 1 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100164static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
165static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
166static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
Christophe Lombardf24be422017-04-12 16:34:07 +0200167/* Interrupt Registers - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100168static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
169static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
170static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
171static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
172static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
173static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
Christophe Lombardf24be422017-04-12 16:34:07 +0200174/* AFU Registers - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100175static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
176static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
Christophe Lombardf24be422017-04-12 16:34:07 +0200177/* Work Element Descriptor - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100178static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
179/* 0x0C0:FFF Implementation Dependent Area */
180
181#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
182#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
183#define CXL_PSL_SPAP_Size_Shift 4
184#define CXL_PSL_SPAP_V 0x0000000000000001ULL
185
Philippe Bergheaud390fd592015-08-28 09:37:36 +0200186/****** CXL_PSL_Control ****************************************************/
Frederic Barrataaa22452016-10-03 21:36:02 +0200187#define CXL_PSL_Control_tb (0x1ull << (63-63))
188#define CXL_PSL_Control_Fr (0x1ull << (63-31))
189#define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
190#define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
Philippe Bergheaud390fd592015-08-28 09:37:36 +0200191
Ian Munsief204e0b2014-10-08 19:55:02 +1100192/****** CXL_PSL_DLCNTL *****************************************************/
193#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
194#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
195#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
196#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
197#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
198#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
199
200/****** CXL_PSL_SR_An ******************************************************/
201#define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
202#define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
203#define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
Christophe Lombardf24be422017-04-12 16:34:07 +0200204#define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
205#define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
206#define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
207#define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
Ian Munsief204e0b2014-10-08 19:55:02 +1100208#define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
209#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
210#define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
211#define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
212#define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
213#define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
214#define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
215#define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
216
Ian Munsief204e0b2014-10-08 19:55:02 +1100217/****** CXL_PSL_ID_An ****************************************************/
218#define CXL_PSL_ID_An_F (1ull << (63-31))
219#define CXL_PSL_ID_An_L (1ull << (63-30))
220
Philippe Bergheaud6e0c50f2016-07-05 13:08:06 +0200221/****** CXL_PSL_SERR_An ****************************************************/
222#define CXL_PSL_SERR_An_afuto (1ull << (63-0))
223#define CXL_PSL_SERR_An_afudis (1ull << (63-1))
224#define CXL_PSL_SERR_An_afuov (1ull << (63-2))
225#define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
226#define CXL_PSL_SERR_An_badctx (1ull << (63-4))
227#define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
228#define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
229#define CXL_PSL_SERR_An_afupar (1ull << (63-7))
230#define CXL_PSL_SERR_An_afudup (1ull << (63-8))
231#define CXL_PSL_SERR_An_AE (1ull << (63-30))
232
Ian Munsief204e0b2014-10-08 19:55:02 +1100233/****** CXL_PSL_SCNTL_An ****************************************************/
234#define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
235/* Programming Modes: */
236#define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
237#define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
238#define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
239#define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
240#define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
241#define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
242/* Purge Status (ro) */
243#define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
244#define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
245#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
246/* Purge */
247#define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
248/* Suspend Status (ro) */
249#define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
250#define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
251#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
252/* Suspend Control */
253#define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
254
255/* AFU Slice Enable Status (ro) */
256#define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
257#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
258#define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
259/* AFU Slice Enable */
260#define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
261/* AFU Slice Reset status (ro) */
262#define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
263#define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
264#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
265/* AFU Slice Reset */
266#define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
267
268/****** CXL_SSTP0/1_An ******************************************************/
269/* These top bits are for the segment that CONTAINS the segment table */
270#define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
271#define CXL_SSTP0_An_KS (1ull << (63-2))
272#define CXL_SSTP0_An_KP (1ull << (63-3))
273#define CXL_SSTP0_An_N (1ull << (63-4))
274#define CXL_SSTP0_An_L (1ull << (63-5))
275#define CXL_SSTP0_An_C (1ull << (63-6))
276#define CXL_SSTP0_An_TA (1ull << (63-7))
277#define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
278/* And finally, the virtual address & size of the segment table: */
279#define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
280#define CXL_SSTP0_An_SegTableSize_MASK \
281 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
282#define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
283#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
284#define CXL_SSTP1_An_V (1ull << (63-63))
285
Christophe Lombardabd1d992017-04-07 16:11:58 +0200286/****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
Ian Munsief204e0b2014-10-08 19:55:02 +1100287/* write: */
288#define CXL_SLBIE_C PPC_BIT(36) /* Class */
289#define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
290#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
291#define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
292/* read: */
293#define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
294#define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
295
Christophe Lombardabd1d992017-04-07 16:11:58 +0200296/****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
Ian Munsief204e0b2014-10-08 19:55:02 +1100297#define CXL_TLB_SLB_P (1ull) /* Pending (read) */
298
Christophe Lombardabd1d992017-04-07 16:11:58 +0200299/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
Ian Munsief204e0b2014-10-08 19:55:02 +1100300#define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
301#define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
302#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
303
304/****** CXL_PSL_AFUSEL ******************************************************/
305#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
306
Christophe Lombardabd1d992017-04-07 16:11:58 +0200307/****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
Ian Munsief204e0b2014-10-08 19:55:02 +1100308#define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
309#define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
310#define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
311#define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
312#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
313#define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
314#define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
315#define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
Michael Neuling2bc79ff2016-04-22 14:57:49 +1000316#define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
Ian Munsief204e0b2014-10-08 19:55:02 +1100317/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
318#define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
319#define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
320#define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
321#define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
322#define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
323
Christophe Lombardf24be422017-04-12 16:34:07 +0200324/****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
325#define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
326#define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
327#define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
328#define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
329#define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
330#define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
331/*
332 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
333 * Status (0:7) Encoding
334 */
335#define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
336#define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */
337#define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */
338#define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */
339#define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */
340#define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */
341#define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */
342
Ian Munsief204e0b2014-10-08 19:55:02 +1100343/****** CXL_PSL_TFC_An ******************************************************/
344#define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
345#define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
346#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
347#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
348
Christophe Lombardf24be422017-04-12 16:34:07 +0200349/****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
350#define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
351#define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
352#define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
353#define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
354#define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
355#define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
356
Ian Munsief204e0b2014-10-08 19:55:02 +1100357/* cxl_process_element->software_status */
358#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
359#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
360#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
361#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
362
Ian Munsied6a6af22014-12-08 19:17:59 +1100363/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
364 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
365 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
366 * of the hang pulse frequency.
367 */
368#define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
369
Ian Munsief204e0b2014-10-08 19:55:02 +1100370/* SPA->sw_command_status */
371#define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
372#define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
373#define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
374#define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
375#define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
376#define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
377#define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
378#define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
379#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
380#define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
381#define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
382#define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
383#define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
384#define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
385#define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
386#define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
387
388#define CXL_MAX_SLICES 4
389#define MAX_AFU_MMIO_REGS 3
390
Ian Munsief204e0b2014-10-08 19:55:02 +1100391#define CXL_MODE_TIME_SLICED 0x4
392#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
393
Christophe Lombard594ff7d2016-03-04 12:26:38 +0100394#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
395#define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
396#define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
397
Ian Munsief204e0b2014-10-08 19:55:02 +1100398enum cxl_context_status {
399 CLOSED,
400 OPENED,
401 STARTED
402};
403
404enum prefault_modes {
405 CXL_PREFAULT_NONE,
406 CXL_PREFAULT_WED,
407 CXL_PREFAULT_ALL,
408};
409
Christophe Lombard47528762016-03-04 12:26:37 +0100410enum cxl_attrs {
411 CXL_ADAPTER_ATTRS,
412 CXL_AFU_MASTER_ATTRS,
413 CXL_AFU_ATTRS,
414};
415
Ian Munsief204e0b2014-10-08 19:55:02 +1100416struct cxl_sste {
417 __be64 esid_data;
418 __be64 vsid_data;
419};
420
421#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
422#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
423
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100424struct cxl_afu_native {
Ian Munsief204e0b2014-10-08 19:55:02 +1100425 void __iomem *p1n_mmio;
Ian Munsief204e0b2014-10-08 19:55:02 +1100426 void __iomem *afu_desc_mmio;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100427 irq_hw_number_t psl_hwirq;
428 unsigned int psl_virq;
Ian Munsief204e0b2014-10-08 19:55:02 +1100429 struct mutex spa_mutex;
Ian Munsief204e0b2014-10-08 19:55:02 +1100430 /*
431 * Only the first part of the SPA is used for the process element
432 * linked list. The only other part that software needs to worry about
433 * is sw_command_status, which we store a separate pointer to.
434 * Everything else in the SPA is only used by hardware
435 */
436 struct cxl_process_element *spa;
437 __be64 *sw_command_status;
438 unsigned int spa_size;
439 int spa_order;
440 int spa_max_procs;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100441 u64 pp_offset;
442};
443
444struct cxl_afu_guest {
Christophe Lombard266eab82016-04-22 15:39:22 +0200445 struct cxl_afu *parent;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100446 u64 handle;
447 phys_addr_t p2n_phys;
448 u64 p2n_size;
449 int max_ints;
Christophe Lombard266eab82016-04-22 15:39:22 +0200450 bool handle_err;
451 struct delayed_work work_err;
Christophe Lombard0d400f72016-03-04 12:26:41 +0100452 int previous_state;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100453};
454
455struct cxl_afu {
456 struct cxl_afu_native *native;
457 struct cxl_afu_guest *guest;
458 irq_hw_number_t serr_hwirq;
459 unsigned int serr_virq;
460 char *psl_irq_name;
461 char *err_irq_name;
462 void __iomem *p2n_mmio;
463 phys_addr_t psn_phys;
464 u64 pp_size;
465
466 struct cxl *adapter;
467 struct device dev;
468 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
469 struct device *chardev_s, *chardev_m, *chardev_d;
470 struct idr contexts_idr;
471 struct dentry *debugfs;
472 struct mutex contexts_lock;
473 spinlock_t afu_cntl_lock;
Andrew Donnellan171ed0f2017-02-06 12:07:17 +1100474
475 /* -1: AFU deconfigured/locked, >= 0: number of readers */
476 atomic_t configured_state;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100477
478 /* AFU error buffer fields and bin attribute for sysfs */
479 u64 eb_len, eb_offset;
480 struct bin_attribute attr_eb;
Ian Munsief204e0b2014-10-08 19:55:02 +1100481
Michael Neuling6f7f0b32015-05-27 16:07:18 +1000482 /* pointer to the vphb */
483 struct pci_controller *phb;
484
Ian Munsief204e0b2014-10-08 19:55:02 +1100485 int pp_irqs;
486 int irqs_max;
487 int num_procs;
488 int max_procs_virtualised;
489 int slice;
490 int modes_supported;
491 int current_mode;
Ian Munsieb087e612015-02-04 19:09:01 +1100492 int crs_num;
493 u64 crs_len;
494 u64 crs_offset;
495 struct list_head crs;
Ian Munsief204e0b2014-10-08 19:55:02 +1100496 enum prefault_modes prefault_mode;
497 bool psa;
498 bool pp_psa;
499 bool enabled;
500};
501
Michael Neuling80fa93f2014-11-14 18:09:28 +1100502
503struct cxl_irq_name {
504 struct list_head list;
505 char *name;
506};
507
Christophe Lombard14baf4d2016-03-04 12:26:36 +0100508struct irq_avail {
509 irq_hw_number_t offset;
510 irq_hw_number_t range;
511 unsigned long *bitmap;
512};
513
Ian Munsief204e0b2014-10-08 19:55:02 +1100514/*
515 * This is a cxl context. If the PSL is in dedicated mode, there will be one
516 * of these per AFU. If in AFU directed there can be lots of these.
517 */
518struct cxl_context {
519 struct cxl_afu *afu;
520
521 /* Problem state MMIO */
522 phys_addr_t psn_phys;
523 u64 psn_size;
524
Ian Munsieb1234292014-12-08 19:18:01 +1100525 /* Used to unmap any mmaps when force detaching */
526 struct address_space *mapping;
527 struct mutex mapping_lock;
Ian Munsied9232a32015-07-23 16:43:56 +1000528 struct page *ff_page;
529 bool mmio_err_ff;
Ian Munsie55e07662015-08-27 19:50:19 +1000530 bool kernelapi;
Ian Munsieb1234292014-12-08 19:18:01 +1100531
Ian Munsief204e0b2014-10-08 19:55:02 +1100532 spinlock_t sste_lock; /* Protects segment table entries */
533 struct cxl_sste *sstp;
534 u64 sstp0, sstp1;
535 unsigned int sst_size, sst_lru;
536
537 wait_queue_head_t wq;
Vaibhav Jain7b8ad492015-11-24 16:26:18 +0530538 /* use mm context associated with this pid for ds faults */
Ian Munsief204e0b2014-10-08 19:55:02 +1100539 struct pid *pid;
540 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
541 /* Only used in PR mode */
542 u64 process_token;
543
Michael Neulingad42de82016-06-24 08:47:07 +0200544 /* driver private data */
545 void *priv;
546
Ian Munsief204e0b2014-10-08 19:55:02 +1100547 unsigned long *irq_bitmap; /* Accessed from IRQ context */
548 struct cxl_irq_ranges irqs;
Michael Neuling80fa93f2014-11-14 18:09:28 +1100549 struct list_head irq_names;
Ian Munsief204e0b2014-10-08 19:55:02 +1100550 u64 fault_addr;
551 u64 fault_dsisr;
552 u64 afu_err;
553
554 /*
555 * This status and it's lock pretects start and detach context
556 * from racing. It also prevents detach from racing with
557 * itself
558 */
559 enum cxl_context_status status;
560 struct mutex status_mutex;
561
562
563 /* XXX: Is it possible to need multiple work items at once? */
564 struct work_struct fault_work;
565 u64 dsisr;
566 u64 dar;
567
568 struct cxl_process_element *elem;
569
Christophe Lombard14baf4d2016-03-04 12:26:36 +0100570 /*
571 * pe is the process element handle, assigned by this driver when the
572 * context is initialized.
573 *
574 * external_pe is the PE shown outside of cxl.
575 * On bare-metal, pe=external_pe, because we decide what the handle is.
576 * In a guest, we only find out about the pe used by pHyp when the
577 * context is attached, and that's the value we want to report outside
578 * of cxl.
579 */
580 int pe;
581 int external_pe;
582
Ian Munsief204e0b2014-10-08 19:55:02 +1100583 u32 irq_count;
584 bool pe_inserted;
585 bool master;
586 bool kernel;
Ian Munsie7a0d85d2016-05-06 17:46:36 +1000587 bool real_mode;
Ian Munsief204e0b2014-10-08 19:55:02 +1100588 bool pending_irq;
589 bool pending_fault;
590 bool pending_afu_err;
Ian Munsie8ac75b92015-05-08 22:55:18 +1000591
Philippe Bergheaudb8102532016-06-23 15:03:53 +0200592 /* Used by AFU drivers for driver specific event delivery */
593 struct cxl_afu_driver_ops *afu_driver_ops;
594 atomic_t afu_driver_events;
595
Ian Munsie8ac75b92015-05-08 22:55:18 +1000596 struct rcu_head rcu;
Ian Munsiecbce0912016-07-14 07:17:09 +1000597
598 /*
599 * Only used when more interrupts are allocated via
600 * pci_enable_msix_range than are supported in the default context, to
601 * use additional contexts to overcome the limitation. i.e. Mellanox
602 * CX4 only:
603 */
604 struct list_head extra_irq_contexts;
Christophe Lombard6dd2d232017-04-07 16:11:55 +0200605
606 struct mm_struct *mm;
Ian Munsief204e0b2014-10-08 19:55:02 +1100607};
608
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200609struct cxl_irq_info;
610
Frederic Barrat6d382612016-05-24 03:39:18 +1000611struct cxl_service_layer_ops {
612 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200613 int (*invalidate_all)(struct cxl *adapter);
Frederic Barrat6d382612016-05-24 03:39:18 +1000614 int (*afu_regs_init)(struct cxl_afu *afu);
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200615 int (*sanitise_afu_regs)(struct cxl_afu *afu);
Frederic Barrat6d382612016-05-24 03:39:18 +1000616 int (*register_serr_irq)(struct cxl_afu *afu);
617 void (*release_serr_irq)(struct cxl_afu *afu);
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200618 irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
619 irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
620 int (*activate_dedicated_process)(struct cxl_afu *afu);
621 int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
622 int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
623 void (*update_dedicated_ivtes)(struct cxl_context *ctx);
624 void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
625 void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
Frederic Barrat6d382612016-05-24 03:39:18 +1000626 void (*psl_irq_dump_registers)(struct cxl_context *ctx);
627 void (*err_irq_dump_registers)(struct cxl *adapter);
628 void (*debugfs_stop_trace)(struct cxl *adapter);
629 void (*write_timebase_ctrl)(struct cxl *adapter);
630 u64 (*timebase_read)(struct cxl *adapter);
Ian Munsieb385c9e2016-06-08 15:09:54 +1000631 int capi_mode;
Ian Munsie5e7823c2016-07-01 02:50:40 +1000632 bool needs_reset_before_disable;
Frederic Barrat6d382612016-05-24 03:39:18 +1000633};
634
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100635struct cxl_native {
636 u64 afu_desc_off;
637 u64 afu_desc_size;
Ian Munsief204e0b2014-10-08 19:55:02 +1100638 void __iomem *p1_mmio;
639 void __iomem *p2_mmio;
640 irq_hw_number_t err_hwirq;
641 unsigned int err_virq;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100642 u64 ps_off;
Frederic Barrat6d382612016-05-24 03:39:18 +1000643 const struct cxl_service_layer_ops *sl_ops;
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100644};
645
646struct cxl_guest {
647 struct platform_device *pdev;
648 int irq_nranges;
649 struct cdev cdev;
650 irq_hw_number_t irq_base_offset;
651 struct irq_avail *irq_avail;
652 spinlock_t irq_alloc_lock;
653 u64 handle;
654 char *status;
655 u16 vendor;
656 u16 device;
657 u16 subsystem_vendor;
658 u16 subsystem;
659};
660
661struct cxl {
662 struct cxl_native *native;
663 struct cxl_guest *guest;
Ian Munsief204e0b2014-10-08 19:55:02 +1100664 spinlock_t afu_list_lock;
665 struct cxl_afu *afu[CXL_MAX_SLICES];
666 struct device dev;
667 struct dentry *trace;
668 struct dentry *psl_err_chk;
669 struct dentry *debugfs;
Michael Neuling80fa93f2014-11-14 18:09:28 +1100670 char *irq_name;
Ian Munsief204e0b2014-10-08 19:55:02 +1100671 struct bin_attribute cxl_attr;
672 int adapter_num;
673 int user_irqs;
Andrew Donnellan16479332016-07-28 15:39:41 +1000674 int min_pe;
Ian Munsief204e0b2014-10-08 19:55:02 +1100675 u64 ps_size;
676 u16 psl_rev;
677 u16 base_image;
678 u8 vsec_status;
679 u8 caia_major;
680 u8 caia_minor;
681 u8 slices;
682 bool user_image_loaded;
683 bool perst_loads_image;
684 bool perst_select_user;
Daniel Axtens13e68d82015-08-14 17:41:25 +1000685 bool perst_same_image;
Frederic Barrate009a7e2016-03-21 14:32:48 -0500686 bool psl_timebase_synced;
Vaibhav Jain70b565b2016-10-14 15:08:36 +0530687
688 /*
689 * number of contexts mapped on to this card. Possible values are:
690 * >0: Number of contexts mapped and new one can be mapped.
691 * 0: No active contexts and new ones can be mapped.
692 * -1: No contexts mapped and new ones cannot be mapped.
693 */
694 atomic_t contexts_num;
Ian Munsief204e0b2014-10-08 19:55:02 +1100695};
696
Frederic Barrat2b04cf32016-03-04 12:26:29 +0100697int cxl_pci_alloc_one_irq(struct cxl *adapter);
698void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
699int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
700void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
701int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
Ryan Grimm4beb5422015-01-19 11:52:48 -0600702int cxl_update_image_control(struct cxl *adapter);
Frederic Barrat2b04cf32016-03-04 12:26:29 +0100703int cxl_pci_reset(struct cxl *adapter);
704void cxl_pci_release_afu(struct device *dev);
Frederic Barratd601ea92016-03-04 12:26:40 +0100705ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
Ian Munsief204e0b2014-10-08 19:55:02 +1100706
Christophe Lombardf24be422017-04-12 16:34:07 +0200707/* common == phyp + powernv - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100708struct cxl_process_element_common {
709 __be32 tid;
710 __be32 pid;
711 __be64 csrp;
Christophe Lombardf24be422017-04-12 16:34:07 +0200712 union {
713 struct {
714 __be64 aurp0;
715 __be64 aurp1;
716 __be64 sstp0;
717 __be64 sstp1;
718 } psl8; /* CAIA 1 */
719 struct {
720 u8 reserved2[8];
721 u8 reserved3[8];
722 u8 reserved4[8];
723 u8 reserved5[8];
724 } psl9; /* CAIA 2 */
725 } u;
Ian Munsief204e0b2014-10-08 19:55:02 +1100726 __be64 amr;
Christophe Lombardf24be422017-04-12 16:34:07 +0200727 u8 reserved6[4];
Ian Munsief204e0b2014-10-08 19:55:02 +1100728 __be64 wed;
729} __packed;
730
Christophe Lombardf24be422017-04-12 16:34:07 +0200731/* just powernv - CAIA 1&2 */
Ian Munsief204e0b2014-10-08 19:55:02 +1100732struct cxl_process_element {
733 __be64 sr;
734 __be64 SPOffset;
Christophe Lombardf24be422017-04-12 16:34:07 +0200735 union {
736 __be64 sdr; /* CAIA 1 */
737 u8 reserved1[8]; /* CAIA 2 */
738 } u;
Ian Munsief204e0b2014-10-08 19:55:02 +1100739 __be64 haurp;
740 __be32 ctxtime;
741 __be16 ivte_offsets[4];
742 __be16 ivte_ranges[4];
743 __be32 lpid;
744 struct cxl_process_element_common common;
745 __be32 software_state;
746} __packed;
747
Christophe Lombard0d400f72016-03-04 12:26:41 +0100748static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000749{
750 struct pci_dev *pdev;
751
Frederic Barratea2d1f92016-03-04 12:26:30 +0100752 if (cpu_has_feature(CPU_FTR_HVMODE)) {
753 pdev = to_pci_dev(cxl->dev.parent);
754 return !pci_channel_offline(pdev);
755 }
756 return true;
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000757}
758
Ian Munsief204e0b2014-10-08 19:55:02 +1100759static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
760{
761 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100762 return cxl->native->p1_mmio + cxl_reg_off(reg);
Ian Munsief204e0b2014-10-08 19:55:02 +1100763}
764
Daniel Axtens588b34b2015-08-14 17:41:17 +1000765static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
766{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100767 if (likely(cxl_adapter_link_ok(cxl, NULL)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000768 out_be64(_cxl_p1_addr(cxl, reg), val);
Daniel Axtens588b34b2015-08-14 17:41:17 +1000769}
770
771static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
772{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100773 if (likely(cxl_adapter_link_ok(cxl, NULL)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000774 return in_be64(_cxl_p1_addr(cxl, reg));
775 else
776 return ~0ULL;
Daniel Axtens588b34b2015-08-14 17:41:17 +1000777}
Ian Munsief204e0b2014-10-08 19:55:02 +1100778
779static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
780{
781 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
Christophe Lombardcbffa3a2016-03-04 12:26:35 +0100782 return afu->native->p1n_mmio + cxl_reg_off(reg);
Ian Munsief204e0b2014-10-08 19:55:02 +1100783}
784
Daniel Axtens588b34b2015-08-14 17:41:17 +1000785static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
786{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100787 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000788 out_be64(_cxl_p1n_addr(afu, reg), val);
Daniel Axtens588b34b2015-08-14 17:41:17 +1000789}
790
791static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
792{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100793 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000794 return in_be64(_cxl_p1n_addr(afu, reg));
795 else
796 return ~0ULL;
Daniel Axtens588b34b2015-08-14 17:41:17 +1000797}
Ian Munsief204e0b2014-10-08 19:55:02 +1100798
799static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
800{
801 return afu->p2n_mmio + cxl_reg_off(reg);
802}
803
Daniel Axtens588b34b2015-08-14 17:41:17 +1000804static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
805{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100806 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000807 out_be64(_cxl_p2n_addr(afu, reg), val);
Daniel Axtens588b34b2015-08-14 17:41:17 +1000808}
Ian Munsief204e0b2014-10-08 19:55:02 +1100809
Daniel Axtens588b34b2015-08-14 17:41:17 +1000810static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
811{
Christophe Lombard0d400f72016-03-04 12:26:41 +0100812 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
Daniel Axtens0b3f9c72015-08-14 17:41:18 +1000813 return in_be64(_cxl_p2n_addr(afu, reg));
814 else
815 return ~0ULL;
Daniel Axtens588b34b2015-08-14 17:41:17 +1000816}
Ian Munsieb087e612015-02-04 19:09:01 +1100817
Christophe Lombardabd1d992017-04-07 16:11:58 +0200818static inline bool cxl_is_power8(void)
819{
820 if ((pvr_version_is(PVR_POWER8E)) ||
821 (pvr_version_is(PVR_POWER8NVL)) ||
822 (pvr_version_is(PVR_POWER8)))
823 return true;
824 return false;
825}
826
Christophe Lombardf24be422017-04-12 16:34:07 +0200827static inline bool cxl_is_power9(void)
828{
829 /* intermediate solution */
830 if (!cxl_is_power8() &&
831 (cpu_has_feature(CPU_FTRS_POWER9) ||
832 cpu_has_feature(CPU_FTR_POWER9_DD1)))
833 return true;
834 return false;
835}
836
Christophe Lombardabd1d992017-04-07 16:11:58 +0200837static inline bool cxl_is_psl8(struct cxl_afu *afu)
838{
839 if (afu->adapter->caia_major == 1)
840 return true;
841 return false;
842}
843
Christophe Lombardf24be422017-04-12 16:34:07 +0200844static inline bool cxl_is_psl9(struct cxl_afu *afu)
845{
846 if (afu->adapter->caia_major == 2)
847 return true;
848 return false;
849}
850
Frederic Barrat2b04cf32016-03-04 12:26:29 +0100851ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
Vaibhav Jaine36f6fe2015-05-22 10:56:05 +0530852 loff_t off, size_t count);
853
Ian Munsiea19bd792016-07-14 07:17:04 +1000854/* Internal functions wrapped in cxl_base to allow PHB to call them */
855bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
856void _cxl_pci_disable_device(struct pci_dev *dev);
Ian Munsiecbce0912016-07-14 07:17:09 +1000857int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
Ian Munsiea2f67d52016-07-14 07:17:10 +1000858int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
859void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsieb087e612015-02-04 19:09:01 +1100860
Ian Munsief204e0b2014-10-08 19:55:02 +1100861struct cxl_calls {
862 void (*cxl_slbia)(struct mm_struct *mm);
Ian Munsiea19bd792016-07-14 07:17:04 +1000863 bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
864 void (*cxl_pci_disable_device)(struct pci_dev *dev);
Ian Munsiecbce0912016-07-14 07:17:09 +1000865 int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
Ian Munsiea2f67d52016-07-14 07:17:10 +1000866 int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
867 void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
Ian Munsiea19bd792016-07-14 07:17:04 +1000868
Ian Munsief204e0b2014-10-08 19:55:02 +1100869 struct module *owner;
870};
871int register_cxl_calls(struct cxl_calls *calls);
872void unregister_cxl_calls(struct cxl_calls *calls);
Christophe Lombard594ff7d2016-03-04 12:26:38 +0100873int cxl_update_properties(struct device_node *dn, struct property *new_prop);
Ian Munsief204e0b2014-10-08 19:55:02 +1100874
Ian Munsief204e0b2014-10-08 19:55:02 +1100875void cxl_remove_adapter_nr(struct cxl *adapter);
876
Daniel Axtens051557722015-08-14 17:41:19 +1000877void cxl_release_spa(struct cxl_afu *afu);
878
Christophe Lombard594ff7d2016-03-04 12:26:38 +0100879dev_t cxl_get_dev(void);
Ian Munsief204e0b2014-10-08 19:55:02 +1100880int cxl_file_init(void);
881void cxl_file_exit(void);
882int cxl_register_adapter(struct cxl *adapter);
883int cxl_register_afu(struct cxl_afu *afu);
884int cxl_chardev_d_afu_add(struct cxl_afu *afu);
885int cxl_chardev_m_afu_add(struct cxl_afu *afu);
886int cxl_chardev_s_afu_add(struct cxl_afu *afu);
887void cxl_chardev_afu_remove(struct cxl_afu *afu);
888
889void cxl_context_detach_all(struct cxl_afu *afu);
890void cxl_context_free(struct cxl_context *ctx);
891void cxl_context_detach(struct cxl_context *ctx);
892
893int cxl_sysfs_adapter_add(struct cxl *adapter);
894void cxl_sysfs_adapter_remove(struct cxl *adapter);
895int cxl_sysfs_afu_add(struct cxl_afu *afu);
896void cxl_sysfs_afu_remove(struct cxl_afu *afu);
897int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
898void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
899
Christophe Lombard86331862016-03-04 12:26:25 +0100900struct cxl *cxl_alloc_adapter(void);
901struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
Ian Munsief204e0b2014-10-08 19:55:02 +1100902int cxl_afu_select_best_mode(struct cxl_afu *afu);
903
Frederic Barrat2b04cf32016-03-04 12:26:29 +0100904int cxl_native_register_psl_irq(struct cxl_afu *afu);
905void cxl_native_release_psl_irq(struct cxl_afu *afu);
906int cxl_native_register_psl_err_irq(struct cxl *adapter);
907void cxl_native_release_psl_err_irq(struct cxl *adapter);
908int cxl_native_register_serr_irq(struct cxl_afu *afu);
909void cxl_native_release_serr_irq(struct cxl_afu *afu);
Ian Munsief204e0b2014-10-08 19:55:02 +1100910int afu_register_irqs(struct cxl_context *ctx, u32 count);
Michael Neuling64288322015-05-27 16:07:07 +1000911void afu_release_irqs(struct cxl_context *ctx, void *cookie);
Andrew Donnellan8dde1522015-09-30 11:58:05 +1000912void afu_irq_name_free(struct cxl_context *ctx);
Ian Munsief204e0b2014-10-08 19:55:02 +1100913
Christophe Lombardf24be422017-04-12 16:34:07 +0200914int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
Christophe Lombard64663f32017-04-07 16:11:57 +0200915int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
Christophe Lombardf24be422017-04-12 16:34:07 +0200916int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
Christophe Lombard64663f32017-04-07 16:11:57 +0200917int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
Christophe Lombardf24be422017-04-12 16:34:07 +0200918int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
Christophe Lombard64663f32017-04-07 16:11:57 +0200919int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
Christophe Lombardf24be422017-04-12 16:34:07 +0200920void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
Christophe Lombard64663f32017-04-07 16:11:57 +0200921void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200922
Andrew Donnellan39d40872017-02-01 14:22:07 +1100923#ifdef CONFIG_DEBUG_FS
924
Ian Munsief204e0b2014-10-08 19:55:02 +1100925int cxl_debugfs_init(void);
926void cxl_debugfs_exit(void);
927int cxl_debugfs_adapter_add(struct cxl *adapter);
928void cxl_debugfs_adapter_remove(struct cxl *adapter);
929int cxl_debugfs_afu_add(struct cxl_afu *afu);
930void cxl_debugfs_afu_remove(struct cxl_afu *afu);
Christophe Lombardf24be422017-04-12 16:34:07 +0200931void cxl_stop_trace_psl9(struct cxl *cxl);
Christophe Lombard64663f32017-04-07 16:11:57 +0200932void cxl_stop_trace_psl8(struct cxl *cxl);
Christophe Lombardf24be422017-04-12 16:34:07 +0200933void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
Christophe Lombard64663f32017-04-07 16:11:57 +0200934void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200935void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
Christophe Lombardf24be422017-04-12 16:34:07 +0200936void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
Christophe Lombard64663f32017-04-07 16:11:57 +0200937void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
Andrew Donnellan39d40872017-02-01 14:22:07 +1100938
939#else /* CONFIG_DEBUG_FS */
940
941static inline int __init cxl_debugfs_init(void)
942{
943 return 0;
944}
945
946static inline void cxl_debugfs_exit(void)
947{
948}
949
950static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
951{
952 return 0;
953}
954
955static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
956{
957}
958
959static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
960{
961 return 0;
962}
963
964static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
965{
966}
967
Christophe Lombardf24be422017-04-12 16:34:07 +0200968static inline void cxl_stop_trace_psl9(struct cxl *cxl)
969{
970}
971
Christophe Lombard64663f32017-04-07 16:11:57 +0200972static inline void cxl_stop_trace_psl8(struct cxl *cxl)
Andrew Donnellan39d40872017-02-01 14:22:07 +1100973{
974}
975
Christophe Lombardf24be422017-04-12 16:34:07 +0200976static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
977 struct dentry *dir)
978{
979}
980
Christophe Lombard64663f32017-04-07 16:11:57 +0200981static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
Andrew Donnellan39d40872017-02-01 14:22:07 +1100982 struct dentry *dir)
983{
984}
985
Christophe Lombardbdd2e712017-04-07 16:11:56 +0200986static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,
Andrew Donnellan39d40872017-02-01 14:22:07 +1100987 struct dentry *dir)
988{
989}
990
Christophe Lombardf24be422017-04-12 16:34:07 +0200991static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
992{
993}
994
Christophe Lombard64663f32017-04-07 16:11:57 +0200995static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
Andrew Donnellan39d40872017-02-01 14:22:07 +1100996{
997}
998
999#endif /* CONFIG_DEBUG_FS */
Ian Munsief204e0b2014-10-08 19:55:02 +11001000
1001void cxl_handle_fault(struct work_struct *work);
1002void cxl_prefault(struct cxl_context *ctx, u64 wed);
1003
1004struct cxl *get_cxl_adapter(int num);
1005int cxl_alloc_sst(struct cxl_context *ctx);
Christophe Lombard444c4ba2016-03-04 12:26:34 +01001006void cxl_dump_debug_buffer(void *addr, size_t size);
Ian Munsief204e0b2014-10-08 19:55:02 +11001007
1008void init_cxl_native(void);
1009
1010struct cxl_context *cxl_context_alloc(void);
Frederic Barratbdecf762016-11-18 23:00:31 +11001011int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
1012void cxl_context_set_mapping(struct cxl_context *ctx,
1013 struct address_space *mapping);
Ian Munsief204e0b2014-10-08 19:55:02 +11001014void cxl_context_free(struct cxl_context *ctx);
1015int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
Michael Neuling1a1a94b2015-05-27 16:07:10 +10001016unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
1017 irq_handler_t handler, void *cookie, const char *name);
1018void cxl_unmap_irq(unsigned int virq, void *cookie);
Michael Neulingeda36932015-05-27 16:07:08 +10001019int __detach_context(struct cxl_context *ctx);
Ian Munsief204e0b2014-10-08 19:55:02 +11001020
Christophe Lombard444c4ba2016-03-04 12:26:34 +01001021/*
1022 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
1023 * in PAPR.
Christophe Lombard66ef20c2017-04-07 16:11:54 +02001024 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1025 * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1026 * PSL_TID_An register in the lower 32 bits.
Christophe Lombard444c4ba2016-03-04 12:26:34 +01001027 */
Ian Munsief204e0b2014-10-08 19:55:02 +11001028struct cxl_irq_info {
1029 u64 dsisr;
1030 u64 dar;
1031 u64 dsr;
Christophe Lombard66ef20c2017-04-07 16:11:54 +02001032 u64 reserved;
Ian Munsief204e0b2014-10-08 19:55:02 +11001033 u64 afu_err;
1034 u64 errstat;
Christophe Lombard444c4ba2016-03-04 12:26:34 +01001035 u64 proc_handle;
1036 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
Ian Munsief204e0b2014-10-08 19:55:02 +11001037};
1038
Michael Neuling1a1a94b2015-05-27 16:07:10 +10001039void cxl_assign_psn_space(struct cxl_context *ctx);
Christophe Lombardf24be422017-04-12 16:34:07 +02001040int cxl_invalidate_all_psl9(struct cxl *adapter);
Christophe Lombard64663f32017-04-07 16:11:57 +02001041int cxl_invalidate_all_psl8(struct cxl *adapter);
Christophe Lombardf24be422017-04-12 16:34:07 +02001042irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
Christophe Lombard64663f32017-04-07 16:11:57 +02001043irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
Christophe Lombardbdd2e712017-04-07 16:11:56 +02001044irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
Christophe Lombard86331862016-03-04 12:26:25 +01001045int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1046 void *cookie, irq_hw_number_t *dest_hwirq,
1047 unsigned int *dest_virq, const char *name);
1048
Ian Munsief204e0b2014-10-08 19:55:02 +11001049int cxl_check_error(struct cxl_afu *afu);
1050int cxl_afu_slbia(struct cxl_afu *afu);
Frederic Barrataaa22452016-10-03 21:36:02 +02001051int cxl_data_cache_flush(struct cxl *adapter);
Ian Munsief204e0b2014-10-08 19:55:02 +11001052int cxl_afu_disable(struct cxl_afu *afu);
Ian Munsief204e0b2014-10-08 19:55:02 +11001053int cxl_psl_purge(struct cxl_afu *afu);
1054
Christophe Lombardf24be422017-04-12 16:34:07 +02001055void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
Christophe Lombard64663f32017-04-07 16:11:57 +02001056void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
Frederic Barrat6d382612016-05-24 03:39:18 +10001057void cxl_native_err_irq_dump_regs(struct cxl *adapter);
Michael Neuling6f7f0b32015-05-27 16:07:18 +10001058int cxl_pci_vphb_add(struct cxl_afu *afu);
1059void cxl_pci_vphb_remove(struct cxl_afu *afu);
Frederic Barratbdecf762016-11-18 23:00:31 +11001060void cxl_release_mapping(struct cxl_context *ctx);
Ian Munsief204e0b2014-10-08 19:55:02 +11001061
1062extern struct pci_driver cxl_pci_driver;
Christophe Lombard14baf4d2016-03-04 12:26:36 +01001063extern struct platform_driver cxl_of_driver;
Michael Neulingc358d84b2015-05-27 16:07:12 +10001064int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
Ian Munsief204e0b2014-10-08 19:55:02 +11001065
Michael Neuling05203362015-05-27 16:07:17 +10001066int afu_open(struct inode *inode, struct file *file);
1067int afu_release(struct inode *inode, struct file *file);
1068long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1069int afu_mmap(struct file *file, struct vm_area_struct *vm);
1070unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
1071ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1072extern const struct file_operations afu_fops;
1073
Christophe Lombard14baf4d2016-03-04 12:26:36 +01001074struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1075void cxl_guest_remove_adapter(struct cxl *adapter);
1076int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1077int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1078ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1079ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1080int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1081void cxl_guest_remove_afu(struct cxl_afu *afu);
1082int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1083int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1084int cxl_guest_add_chardev(struct cxl *adapter);
1085void cxl_guest_remove_chardev(struct cxl *adapter);
1086void cxl_guest_reload_module(struct cxl *adapter);
1087int cxl_of_probe(struct platform_device *pdev);
1088
Frederic Barrat5be587b2016-03-04 12:26:28 +01001089struct cxl_backend_ops {
1090 struct module *module;
1091 int (*adapter_reset)(struct cxl *adapter);
1092 int (*alloc_one_irq)(struct cxl *adapter);
1093 void (*release_one_irq)(struct cxl *adapter, int hwirq);
1094 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1095 struct cxl *adapter, unsigned int num);
1096 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1097 struct cxl *adapter);
1098 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1099 unsigned int virq);
1100 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1101 u64 dsisr, u64 errstat);
1102 irqreturn_t (*psl_interrupt)(int irq, void *data);
1103 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
Michael Neuling2bc79ff2016-04-22 14:57:49 +10001104 void (*irq_wait)(struct cxl_context *ctx);
Frederic Barrat5be587b2016-03-04 12:26:28 +01001105 int (*attach_process)(struct cxl_context *ctx, bool kernel,
1106 u64 wed, u64 amr);
1107 int (*detach_process)(struct cxl_context *ctx);
Ian Munsie292841b2016-05-24 02:14:05 +10001108 void (*update_ivtes)(struct cxl_context *ctx);
Christophe Lombard47528762016-03-04 12:26:37 +01001109 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
Christophe Lombard0d400f72016-03-04 12:26:41 +01001110 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
Frederic Barrat5be587b2016-03-04 12:26:28 +01001111 void (*release_afu)(struct device *dev);
1112 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1113 loff_t off, size_t count);
1114 int (*afu_check_and_enable)(struct cxl_afu *afu);
1115 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1116 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1117 int (*afu_reset)(struct cxl_afu *afu);
1118 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1119 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1120 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1121 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
Frederic Barratd601ea92016-03-04 12:26:40 +01001122 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1123 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1124 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1125 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
Frederic Barrat5be587b2016-03-04 12:26:28 +01001126};
1127extern const struct cxl_backend_ops cxl_native_ops;
Christophe Lombard14baf4d2016-03-04 12:26:36 +01001128extern const struct cxl_backend_ops cxl_guest_ops;
Frederic Barrat5be587b2016-03-04 12:26:28 +01001129extern const struct cxl_backend_ops *cxl_ops;
1130
Vaibhav Jain17eb3ee2016-02-29 11:10:53 +05301131/* check if the given pci_dev is on the the cxl vphb bus */
1132bool cxl_pci_is_vphb_device(struct pci_dev *dev);
Philippe Bergheaud6e0c50f2016-07-05 13:08:06 +02001133
1134/* decode AFU error bits in the PSL register PSL_SERR_An */
1135void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
Vaibhav Jain70b565b2016-10-14 15:08:36 +05301136
1137/*
1138 * Increments the number of attached contexts on an adapter.
1139 * In case an adapter_context_lock is taken the return -EBUSY.
1140 */
1141int cxl_adapter_context_get(struct cxl *adapter);
1142
1143/* Decrements the number of attached contexts on an adapter */
1144void cxl_adapter_context_put(struct cxl *adapter);
1145
1146/* If no active contexts then prevents contexts from being attached */
1147int cxl_adapter_context_lock(struct cxl *adapter);
1148
1149/* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1150void cxl_adapter_context_unlock(struct cxl *adapter);
1151
Christophe Lombard6dd2d232017-04-07 16:11:55 +02001152/* Increases the reference count to "struct mm_struct" */
1153void cxl_context_mm_count_get(struct cxl_context *ctx);
1154
1155/* Decrements the reference count to "struct mm_struct" */
1156void cxl_context_mm_count_put(struct cxl_context *ctx);
1157
Ian Munsief204e0b2014-10-08 19:55:02 +11001158#endif