Michael Williamson | f2dbb6d | 2010-09-02 13:58:07 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * Critical Link MityOMAP-L138 SoM |
| 3 | * |
| 4 | * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of |
| 8 | * any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/console.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/mtd/partitions.h> |
| 16 | |
| 17 | #include <asm/mach-types.h> |
| 18 | #include <asm/mach/arch.h> |
| 19 | #include <mach/common.h> |
| 20 | #include <mach/cp_intc.h> |
| 21 | #include <mach/da8xx.h> |
| 22 | #include <mach/nand.h> |
| 23 | #include <mach/mux.h> |
| 24 | |
| 25 | #define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */ |
| 26 | #define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ |
| 27 | |
| 28 | /* |
| 29 | * MityDSP-L138 includes a 256 MByte large-page NAND flash |
| 30 | * (128K blocks). |
| 31 | */ |
| 32 | struct mtd_partition mityomapl138_nandflash_partition[] = { |
| 33 | { |
| 34 | .name = "rootfs", |
| 35 | .offset = 0, |
| 36 | .size = SZ_128M, |
| 37 | .mask_flags = 0, /* MTD_WRITEABLE, */ |
| 38 | }, |
| 39 | { |
| 40 | .name = "homefs", |
| 41 | .offset = MTDPART_OFS_APPEND, |
| 42 | .size = MTDPART_SIZ_FULL, |
| 43 | .mask_flags = 0, |
| 44 | }, |
| 45 | }; |
| 46 | |
| 47 | static struct davinci_nand_pdata mityomapl138_nandflash_data = { |
| 48 | .parts = mityomapl138_nandflash_partition, |
| 49 | .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), |
| 50 | .ecc_mode = NAND_ECC_HW, |
| 51 | .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, |
| 52 | .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ |
| 53 | }; |
| 54 | |
| 55 | static struct resource mityomapl138_nandflash_resource[] = { |
| 56 | { |
| 57 | .start = DA8XX_AEMIF_CS3_BASE, |
| 58 | .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, |
| 59 | .flags = IORESOURCE_MEM, |
| 60 | }, |
| 61 | { |
| 62 | .start = DA8XX_AEMIF_CTL_BASE, |
| 63 | .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, |
| 64 | .flags = IORESOURCE_MEM, |
| 65 | }, |
| 66 | }; |
| 67 | |
| 68 | static struct platform_device mityomapl138_nandflash_device = { |
| 69 | .name = "davinci_nand", |
| 70 | .id = 0, |
| 71 | .dev = { |
| 72 | .platform_data = &mityomapl138_nandflash_data, |
| 73 | }, |
| 74 | .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), |
| 75 | .resource = mityomapl138_nandflash_resource, |
| 76 | }; |
| 77 | |
| 78 | static struct platform_device *mityomapl138_devices[] __initdata = { |
| 79 | &mityomapl138_nandflash_device, |
| 80 | }; |
| 81 | |
| 82 | static void __init mityomapl138_setup_nand(void) |
| 83 | { |
| 84 | platform_add_devices(mityomapl138_devices, |
| 85 | ARRAY_SIZE(mityomapl138_devices)); |
| 86 | } |
| 87 | |
| 88 | static struct davinci_uart_config mityomapl138_uart_config __initdata = { |
| 89 | .enabled_uarts = 0x7, |
| 90 | }; |
| 91 | |
| 92 | static const short mityomap_mii_pins[] = { |
| 93 | DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, |
| 94 | DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, |
| 95 | DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, |
| 96 | DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, |
| 97 | DA850_MDIO_D, |
| 98 | -1 |
| 99 | }; |
| 100 | |
| 101 | static const short mityomap_rmii_pins[] = { |
| 102 | DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, |
| 103 | DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, |
| 104 | DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, |
| 105 | DA850_MDIO_D, |
| 106 | -1 |
| 107 | }; |
| 108 | |
| 109 | static void __init mityomapl138_config_emac(void) |
| 110 | { |
| 111 | void __iomem *cfg_chip3_base; |
| 112 | int ret; |
| 113 | u32 val; |
| 114 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 115 | |
| 116 | soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ |
| 117 | |
| 118 | cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); |
| 119 | val = __raw_readl(cfg_chip3_base); |
| 120 | |
| 121 | if (soc_info->emac_pdata->rmii_en) { |
| 122 | val |= BIT(8); |
| 123 | ret = davinci_cfg_reg_list(mityomap_rmii_pins); |
| 124 | pr_info("RMII PHY configured\n"); |
| 125 | } else { |
| 126 | val &= ~BIT(8); |
| 127 | ret = davinci_cfg_reg_list(mityomap_mii_pins); |
| 128 | pr_info("MII PHY configured\n"); |
| 129 | } |
| 130 | |
| 131 | if (ret) { |
| 132 | pr_warning("mii/rmii mux setup failed: %d\n", ret); |
| 133 | return; |
| 134 | } |
| 135 | |
| 136 | /* configure the CFGCHIP3 register for RMII or MII */ |
| 137 | __raw_writel(val, cfg_chip3_base); |
| 138 | |
| 139 | soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK; |
| 140 | pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); |
| 141 | soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; |
| 142 | |
| 143 | ret = da8xx_register_emac(); |
| 144 | if (ret) |
| 145 | pr_warning("emac registration failed: %d\n", ret); |
| 146 | } |
| 147 | |
| 148 | static struct davinci_pm_config da850_pm_pdata = { |
| 149 | .sleepcount = 128, |
| 150 | }; |
| 151 | |
| 152 | static struct platform_device da850_pm_device = { |
| 153 | .name = "pm-davinci", |
| 154 | .dev = { |
| 155 | .platform_data = &da850_pm_pdata, |
| 156 | }, |
| 157 | .id = -1, |
| 158 | }; |
| 159 | |
| 160 | static void __init mityomapl138_init(void) |
| 161 | { |
| 162 | int ret; |
| 163 | |
| 164 | /* for now, no special EDMA channels are reserved */ |
| 165 | ret = da850_register_edma(NULL); |
| 166 | if (ret) |
| 167 | pr_warning("edma registration failed: %d\n", ret); |
| 168 | |
| 169 | ret = da8xx_register_watchdog(); |
| 170 | if (ret) |
| 171 | pr_warning("watchdog registration failed: %d\n", ret); |
| 172 | |
| 173 | davinci_serial_init(&mityomapl138_uart_config); |
| 174 | |
| 175 | mityomapl138_setup_nand(); |
| 176 | |
| 177 | mityomapl138_config_emac(); |
| 178 | |
| 179 | ret = da8xx_register_rtc(); |
| 180 | if (ret) |
| 181 | pr_warning("rtc setup failed: %d\n", ret); |
| 182 | |
| 183 | ret = da850_register_cpufreq("pll0_sysclk3"); |
| 184 | if (ret) |
| 185 | pr_warning("cpufreq registration failed: %d\n", ret); |
| 186 | |
| 187 | ret = da8xx_register_cpuidle(); |
| 188 | if (ret) |
| 189 | pr_warning("cpuidle registration failed: %d\n", ret); |
| 190 | |
| 191 | ret = da850_register_pm(&da850_pm_device); |
| 192 | if (ret) |
| 193 | pr_warning("da850_evm_init: suspend registration failed: %d\n", |
| 194 | ret); |
| 195 | } |
| 196 | |
| 197 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
| 198 | static int __init mityomapl138_console_init(void) |
| 199 | { |
| 200 | if (!machine_is_mityomapl138()) |
| 201 | return 0; |
| 202 | |
| 203 | return add_preferred_console("ttyS", 1, "115200"); |
| 204 | } |
| 205 | console_initcall(mityomapl138_console_init); |
| 206 | #endif |
| 207 | |
| 208 | static void __init mityomapl138_map_io(void) |
| 209 | { |
| 210 | da850_init(); |
| 211 | } |
| 212 | |
| 213 | MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") |
| 214 | .phys_io = IO_PHYS, |
| 215 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, |
| 216 | .boot_params = (DA8XX_DDR_BASE + 0x100), |
| 217 | .map_io = mityomapl138_map_io, |
| 218 | .init_irq = cp_intc_init, |
| 219 | .timer = &davinci_timer, |
| 220 | .init_machine = mityomapl138_init, |
| 221 | MACHINE_END |